Abstract: A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate.

Abstract: A semiconductor chip arrangement and method is disclosed. In one embodiment, the invention provides a method for providing a semiconductor chip arrangement including providing a semiconductor chip having a first connecting area, and providing a chip carrier having a concave shaped section formed in a second connecting area. A connecting mechanism is provided between the first connecting area and the second connecting area and pressing the semiconductor chip onto the chip carrier such that the connecting mechanism positively locks the first connecting area to the concave shaped section of the second connecting area.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include placing an anisotropic conductive layer comprising at least one compliant conductive sphere on at least one interconnect structure disposed on a first substrate, applying pressure to contact the compliant conductive spheres to the at least one interconnect structure, removing a portion of the anisotropic conductive layer to expose at least one of the compliant conductive spheres; and then attaching a second substrate to the anisotropic conductive layer.

Abstract: A microelectronic package includes a carrier (110, 210, 410, 1110) having a first surface (111, 211, 411, 1111) and an opposing second surface (112, 212, 412, 1112), an adhesive layer (120, 220, 221, 520, 1220, 1221) at the first surface of the carrier, a die (130, 230, 231, 530, 531, 1230, 1231) attached to the first surface of the carrier by the adhesive layer, an encapsulation material (140, 240, 640, 1340) at the first surface of the carrier and at least partially surrounding the die and the adhesive layer, and a build-up layer (150, 250, 750, 1450) adjacent to the encapsulation material, wherein the die and the build-up layer are in direct physical contact with each other. In one embodiment the carrier is a heat spreader having a first surface and a second surface the second surface being a top surface of the microelectronic package.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: A chip module and a fabricating method thereof are provided. Firstly, a substrate is provided. Next, a chip is assembled on the substrate and electrically connected with the substrate. Afterward, a plurality of passive units is assembled on the substrate in the style of encircling the chip. Then, a first glue structure is filled between the passive units so that an encircled area is defined by the first glue structure and the passive units. Then, a second glue structure is filled in the encircled area so that the chip is covered by the second glue structure.

Abstract: A package substrate may have an improved surface structure for controlling the flow of an adhesive. The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be provided on the lower surface, clear of the passivation layer. The semiconductor package may have an indented or non-planar surface structure.

Abstract: An electronic device may include first, second, and third substrates wherein the second electronic substrate is between the first and second electronic substrates. A first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates. In addition or in an alternative, an electronic device may include a printed circuit board, a first electronic substrate on the printed circuit board, a second electronic substrate on the first electronic substrate, and a third electronic substrate on the second electronic substrate. More particularly, the first electronic substrate may be between the printed circuit board and the second electronic substrate, and the second electronic substrate may be between the first and third electronic substrates.

Abstract: A semiconductor device-composing substrate 10 has a support base 12, an interconnect layer 14 including interconnects 13, and an insulating resin layer 16. The semiconductor device-composing substrate 10 also has a mounting region D1 on which a semiconductor chip 30 is to be mounted. The insulating resin layer 16 is formed on the interconnect layer 14. Chip-connecting electrodes 17, external electrode pads 18 and the resin stopper patterns 19 are formed in the insulating resin layer 16. The chip-connecting electrodes 17 are provided in the mounting region D1. The external electrode pads 18 are provided outside the mounting region D1. The resin stopper patterns 19 are provided between the mounting region D1 and the external electrode pads 18.

Abstract: An electronic structural member or a semiconductor device having conductive bumps is provided. The conductive bump includes an organic buffer layer with an undercut structure, and the conductive bump is deformable during the bonding process so as to compensate the height difference between the conductive bumps. In addition, an adhesive is further disposed between the IC chip and the substrate, and partial adhesive fills in the undercut structure, such that not only the adhesive area can be increased to enhance the bonding force between the IC chip and the substrate, but the return force of the adhesive can be reduced.

Abstract: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation.

Abstract: A packaging apparatus is disclosed having a substrate with an interior area and a peripheral area. The substrate is configured to have an integrated circuit chip bonded to an adhesion structure located substantially within the interior area of the substrate. The substrate is further configured to have the integrated circuit chip electrically coupled to either the interior area on a distal surface of the substrate or the peripheral area on a proximate side of the substrate through a conductive structure. The adhesion structure includes a bonding area configured to accept an adhesive layer formed between the integrated circuit chip and the interior area of the substrate, and at least one protrusion structure being formed substantially within the bonding area of the substrate and configured to define a gap between the integrated circuit chip and the interior area of the substrate.

Abstract: The present invention is to provide an adhesive resin composition for use in preparing an adhesive in the form of a film which is excellent in the adhesiveness at a low temperature and in the heat resistance, an adhesive in the form of a film comprising the adhesive resin composition, and a semiconductor device using the adhesive in the form of a film.

Abstract: A dicing die adhesive film for semiconductor of the present invention has a 3-layered structure including a first adhesive layer attached on the back of a semiconductor wafer; a second adhesive layer attached onto the first adhesive layer; and a dicing film attached onto the second adhesive layer, and therefore has an advantage that it can ensure reliability of the semiconductor packaging process since it may prevent the die-flying phenomenon and the poor pickup of the die in the dicing process and maintain a sufficient adhesive force between the die and the substrate upon die boding.

Abstract: A semiconductor package with a heat sink and a method for fabricating the same are proposed. A first adhesive of a low Young's modulus is disposed on a corner region of a heat sink mounting area of a substrate. A second adhesive of a high Young's modulus is disposed on the heat sink mounting area except the corner region. The heat sink is mounted on the heat sink mounting area and thereby secured in position to the substrate, by the first and second adhesives. The disposition of the first and second adhesives of different Young's moduli not only prevents detachment of the heat sink from the substrate, but also controls the flatness of the heat sink. The prevent invention does not affect the appearance of the semiconductor package and its ensuing assembly process.

Abstract: A composite conductive film and a semiconductor package using such film are provided. The composite conductive film is formed of a polymer-matrix and a plurality of nano-sized conductive lines is provided. The composite conductive film has low resistance, to connect between a fine-pitch chip and a chip in a low temperature and low pressure condition. The conductive lines are parally arranged and spaced apart from each other, to provide anisotropic conductivity. The present conductive film can be served as an electrical connection between a fine-pitch chip and a chip or a fine-pitch chip and a substrate.

Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.

Abstract: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact pads disposed on the surface of a chip package.

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract: The present invention relates to an electronic module having a layer of adhesive between metallic surfaces of components of the module. The metallic surfaces are arranged facing one another. The adhesive of the layer of adhesive includes agglomerates of nanoparticles, which form paths, surrounded by an adhesive base composition, in the adhesive base composition. Furthermore, the invention relates to a process for producing the module.

Abstract: A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that extend from one edge of the transparent element to the other edge. A third embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches. A fourth embodiment has a transparent element with an adhesive flow restriction area formed as a protuberance. A fifth embodiment comprises a trench in the die. A sixth embodiment has a die with a plurality of trenches in the die as an adhesive flow restriction area. A seventh embodiment has a die with a protuberance.

Abstract: In one embodiment, an electronic device package (1) includes a leadframe (2) with a flag (3). An electronic chip (8) is attached to the flag (3) with a die attach layer (9). A trench (16) having curved sidewalls is formed in the flag (3) in proximity to the electronic chip (8) and surrounds the periphery of the chip (8). An encapsulating layer (19) covers the chip (8), portions of the flag (3), and at least a portion of the curved trench (16). The curved trench (16) reduces the spread of die attach material across the flag (3) during chip attachment, which reduces chip and package cracking problems, and improves the adhesion of encapsulating layer (19). The shape of the curved trench (16) prevents flow of die attach material into the curved trench (16), which allows the encapsulating layer (19) to adhere to the surface of the curved trench (16).

Abstract: An assembly for producing partially packaged semiconductor devices is provided. In one embodiment, the assembly includes a magnetic plate; a flexible substrate disposed adjacent the magnetic plate and having two surfaces; a nonstick coating disposed on one surface of the flexible substrate thereby exposing a nonstick surface; and a tape layer having two surfaces. The tape layer is adhesively attached to the nonstick surface to expose a surface of the tape layer. A frame is disposed on the exposed surface of the tape layer, and a plurality of integrated circuit (IC) die is positioned within the frame and supported by the tape layer. A panel is formed within the frame that at least partially surrounds the plurality of IC die and that contacts the tape layer.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: A mounting structure is provided. The mounting structure includes: a substrate; a line formed on the substrate; an electronic component in which a terminal having a protrusion protruded to the substrate and made of an elastic material and a conductive member disposed on the protruded surface of the protrusion and electrically connected to the line is disposed on a mounting surface of the electronic component opposed to the substrate; and an adhesive in which metal powders, a part of which is interposed between the conductive member and the line, are mixed and which serves to bond and fix the electronic component to the substrate. Here, the conductive member and the line interpose the metal powders therebetween and come in surface-contact with each other.

Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.

Abstract: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact pads disposed on the surface of a chip package.

Abstract: A semiconductor die is attached to a packaging substrate by a patterned layer of conductive metal that includes voids. The voids provide a space into which the metal may expand when heated in order to avoid placing mechanical stress on the bonds caused by mismatches in the thermal coefficients of thermal expansion of the die, the conductive metal bond layer and the substrate. An additional coating of conductive metal may be flowed over the bond lines to reinforce the bonds.

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.

Abstract: A method for providing improved gettering in a vacuum encapsulated device is described. The method includes forming a plurality of small indentation features in a device cavity formed in a lid wafer. The gettering material is then deposited over the indentation features. The indentation features increase the surface area of the getter material, thereby increasing the volume of gas that the getter material can absorb. This may improve the vacuum maintained within the vacuum cavity over the lifetime of the vacuum encapsulated device.

Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer applied onto the carrier, an adhesive layer applied to the electrically insulating layer. A first semiconductor chip applied to the adhesive layer.

Abstract: A semiconductor device includes a circuit board, a wiring part, a protective coating glass, and a resin part. The circuit board has an approximately rectangular shape. The protective coating glass is disposed on the circuit board and is arranged on an inside of the circuit board in such a manner that an outer-peripheral end of the protective coating glass is away from each of four sides of the circuit board at a first distance and is away from each of four corners of the circuit board at a second distance that is larger than the first distance. The resin part seals the circuit board, the wiring part, and the protective coating glass in such a manner that an outer-peripheral end portion of the circuit board that is located on an outside of the protective coating glass directly contact with the resin part.

Abstract: Provided are a semiconductor package having molded balls on a bottom surface of a PCB and a method of manufacturing the semiconductor package. The semiconductor package includes: a semiconductor chip mounting member comprising circuit patterns on a first surface, an insulating layer defining openings exposing at least portions of the circuit patterns, and external contact terminals arranged on the portions of circuit patterns exposed by the openings; a semiconductor chip formed on a second surface of the semiconductor chip mounting member and electrically connected to the semiconductor chip mounting member; a first sealing portion coating the second surface of the semiconductor chip mounting member and the semiconductor chip; and a second sealing portion arranged on the insulating layer and the external contact terminals such that at least portions of the external contact terminals are exposed.

Abstract: A semiconductor chip is attached to a lead frame with a filmy organic die-bonding material having a water absorption of 1.5% by volume or less; having a saturation moisture absorption of 1.0% by volume or less, having a residual volatile component in an amount not more than 3.0% by weight, having a modulus of elasticity of 10 MPa or less at a temperature of 250 ° C. The semiconductor device thus obtained can be free from occurrence of reflow cracks during reflow soldering for the packaging of semiconductor devices.

Abstract: Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing the dice with conventional contact technology. The die carrier may include a flex circuit base substrate and a rigid support frame. Further embodiments comprise materials and methods for attaching the semiconductor dice to the die carrier and for providing a temporary electrical connection with the semiconductor dice during testing. Exemplary materials for providing the temporary electrical connection may comprise a conductive film or tape, a conductive or conductor-filled epoxy, resin or RTV adhesive-based materials, a water-soluble material impregnated with a conductive filler or non-reflowed solder paste.

Abstract: An adhesive film for semiconductor use of the present invention is used in a method in which, after the adhesive film for semiconductor use is laminated to one side of a metal sheet, the metal sheet is processed to give a wiring circuit, a semiconductor die is mounted and molded, and the adhesive film is then peeled off. The adhesive film includes a resin layer A formed on one side or both sides of a support film, the 90 degree peel strength between the resin layer A and the metal sheet prior to the processing of the metal sheet laminated with the adhesive film for semiconductor use to give the wiring circuit is 20 N/m or greater at 25° C., and the 90 degree peel strengths, after molding with a molding compound the wiring circuit laminated with the adhesive film for semiconductor use, between the resin layer A and the wiring circuit and between the resin layer A and the molding compound are both 1000 N/m or less at at least one point in the temperature range of 0° C. to 250° C.

Abstract: A semiconductor device includes a semiconductor substrate having top and bottom surfaces, the top surface having at least one device region thereon. At least one trench opening is formed through the substrate from the bottom surface and connecting to the device region. A layer of conductive material is deposited in the at least one trench opening and partially fills the trench opening. A layer of conductive adhesive is deposited over the layer of conductive material and fills a remaining portion of the trench opening.

Abstract: In a semiconductor device provided with a thinned semiconductor element, the present invention intends to inhibit damage of the semiconductor element in the neighborhood of its outer periphery so as to improve reliability. A plurality of external connection terminals are formed on a front surface of the thinned semiconductor element. A plate higher in rigidity than the semiconductor element is adhered with a resin binder to a rear surface of the semiconductor element. An outer shape of the plate is made larger than that of the semiconductor element, and the resin binder covers a side face of the semiconductor element to form a reinforcement portion for reinforcing a periphery of the semiconductor element.

Abstract: The invention enhances moisture resistance between a supporting body and an adhesive layer to enhance the reliability of a semiconductor device. A semiconductor device of the invention has a first insulation film formed on a semiconductor element, a first wiring formed on the first insulation film, a supporting body formed on the semiconductor element with an adhesive layer being interposed therebetween, a third insulation film covering the back surface of the semiconductor element onto the side surface thereof and the side surface of the adhesive layer, a second wiring connected to the first wiring and extending onto the back surface of the semiconductor element with the third insulation film being interposed therebetween, and a protection film formed on the second wiring.

Abstract: A semiconductor device with a semiconductor chip and electrical connecting elements to a conductor structure and a method for producing the same is disclosed. In one embodiment, the conductor structure has a chip island and contact terminal areas. These are arranged in a coplanar manner in relation to each other. The semi-conductor structure is selectively coated by a filled plastic film. Both the semiconductor chip and the electrical connecting elements are mechanically fixed and electrically connected by means of the film-covered chip island and the film-covered contact terminal areas, respectively.

Abstract: An apparatus composed of: (a) a substrate; and (b) a deposited composition comprising a liquid and a plurality of metal nanoparticles with a covalently bonded stabilizer.

Abstract: A method of packaging a microchip device, an interposer for packaging, and a packaged microchip device. An interposer is placed on microchip devices. The interposer includes an aperture which extends from the interposer surface where external electrical contacts are located on the surface of the microchip devices. Electrical contacts on the microchip device surface are accessible through the aperture in order to electrically connect the electrical contacts with the external electrical contacts of the interposer. The aperture is divided into at least two openings or aperture regions, separated by a bridge. This facilitates the handling of the interposer.

Abstract: An adhesive sheet comprising a release substrate 10, a substrate film 14, and a first tacky-adhesive layer 12 placed between the release substrate 10 and the substrate film 14, wherein an annular incision D is formed on the release substrate 10 from the surface of the first tacky-adhesive layer 12 side, the first tacky-adhesive layer 12 is laminated so as to cover the whole inner surface of the incision D in the release substrate 10, and the incision D has a depth d of less than the thickness of the release substrate 10 and 25 ?m or less.

Abstract: A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the at least first surface of the die contacting the at least first surface of the ablative base material; and ablating a channel in the ablative material proximate to the die.

Abstract: The thermally conductive body for use by being placed between a heat generating body and a heat radiating body, in which the body is molded from a thermally conductive polymer composition. The thermally conductive polymer composition contains a polymer matrix and a thermally conductive filler. At least part of the thermally conductive filler is formed in the shape of fibers and oriented in a certain direction. In the body, ends of the thermally conductive filler formed in the shape of fibers are exposed on the outer surface intersecting the direction of the orientation. Protrusions extending along the outer surface are formed thereat. In case, the body is placed between the heat generating body and the heat radiating body so that the outer surface contacts at least one of the heat generating body and the heat radiating body.

Abstract: A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.

Abstract: A COF flexible printed wiring board, used for a semiconductor device, contains an insulating layer, a wiring pattern formed of a conductor layer on one side of the insulating layer, on which a semiconductor chip is to be mounted, and a heat-resistant releasing layer, wherein the releasing layer is formed from a releasing agent and is provided on a surface of the insulating layer, which surface is opposite to the mounting side of the semiconductor chip, and the releasing layer and the insulating layer, as a whole, exhibit an optical transmittance of 50% or higher, excluding the area corresponding to the wiring pattern.

Abstract: Reactive solder material. The reactive solder material may be soldered to semiconductor surfaces such as the backside of a die or wafer. The reactive solder material includes a base solder material alloyed with an active element material. The reactive solder material may also be applied to a portion of a thermal management device. The reactive solder material may be useful as a thermally conductive interface between a semiconductor surface and a thermal management device.

Abstract: A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.