Configuration Or Pattern Of Bonds Patents (Class 257/786)
  • Patent number: 8372726
    Abstract: System, devices and methods are presented that provide an imaging array fabrication process method, comprising fabricating an array of semiconductor imaging elements, interconnecting the elements with stretchable interconnections, and transfer printing the array with a pre-strained elastomeric stamp to a secondary non-planar surface.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: February 12, 2013
    Assignee: MC10, Inc.
    Inventors: Bassel de Graff, William J. Arora, Gilman Callsen, Roozbeh Ghaffari
  • Patent number: 8373249
    Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Bryan Almond, Ken S. Hunt, Andrew M. Lever, Joe A. Ward
  • Patent number: 8368234
    Abstract: A semiconductor device is provided in which a semiconductor chip is bonded to a substrate with a sufficiently increased bonding strength and cracking is assuredly prevented which may otherwise occur due to heat shock, heat cycle and the like. The semiconductor device includes a semiconductor chip and a substrate having a bonding area to which the semiconductor chip is bonded via a metal layer. The metal layer includes an Au—Sn—Ni alloy layer and a solder layer provided on the Au—Sn—Ni alloy layer. Undulations are formed in an interface between the Au—Sn—Ni alloy layer and the solder layer.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: February 5, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Motoharu Haga, Yasumasa Kasuya, Hiroaki Matsubara
  • Patent number: 8368226
    Abstract: A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 5, 2013
    Assignee: Oracle International Corporation
    Inventors: Aparna Ramachandran, Gary John Formica
  • Publication number: 20130026659
    Abstract: A method for producing a MEMS component including the steps of simultaneously embedding structure elements during producing the multi-level conductive path layer stack which structure elements are to be subsequently exposed, subsequently producing a recess that extends from a substrate backside to the multi-level conductive path layer stack, exposing the micromechanical structure elements in the multi-level conductive path layer stack through the recess. In order to increase process precision a reference mask for defining a lateral position or a lateral extension of the micromechanical structure elements to be exposed is produced, wherein the reference mask is either arranged on the substrate front side between the substrate and the multi-level conductive path layer stack or in a layer of the multi-level conductive path layer stack which layer is more proximal to the substrate than the structure element to be exposed.
    Type: Application
    Filed: March 22, 2011
    Publication date: January 31, 2013
    Applicant: IHP GmbH - Innovations for High Performance Microelectronics
    Inventors: Mehmet Kaynak, Bernd Tillack, Rene Scholz
  • Patent number: 8362616
    Abstract: A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. According to the present invention, because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. Therefore, the flexibility of the layout of the second wiring layer is enhanced and the restriction on the wiring density can be relaxed.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: January 29, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Koji Yasumori, Hisayuki Nagamine
  • Patent number: 8362516
    Abstract: An excellent light emitting element capable of improving problems caused by a material having high light-reflectivity and susceptible to electromigration, especially Al used for the electrode. FIG. 2A depicts semiconductor light emitting element having a first and second electrodes 20 and 30 disposed at a same surface side respectively on a first and second conductive type semiconductor layer 11 and 13. In the electrode disposing surface, the first electrode 20 comprises a first base part 23 and a first extended part 24 extending from the first base part, and a plurality of separated external connecting parts 31 of the second electrode 30 arranged side by side in extending direction of the first extended part.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: January 29, 2013
    Assignee: Nichia Corporation
    Inventors: Yoshiki Inoue, Masahiko Sano
  • Patent number: 8362613
    Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 29, 2013
    Assignee: STMicroelectronics Pvt Ltd.
    Inventors: Anil Yadav, Sanjeev Kumar Jain, Rajesh Bajaj
  • Patent number: 8362621
    Abstract: A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jin Lee, Dong Hyeon Jang, Nam Seog Kim, In Young Lee, Ha Young Yim
  • Patent number: 8362614
    Abstract: A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: January 29, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuaki Katagiri, Hiroya Shimizu, Fumiyuki Osanai, Yasushi Takahashi, Seiji Narui
  • Patent number: 8357998
    Abstract: In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: January 22, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Pin Huang, Cheng Tsung Hsu, Cheng Lan Tseng, Chih Cheng Hung, Yu Chi Chen
  • Publication number: 20130015592
    Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.
    Type: Application
    Filed: December 14, 2011
    Publication date: January 17, 2013
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Nikhil Vishwanath Kelkar, Sagar Pushpala, Seshasayee sS. Ankireddi
  • Patent number: 8350364
    Abstract: An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces respectively being provided on the active front face and/or on the passive rear face, and with conductive connections being provided in the form of structured conductive tracks for providing an electrical connection from the active front face to the passive rear face. An electronic assembly formed of stacked semiconductor chips, and a method for producing the electronic component and the electronic assembly are also provided.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: January 8, 2013
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Ingo Wennemuth
  • Patent number: 8349733
    Abstract: A manufacturing method of a substrate with through electrodes, comprising a substrate having through holes, and through electrodes received in the through holes, includes a through electrode formation step of forming the through electrodes on a support plate, a substrate formation step of forming the substrate, a through electrode reception step of stacking the substrate on the support plate 45 and receiving the through electrodes in the through holes, a resin filling step of filling gaps between side surfaces of the through electrodes and inner walls of the through holes of the substrate 11 with a resin, and a support plate removal step of removing the support plate after the resin filling step.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: January 8, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Publication number: 20130001806
    Abstract: Disclosed are a fabrication process and a device of a multi-chip package having spliced substrates, characterized in utilizing an incomplete substrate and a substrate block with different dimensions to combine as a spliced complete substrate during the fabrication process. Two kinds of chips with different functions, including memory and controller, are disposed on the incomplete substrate and the substrate block, respectively. Then, the incomplete substrate and the substrate block are then spliced together by joining their spliced portions formed on their substrate sidewalls. Finally, an encapsulant is formed on the incomplete substrate and further formed on the substrate block. Accordingly, it is possible to integrate different functional chips into a single multi-chip package by optimizing packaging processing parameters with optimized materials.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventor: Hian-Hang MAH
  • Patent number: 8344514
    Abstract: A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 1, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Chad A. Cobbley, Jonathon G. Greenwood
  • Patent number: 8344477
    Abstract: One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: January 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Masafumi Yamaji
  • Publication number: 20120326338
    Abstract: According to one embodiment, a semiconductor device is provided which includes a substrate in which conductor layers and insulated layers are stacked alternately, a semiconductor element mounted on a first surface side of the substrate, and a reinforcing plate attached to a second surface side that is an opposite side of the first surface of the substrate.
    Type: Application
    Filed: June 27, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toyokazu EGUCHI, Manabu Matsumoto, Isao Ozawa
  • Patent number: 8338967
    Abstract: The present invention relates to a stress buffering package for a semiconductor component, wherein a stress buffering means comprises individual stress buffering elements that do not influence the stress buffering effect from each other. Furthermore the invention relates a method for manufacturing a stress buffering package for a semiconductor component.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: December 25, 2012
    Assignee: NXP B.V.
    Inventor: Hendrik P. Hochstenbach
  • Patent number: 8338288
    Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: December 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tamaki Wada, Akihiro Tobita, Seiichi Ichihara
  • Patent number: 8338829
    Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: December 25, 2012
    Assignee: Panasonic Corporation
    Inventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
  • Patent number: 8334201
    Abstract: A method of fabricating a semiconductor device, including forming a circuit block in a peripheral edge portion of a semiconductor chip, forming a circuit block pad on the circuit block to provide an electrical interface for the circuit block, and forming a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and providing a bonding wire pad for the circuit block.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: December 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Tetsuya Katou
  • Patent number: 8334590
    Abstract: A semiconductor device for use in a printed circuit board is provided. In the semiconductor device, metal pillars are disposed perpendicular to bond pads of a semiconductor die. This configuration eliminates the need to form via holes for the connection of interconnection layers and the bond pads of the semiconductor die, thus simplifying the fabrication procedure of the semiconductor device. In addition, the semiconductor die is embedded in the semiconductor device. Based on this configuration, the use of the semiconductor device in a printed circuit board facilitates the stacking of a plurality of semiconductor dies and can reduce the thickness required for the stack, which make the semiconductor device light in weight and small in thickness and size.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: December 18, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Yoon Ha Jung, Kyu Won Lee, Chan Yok Park
  • Publication number: 20120313265
    Abstract: A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 13, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Norio YAMANISHI
  • Patent number: 8330270
    Abstract: An integrated circuit package having a selectively etched leadframe strip defining a die attach pad and a plurality of contact pads, at least one side of the die attach pad having a plurality of spaced apart pad portions; a semiconductor die mounted to the die attach pad and wires bonding the semiconductor die to respective ones of the contact pads; a first surface of the leadframe strip, including the semiconductor die and wire bonds, encapsulated in a molding material such that at least one surface of the leadframe strip is exposed, and wherein solder paste is disposed on said contact pads and said at least one side of said die attach pad.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: December 11, 2012
    Assignee: UTAC Hong Kong Limited
    Inventors: Geraldine Tsui Yee Lin, Walter de Munnik, Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil McLellan
  • Patent number: 8330188
    Abstract: A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: December 11, 2012
    Assignee: Panasonic Corporation
    Inventors: Takayuki Yoshida, Kimihito Kuwabara, Takuma Motofuji, Toshiyuki Fukuda
  • Patent number: 8331094
    Abstract: A stacked microprocessor package architecture includes one or more microprocessor packages, the microprocessor packages including one or more microprocessor die disposed on a substrate, a satellite die, a thermal bus thermally coupled to the microprocessor die and thermally connected to system cooling, and a power bus providing power to the microprocessor die and coupled to system power. The microprocessor packages may include a module cap providing mechanical protection and/or thermal isolation or a thermal cooling path for stacked modules. Variable height standoffs provide signal connection from substrates of the stacked microprocessor packages to a system board.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: December 11, 2012
    Assignee: Oracle International Corporation
    Inventors: Seshasayee Ankireddi, Vadim Gektin
  • Patent number: 8329581
    Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: December 11, 2012
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B. Riley, III, Ilyas Mohammed
  • Patent number: 8324735
    Abstract: There is provided a semiconductor device including: plural first output pads formed along one edge of an outer periphery of a substrate; plural second output pads formed along at least one of an edge at an opposite side of the substrate from the one edge, and an edge adjoining the one edge; plural internal circuits, each of which is provided with an output terminal connected with an output pad of one of the first output pads and the second output pads; plural first lines, each of which connects one of the output terminals of the internal circuits with one of the plurality of first output pads; and plural second lines, each of which connects one of the output terminals of the internal circuits with one of the plural second output pads, resistance values per unit of wiring length being lower in the second lines than in the first lines.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: December 4, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Koji Higuchi
  • Patent number: 8324741
    Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 4, 2012
    Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 8324740
    Abstract: A semiconductor device includes a multilayer wiring board and a semiconductor chip mounted on the multilayer wiring board. Electrode pads of the semiconductor chip include: first electrode pads including electrode pads respectively disposed in the vicinity of corners of the back surface of the semiconductor chip; and second electrode pads other than the first electrode pads. Connection pads of the multilayer wiring board include: first connection pads connected to the first electrode pads via bumps; and second connection pads connected to the second electrode pads via bumps. The first connection pads are supported by a first insulating region made of a thermoplastic resin, and the second connection pads are supported by a second insulating region made of a thermosetting resin.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: December 4, 2012
    Assignee: Panasonic Corporation
    Inventor: Kiyomi Hagihara
  • Patent number: 8324725
    Abstract: Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: December 4, 2012
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, Charles A. Miller, Bruce J. Barbara, Barbara Vasquez
  • Patent number: 8319222
    Abstract: A connection structure comprising an adhesive composition is provided. The adhesive composition is capable of providing good adhesion strength to the polyimide surface of a flexible circuit board that is exposed on the metal wiring surface and between the traces even when the polyimide surface is relatively smooth. The adhesive composition contains a thermoplastic resin, a polyfunctional acrylate, and a radical polymerization initiator and further contains a monofunctional urethane acrylate having a urethane residue at its terminal end. The monofunctional urethane acrylate is represented by the formula (1): CH2?CR0—COO—R1—NHCOO—R2??(1) wherein R0 is a hydrogen atom or a methyl group, R1 is a divalent hydrocarbon group, and R2 is an optionally substituted lower alkyl group.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: November 27, 2012
    Assignee: Sony Chemical & Information Device Corporation
    Inventors: Yasushi Akutsu, Yasunobu Yamada, Kouichi Miyauchi
  • Patent number: 8319354
    Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: November 27, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin
  • Patent number: 8319114
    Abstract: A dual footprint mounting package for a surface mount power converter modules and its method of manufacture. Castellated regions are formed on the edge of the component package using the appropriate sized drill or milling bit. Edge plating is applied to the castellated surfaces to create edge pads. The edge plating provides electrical continuity between the edge pads and the SMT pads. Solder mask, or other materials, is applied to prevent solder from wicking between each SMT pad and its respective edge pad. Such component may be attached to a larger device PWB using either the edge pads or the SMT pads, or may even be attached using a combination of the two, such as in the event of a pad failure or other defect.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: November 27, 2012
    Assignee: Densel Lambda K.K.
    Inventors: Sun-Wen Cyrus Cheng, Paulette Lemond, Carl Milton Wildrick
  • Patent number: 8310055
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-ju Park, Jae-ho Min, Myeong-cheol Kim, Dong-chan Kim, Jae-hwang Sim
  • Patent number: 8308960
    Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: November 13, 2012
    Assignee: Silex Microsystems AB
    Inventors: Edvard Kälvesten, Thorbjörn Ebefors, Thierry Corman
  • Patent number: 8310068
    Abstract: A TCP type semiconductor device, which is connected to a plurality of substrate-side electrodes parallel to each other and each having a linear shape, has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connecting between the semiconductor chip and the plurality of substrate-side electrodes, respectively. Each of the plurality of leads has an external terminal section extending in a first direction and configured to come in contact with corresponding one of the plurality of substrate-side electrodes. A part of the external terminal section is a wide section that is formed wider than the other section of the external terminal section A position of the wide section in the first direction is different between adjacent leads of the plurality of leads.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Suguru Sasaki
  • Patent number: 8310059
    Abstract: A semiconductor integrated circuit free from increase in chip area or significant reversion in designing is provided. The semiconductor integrated circuit includes: IO buffers arrayed in line; pad coupling wirings respectively arrayed in correspondence with the IO buffers; and IO buffer switching wirings respectively arrayed in line in correspondence with the IO buffers, set in a layer different from those of the IO buffers and the pad coupling wirings so that they overlap with part of the corresponding pad coupling wirings, and extended to other pad coupling wirings adjacent to the corresponding pad coupling wirings. Each of the IO buffer switching wirings is formed in an identical shape so that it is not short-circuited to adjacent other IO buffer switching wirings. The IO buffers are electrically coupled with the corresponding IO buffer switching wirings in the same positions.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Masafumi Tomoda
  • Patent number: 8304879
    Abstract: A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: November 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Da Un Nah, Jae Myun Kim, Tae Hoon Kim, Jung Tae Jeong, Bok Gyu Min, Ki Bum Kim
  • Patent number: 8304337
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • Patent number: 8304885
    Abstract: A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: November 6, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Fumihiko Terasaki
  • Patent number: 8304867
    Abstract: An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Fabian McCarthy, Stanley Craig Beddingfield
  • Patent number: 8304922
    Abstract: A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Sangkwon Lee, Tae Keun Lee
  • Patent number: 8304921
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a planar support structure having a cavity; forming a terminal within the cavity with the terminal coplanar with the planar support structure; forming a conductive pathway on the terminal and the planar support structure with the conductive pathway having a route portion and an interconnect attach portion at the end of the route portion; connecting a device and the interconnect attach portion with the interconnect attach portion towards the device; and forming an encapsulation over the planar support structure covering the conductive pathway and the device.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Allan P. Ilagan, Philip Lyndon Cablao
  • Patent number: 8299631
    Abstract: Provided is a semiconductor element in which decrease in reliability of wiring is suppressed. A driver IC (10) has a plurality of output bumps (12) arranged in the direction (direction A) along the long sides (11a and 11b). The output bumps include a plurality of source bumps (12a) arranged near the center section of the long side, and a plurality of gate bumps (12b) arranged towards the end portions of the long side. The source bumps are arranged close to the long side (11a), and the gate bumps are arranged closer to the long side (11b) than the source bumps.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: October 30, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Horiguchi, Takashi Matsui, Motoji Shiota
  • Patent number: 8299632
    Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: October 30, 2012
    Assignee: ATI Technologies ULC
    Inventors: Roden Topacio, Gabriel Wong
  • Patent number: 8294266
    Abstract: Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 23, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roden R. Topacio, Neil McLellan, Yip Seng Low, Andrew K W Leung
  • Patent number: 8294265
    Abstract: A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: October 23, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Kwang Sun Oh, Dong Hee Lee, Dong In Kim, Bae Yong Kim, Jin Woo Park
  • Patent number: 8294264
    Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Wang, Chi-Chun Hsieh, An-Jhih Su, Hsien-Wei Chen, Shin-Puu Jeng, Liwei Lin