Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: A dicing die attachment film includes a die attachment layer attached to one surface of a semiconductor wafer; a dicing film layer attached to a dicing die that is used for cutting the semi-conductor wafer into die units; and an intermediate layer laminated between the die attachment layer and the dicing film layer. The intermediate layer has a modulus of 100 to 3000 MPa, which is greater than a modulus of the die attachment layer and the dicing film layer.

Abstract: Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being destroyed due to electro-migration (EM) and stress-migration (SM). An illustrated metal interconnection line includes: a semiconductor substrate; a metal pattern on the substrate; a glue pattern under the metal pattern; an anti-reflection pattern on the metal pattern; and dummy patterns surrounding side walls of the metal pattern.

Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: A separation layer and a semiconductor element layer including a thin film transistor are formed. A conductive resin electrically connected to the semiconductor element layer is formed. A first sealing layer including a fiber and an organic resin layer is formed over the semiconductor element layer and the conductive resin. A groove is formed in the first sealing layer, the semiconductor element layer, and the separation layer. A liquid is dropped into the groove to separate the separation layer and the semiconductor element layer. The first sealing layer over the conductive resin is removed to form an opening. A set of the first sealing layer and the semiconductor element layer is divided into a chip. The chip is bonded to an antenna formed over a base material. A second sealing layer including a fiber and an organic resin layer is formed so as to cover the antenna and the chip.

Abstract: Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.

Abstract: A circuit with embedding components (13) is produced by placing the components (13) on a substrate (14) and applying sheets (15) of prepreg. The prepreg sheets (15) have apertures to accommodate the -components, the number of sheets and arrangement of apertures being chosen to accommodate a variety of component X, Y and Z dimensions. A top layer with Cu foil (16(b)) is applied. The assembly is pressed in an operation analogous to conventional multilayer board lamination pressing. This causes all of the prepreg resin to flow to completely embed the components without raids or damage. Electrical connections are made by drilling and plating vias.

Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract: In one aspect of the present invention, a manufacturing method of a semiconductor device may include performing an electrical test on a plurality of electronic components on a wafer, generating a mapping data set including category information representing categories of the respective electronic components based on the electrical test result and position information representing positions of the respective electronic components in the wafer, forming bumps on the plurality of electronic components at wafer level in various bump layouts employed in accordance with the categories assigned to the respective electronic components, with reference to the mapping data set, and dicing the wafer to separate the plurality of electronic components into individual chips, after forming the bumps.

Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.

Abstract: A resin layer covering a semiconductor chip on a wiring board is composed of a first resin layer and a second resin layer, wherein the first resin layer and the second resin layer differ in their plan view pattern, satisfying a relation of a<b, where “a” is difference in length in the direction from the center of the board towards the edges between the first resin layer and the second resin layer, and “b” is difference in length in the direction from the center of the board towards the corners between the first resin layer and the second resin layer.

Abstract: Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant ? and/or lower loss tangent ? than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower ? buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower ? buffer region reduces the parasitic loss in the encapsulation. Low ? and/or ? buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has ? less than about 3.0 and/or ? less than about 0.005.

Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to simulate the components from the substrate. Prior to the simulating step the components can be tested and burned-in while they remain on the substrate.

Abstract: Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).

Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

Abstract: This invention is directed to preventing deformation, breakage, and the like of leads in a semiconductor device, reducing the fraction of defects, and making the semiconductor device smaller and thinner. In order to accomplish these objects, in a carrier including a base having a device hole and a plurality of leads for bonding a chip, the leads are provided with thin heat-resistant films.

Abstract: This invention involves encapsulating an RFID device in an encapsulating material by known encapsulating processes to form a domed, encapsulated RFID tag. The encapsulating material may be translucent or opaque, flexible or hard, and has minimal effect on transmission or reception of radio frequency (RF) signals. The invention further involves a stand-off bracket, composed of one or more materials that have minimal effect on transmission or reception of RF signals, for mounting an RFID device on or near materials that impede RF transmission and reception. The encapsulated RFID tag and stand-off bracket, separately, may have an adhesive or other attachment means on one of their surfaces so that they may be adhered or otherwise attached to another surface. In one application, an encapsulated RFID tag in the 860-928 MHz range is mounted on a stand-off bracket and may be used for tracking items to which it is attached.

Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.

Abstract: A semiconductor pressure sensor can reduce the damage of bonding wires to increase their life time even under an environment in which the temperature and pressure change rapidly and radically. The semiconductor pressure sensor includes a package (1) made of a resin and having a concave portion (1a), a lead (2) formed integral with the package (1) by insert molding, with its one end exposed into the concave portion (1a) and its other end extended from the package (1) to the outside, a sensor chip (3) arranged in the concave portion (1a) for detecting pressure, and a bonding wire (4) electrically connecting the sensor chip (3) and the lead (2) with each other. An interface between the lead (2) and the package (1) on the side of the concave portion (1a) is covered with a first protective resin portion (6) of electrically insulating property, and the bonding wire (4) is covered with a second protective resin portion (7) that is softer than the first protective resin portion (6).

Abstract: A semiconductor device includes a silicon substrate having first and second surfaces, in which a wiring pattern is formed on the first surface; a first resin layer formed over the first surface of the silicon substrate; and a second resin layer formed over the second surface of the silicon substrate. The silicon substrate has a thickness less than 150 ?m, and each of the first and second resin layers has a thickness larger than that of the silicon substrate.

Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.

Abstract: A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.

Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, some buffer material and some encapsulation is provided. The substrate has a first surface and a corresponding second surface. The chip has an active surface and a back surface. The bumps are disposed between the active surface of the chip and the first surface of the substrate. The buffer material is disposed on the back surface of the chip. The encapsulation is disposed over the first surface of the substrate to enclose the chip and the buffer material.

Abstract: One embodiment of this invention pertains to multiple encapsulated thin-film electronic devices. These encapsulated devices include a substrate and multiple thin-film electronic devices are on this substrate. Each of the multiple thin-film electronic devices has an active area. The encapsulated devices also include an encapsulation layer that is on the substrate and this encapsulation layer has multiple holes and these multiple holes are over the active areas of the multiple thin-film electronic devices. The encapsulated devices also include multiple substantially flat encapsulation pieces that are on the encapsulation layer and these multiple substantially flat encapsulation pieces cover the multiple holes of the encapsulation layer. An absorbent material is not attached to any of the substantially flat encapsulation pieces.

Abstract: A semiconductor device having a semiconductor substrate, at least one of a protruding electrode and wiring formed on one surface of the semiconductor substrate, and a first resin film formed on this surface. The first resin film has elasticity low enough to reduce stress induced by a difference in thermal expansion coefficient between the semiconductor substrate and the first resin film. A second resin film, having higher elasticity or higher strength than the first resin film, may be formed on the other surface of the semiconductor substrate.

Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

Abstract: A semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame includes a die pad and a plurality of leads properly spaced apart from the die pad, each lead being composed of an inner lead portion and an outer lead portion, wherein the inner lead portion is directed toward the die pad, and the outer lead portion has a terminal. At least a chip is mounted on the die pad, and a first encapsulant is formed for encapsulating the chip, die pad and inner lead portions. An injection-molded second encapsulant is formed for encapsulating the first encapsulant and outer lead portions, but exposing the terminals of the outer lead portions. The second encapsulant made by injection molding can prevent resin flash over the exposed terminals, thereby assuring electrical-connection quality of the semiconductor package.

Abstract: An integrated circuit package system including a leadframe having an aperture provided therein and an integrated circuit package mounted to the leadframe over or under the aperture. A die is mounted within the aperture to the integrated circuit package and the die includes a plurality of the die.

Abstract: A semiconductor wafer includes a redistribution layer which is electrically connected with a pad which is an end portion of an interconnect, a first resin layer which is formed over the redistribution layer, a second resin layer which is formed over the first resin layer and covers the side surface of the first resin layer, and an external terminal which is formed to be electrically connected with the redistribution layer in a manner to avoid the pad.

Abstract: A device, such as an integrated circuit or an electronic circuit component is affixed to a substrate. A first encapsulation structure encases a first integrated circuit and has at least one groove formed therein. An adhesive partially fills the groove in the first encapsulation structure. A second integrated circuit is affixed to the first encapsulation structure by use of the adhesive in the groove. A second encapsulation structure at least partially encases the first encapsulation structure, the first integrated circuit, and the second integrated circuit.

Abstract: A lead frame of the present invention includes a plurality of tie bars including tie bars each having deformable portions that protect opposite outside frames from deformation. The outside frames each are formed with positioning holes. Element loading portions to be loaded with semiconductor elements are connected to the outside frames by such tie bars. The lead frame is therefore free from deformation during lead forming while promoting the miniaturization of the semiconductor devices.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: The present invention provides an apparatus and method for use in processing semiconductor workpieces. The new apparatus and method allows for the production of thinner workpieces that at the same time remain strong. Particularly, a chuck is provided that includes a body, a retainer removeably attached to the body and a seal forming member. When a workpiece is placed on the chuck body and the retainer is engaged to the body, a peripheral portion of the back side of the workpiece is covered by the retainer while an interior region of the back side of the workpiece is exposed. The exposed back side of the workpiece is then subjected to a wet chemical etching process to thin the workpiece and form a relatively thick rim comprised of semiconductor material at the periphery of the workpiece. The thick rim or hoop imparts strength to the otherwise fragile, thinned semiconductor workpiece.

Abstract: Two types of resin films are prepared for manufacturing a multi-layer board containing a chip component. A fist type has a via hole for the chip component to be inserted into, while a second type does not have the via hole. Resin films including the two types are piled before the chip component is inserted. At least a given resin film of the first type has a via hole provided with protruding members. Of the protruding members, opposing protruding members form a gap between their tips. This gap is shorter than an outer dimension of the inserted chip component. The chip component crushes portion of the tips of the protruding members while being pressed and inserted into the via hole in the given resin film.

Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.

Abstract: A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined by a peripheral opening in a surrounding frame, which may be part of a multiframe strip. The substrate is connected to the frame by connecting segments. The card includes a first plastic casting molded to the substrate and encapsulating the semiconductor components while leaving a peripheral portion of the substrate uncovered. A second plastic casting is molded to the peripheral portion to abut the first plastic casting and form the card periphery. A method for fabricating the semiconductor card is also included.

Abstract: The invention relates to a semiconductor component for mounting on a printed circuit board. The semiconductor component includes a housing that at least partially surrounds at least one flat semiconductor chip. Electrical contacts are assigned to the semiconductor chip and serve to establish an electrical connection to electrodes provided on a printed circuit board. The flat semiconductor chip has a mounting lateral surface that includes contact surfaces configured to make contact with the electrical contacts. A buffer layer is located between the housing and the chip, and surrounds the chip up to a supporting surface located on the mounting lateral surface.

Abstract: A package-in-package system is provided including forming a top substrate having a first integrated circuit electrically connected thereto and mounting a second integrated circuit over the first integrated circuit. The system includes forming first electrical connectors on the second integrated circuit and encapsulating the second integrated circuit in a first encapsulant with the first electrical connectors exposed. The system includes mounting the second integrated circuit over a bottom substrate with the first electrical connectors electrically connected thereto and encapsulating the top substrate and the first encapsulant in a second encapsulant.

Abstract: A semiconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to expose a portion of the second surface to reveal information pertaining to the semiconductor device. The coating layer is patterned by directing a radiation beam (30) such as a laser to selectively remove material from the coating layer.

Abstract: A process for fabricating a chip package structure with the following steps is provided. First, a chip having an active surface is provided. A plurality of solder bumps is disposed on the active surface. Then, a polymer material including flux is placed on the surface of the solder bumps by a dipping process. The chip is disposed on a carrier such that the carrier is in contact with the solder bumps. A reflow process is carried out so that the chip and the carrier are electrically connected through the solder bumps and a plurality of supporting structures made from the polymer material are formed around the junctions between the solder bumps and the carrier. The supporting structures enhance the endurance of the solder bumps to thermal stress and reduce damage due to fatigue.

Abstract: An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust, inflexible cost-effective bond. The semiconductor die is attached to the carrier substrate with a plurality of discrete adhesive elements so as to provide a gap or standoff therebetween. Wire bonds may then be formed between bond pads on the semiconductor die to conductive pads or terminals on the carrier substrate. With this arrangement, a dielectric filler material is disposed in the gap or standoff to form a permanent bonding agent between the semiconductor die and the carrier substrate. By applying the dielectric filler material after forming the wire bonds, the dielectric filler material coats at least a portion of the wire bonds to stabilize the wire bonds and prevent wire sweep in an encapsulation process, such as transfer molding, performed thereafter.

Abstract: To refine an electrical or electronic component having at least one discrete or integrated device formed from a wafer, in plate or disk form, of semiconductive or insulating material, the front face of which device has at least one protruding electrode and is encapsulated by at least one front-face encapsulant, the side faces of which device are at least partly encapsulated by at least one side-face encapsulant, and the rear face of which device is encapsulated by at least one rear-face encapsulant, and to refine a method of producing the same, in such a way that, with the aim of widening the possible uses and applications, electrical contact is made not solely with the front face of the device that is to be housed in the plastics package of very small dimensions, it is proposed that both the side-face encapsulant and the rear-face encapsulant be formed at least partly of layers, but with the layers connected, of electrically conductive material.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.

Abstract: A photovoltaic module comprises electrically interconnected and mutually spaced photovoltaic cells that are encapsulated by a light-transmitting encapsulant between a light-transparent front cover and a back cover, with the back cover sheet being an ionomer/nylon alloy embossed with V-shaped grooves running in at least two directions and coated with a light reflecting medium so as to provide light-reflecting facets that are aligned with the spaces between adjacent cells and oriented so as to reflect light falling in those spaces back toward said transparent front cover for further internal reflection onto the solar cells, whereby substantially all of the reflected light will be internally reflected from said cover sheet back to the photovoltaic cells, thereby increasing the current output of the module. The internal reflector improves power output by as much as 67%.

Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.

Abstract: Solder joints coupling pins to a microelectronic package substrate are enshrouded with an encapsulation material. In this manner, pin movement is limited even if the pin solder subsequently melts.

Abstract: A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.