Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: A packaging layer (200) for a wafer level assembly is fabricated from a glass material comprising both inorganic and organic components. This allows matching between the coefficient of thermal expansion of the packaging layer and that of other materials in the wafer assembly, particularly electrical interconnect materials. It is also possible to introduce properties to support such methods as photolithographic and low temperature processing of the packaging layer. This can improve fabrication accuracy and allows the packaging layer to be used with structures in a wafer assembly which might be damaged by high temperature processing, such as active optoelectronic devices and integrated circuits. Another major advantage is that the glass material can be used to provide optical characteristics as well as mechanical protection. The refractive index and other optical properties can be preselected and thus the glass material can be used for instance for waveguiding and index matching.

Abstract: An integrated circuit package system includes: providing a substrate; mounting a first package above the substrate, the first package having a mold cavity exposing an exposed portion on a first integrated circuit from a first package encapsulation; mounting a second package above the first package and attached to the exposed portion of the first integrated circuit; mounting a structure above the second package and connected to the substrate around the first package; and encapsulating the first package and the second package with an outer encapsulation having a completely planar top or a planar top co-planar to a top surface of the structure.

Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.

Abstract: Composite with a first part composed of a thermoset material and with a second part composed of a thermoplastic material, and with an adhesion-promoter layer located between these, where the first part has been bonded by way of the adhesion-promoter layer to the second part, and where the adhesion-promoter layer comprises pyrolytically deposited semiconductor oxides and/or pyrolytically deposited metal oxides.

Abstract: A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate.

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

Abstract: A semiconductor module manufacturing method includes a step of bonding a semiconductor wafer, which has a plurality of semiconductor elements each of which has an element electrode formed thereon, on an expansible first insulating resin layer; a step of dicing the semiconductor wafer; a step of expanding the first insulating resin layer to widen a gap between semiconductor elements; a pressure-bonding step of pressure-bonding a metal plate whereupon an electrode is arranged and the semiconductor elements with the widened gaps in between, by having a second insulating resin layer in between, and electrically connecting the electrode and the element electrodes; a step of forming a wiring layer which corresponds to each semiconductor element by selectively removing the metal plate and forming a plurality of semiconductor modules connected by the first insulating resin layer and the second insulating resin layer; and a step of separating the semiconductor modules by cutting the first insulating resin layer and th

Abstract: The invention relates to an electronic device, having a front face 8 and a rear face 8?, fitted with at least one discrete integrated component, comprising: a) the active face 10 of the component appearing to the side of the front face 8; b) coating material 3, present at least laterally relative to the component, ensuring the so-called component is held in the device; and c) an insulating buffer layer 6, absent from the active face 10 of the component, separating the coating material 3 from this component 4.

Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Abstract: The invention relates to a semiconductor device comprising semiconductor device components embedded in plastic housing composition. The semiconductor device components partly contain copper or have copper-containing coatings and/or coating structures. The copper-containing regions of the semiconductor device components have an adhesion promoting layer with copper(II) oxide whiskers on the surfaces that are in contact with the plastic housing composition.

Abstract: A microfluidic component having at least one first polymer layer, which is provided with a microstructure for at least one fluid, and having at least one second polymer layer. It is provided that at least one semiconductor component is situated on the first and/or the second polymer layer. Furthermore, a manufacturing method for such a microfluidic component is described.

Abstract: A light emitting device includes a resin molded body having a circular or an oval recessed section at the center suppresses generation of cracks. The device is provided with a light emitting element, a first resin molded body having a plurality of outer surfaces, and a recessed section at the center. First and second leads are electrically connected to the light emitting element, and a second resin molded body is applied in the recessed section. The light emitting element is placed on the first lead, and the surface of the second resin molded resin forms a light emitting surface. A gate notch is formed on an extended line of a normal line on one point on a circular cross-section of the recessed section in the normal line direction.

Abstract: This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.

Abstract: Methods and apparatus provide for: applying an inorganic barrier layer to at least a portion of a flexible substrate, the barrier layer being formed from a low liquidus temperature (LLT) material; and sintering the inorganic barrier layer while maintaining the flexible substrate below a critical temperature.

Abstract: Various embodiments of the present invention relates to systems, devices and methods of detecting tampering and preventing unauthorized access by incorporating programmability and randomness into a process of coupling, driving and sensing conductive wires that are arranged above sensitive areas in a secured system. Such a tampering detection system comprises a security mesh network, a random number generator, a security controller and a security monitor. The security mesh network includes a plurality of security elements made from the conductive wires. The security controller selects a subset of security elements, forms a security array, and generates a driving stimulus. The security monitor selects a SENSE node, monitors an output at the SENSE node, and generates a flag signal indicating the presence of a tampering attempt. Programmability and randomness are introduced to at least one of the system parameters including array configuration, driving stimulus, SENSE node, and detection mode via random numbers.

Abstract: An embodiment of the present invention is a technique to form a resin. A mixture is formed by a curing agent dissolved in the epoxy resin. The epoxy resin contains a first rigid rod mesogen. The curing agent contains a second rigid rod mesogen and one of a hydroxyl, amine, and anhydride.

Abstract: The present invention relates to a primer resin for semiconductor devices which comprises a polyamide resin represented by the following formula (1): (wherein, R1 represents a tetravalent aromatic tetracarboxylic acid residue selected from the group consisting of pyromellitic acid, 3,4,3?,4?-diphenyl ether tetracarboxylic acid, 2,3,6,7-naphthalenetetracarboxylic acid and 3,4,3?,4?-benzophenone tetracarboxylic acid, R2 represents at least one kind of divalent diamine residue selected from the group consisting of diamino-4,4?-hydroxydiphenylsulfone, 4,4?-diamino-3,3?5,5?-tetraethyldiphenylmethane and 1,3-bis-(aminophenoxy)benzene, and n is a repeating number and represents a positive number of 10 to 1000) and has a lead frame comprising copper or 42 alloy, a semiconductor device having said primer resin layer between a lead frame comprising copper or 42 alloy and a cured product of a sealing resin, and a semiconductor sealing epoxy resin composition containing said primer resin; and said semiconductor devic

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material; exposing the stack interconnector by removing the sacrificial carrier assembly; and forming a base array over the underfill material and the stack interconnector.

Abstract: A flexible barrier film has a thickness of from greater than zero to less than 5,000 nanometers and a water vapor transmission rate of no more than 1×10?2 g/m2/day at 22° C. and 47% relative humidity. The flexible barrier film is formed from a composition, which comprises a multi-functional acrylate. The composition further comprises the reaction product of an alkoxy-functional organometallic compound and an alkoxy-functional organosilicon compound. A method of forming the flexible barrier film includes the steps of disposing the composition on a substrate and curing the composition to form the flexible barrier film. The flexible barrier film may be utilized in organic electronic devices.

Abstract: A chip module and a fabricating method thereof are provided. Firstly, a substrate is provided. Next, a chip is assembled on the substrate and electrically connected with the substrate. Afterward, a plurality of passive units is assembled on the substrate in the style of encircling the chip. Then, a first glue structure is filled between the passive units so that an encircled area is defined by the first glue structure and the passive units. Then, a second glue structure is filled in the encircled area so that the chip is covered by the second glue structure.

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract: An electronic component, in which the outer perimeter portion of a component (2) is surrounded with a first sealing resin (4), a second sealing resin (3) is filled within the periphery of the first sealing resin (4), the component (2) and a board (1) are electrically connected by a wire (5), the edge, in the vicinity of which the wire (5) passes, of the outer perimeter edge portions of the component (2) is formed to be a chamfered oblique surface (31), and the wire (5) is provided to extend to the board (1) along the oblique surface (31). By this means, the overall height of the electronic component can be kept low.

Abstract: An encapsulation device including two casings made of a flexible polymer material, each delimiting a sealed space, and at least one hydrophobic material filling each of the casings, the casings being stacked and sealingly interconnected at peripheral edges thereof, a sealed space then being defined between the two casings for receiving a device to be encapsulated.

Abstract: An electronic component packaging structure includes a circuit board, electronic components mounted on the circuit board and a moisture-proof coating layer covering the electronic components. The moisture-proof coating layer is constituted from a polymer material coating having at least two layers of a lower layer and an upper layer, and the polymer material forming the lower layer has higher swelling property and/or solubility to a repairing solvent that is selected from among hydrocarbon-based solvents than the polymer material forming the upper layer.

Abstract: Disclosed herein is a light emitting device, which includes a first substrate, a protective layer, a second substrate, a buffer member and a sealant. The first substrate has an illuminating member thereon. The protective layer covers the illuminating member and has a first coefficient of thermal expansion. The second substrate is disposed over the protective layer. The buffer member is disposed between the first and second substrates and surrounds the protective layer, wherein the buffer member has a second coefficient of thermal expansion which is less than the first coefficient. The sealant surrounds the buffer member and seals off the space between the first and second substrates, wherein the sealant has a third coefficient of thermal expansion which is less than the second coefficient.

Abstract: The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 ?m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).

Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

Abstract: A process for fabricating an amorphous diamond-like film layer for protection of a moisture or oxygen sensitive electronic device is described. The process includes forming a plasma from silicone oil, depositing an amorphous diamond-like film layer from the plasma, and combining the amorphous diamond-like film layer with a moisture or oxygen sensitive electronic device to form a protected electronic device. Articles including the amorphous diamond-like film layer on an organic electronic device are also disclosed.

Abstract: To provide a semiconductor wafer surface protection sheet having good adhesion to irregularities on a patterned surface of a semiconductor wafer and having good peelability after wafer grinding. Specifically, a semiconductor wafer surface protection sheet is provided that includes a base layer having a tensile elasticity at 25 C°, E(25), of 1 GPa or more; a resin layer A that satisfies the condition EA(60)/EA(25) <0.1, where EA(25) is a tensile elasticity at 2 C° and EA(60) is a tensile elasticity at 60° C., the EA(60) ranging from 0.005 MPa to 1 MPa; and a resin layer B having a tensile elasticity at 60° C., EB(60), of 1 MPa or more and having a thickness of 0.1 ?m to less than 100 ?m, the EB(60) being larger than the EA(60) of the resin layer A.

Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor chips, and a first sealing material. The substrate may include, but is not limited to, a chip mounting area and a higher-level portion. The higher level portion surrounds the chip mounting area. The higher-level portion is higher in level than the chip mounting area. The stack of semiconductor chips is disposed over the chip mounting area. A first sealing material seals the stack of semiconductor chips. The first sealing material is confined by the higher-level portion.

Abstract: An organic light emitting diode (OLED) display comprises: a substrate; a display unit formed on the substrate and including an organic light emitting element; an interception layer positioned at the outside of the display unit on the substrate; and a thin film encapsulation layer which is formed with a stacked film of an inorganic film and an organic film, which has an end portion contacting the interception layer, and which covers the entire display unit and at least a part of the interception layer.

Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

Abstract: A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with the small interconnect on the lower tip and below the upper tip; and encapsulating around the small interconnect and around the large interconnect with an exposed surface.

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Abstract: A semiconductor device includes a substrate, a semiconductor chip, and first and second insulations. The substrate has at least a first region and a second region. The semiconductor chip structure covers the first region. The first insulation covers the second region. The first insulation has a first thermal expansion coefficient approximately equal to that of the semiconductor chip structure. The second insulation covers the semiconductor chip structure and the first insulation so that the semiconductor chip structure and the first insulation are sandwiched between the substrate and the second insulation. The second insulation has a second thermal expansion coefficient approximately equal to that of the substrate.

Abstract: The present invention relates to coating systems and coating systems on substrates. In an embodiment, the invention includes an article including a substrate, a base layer disposed on the substrate, the base layer comprising a silane compound with a photoreactive group, or the reaction product of a silane compound with a photoreactive group, and a polymer layer disposed on the base layer, the polymer layer comprising a polymer terminally anchored to the base layer. In an embodiment, the invention includes a coating for an article. In an embodiment, the invention includes a method of depositing a coating onto a substrate.

Abstract: A thin-layer encapsulation (1) for an optoelectronic component. The thin-layer encapsulation (1) comprises a sequence of layers (2) that comprises the following layers: a first ALD layer (3) deposited by means of atomic layer deposition, and a second ALD layer (4) deposited by means of atomic layer deposition. A method is disclosed for producing the thin-layer encapsulation and an optoelectronic component is disclosed having such a thin-layer encapsulation.

Abstract: A device including a semiconductor chip. One embodiment provides a device, including a metal layer having a first layer face. A semiconductor chip includes a first chip face. The semiconductor chip is electrically coupled to and placed over the metal layer with the first chip face facing the first layer face. An encapsulation material covers the first layer face and the semiconductor chip. At least one through-hole extends from the first layer face through the encapsulation material. The at least one through-hole is accessible from outside the device.

Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.

Abstract: Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate.

Abstract: An encapsulation resin composition for preapplication, comprising (a) an epoxy resin, and (b) a curing agent having flux activity, wherein the tack after B-staging is at least 0 gf/5 mm? and at most 5 gf/5 mm?, and the melt viscosity at 130° C. is at least 0.01 Pa·s and at most 1.0 Pa·s; a preapplied encapsulated component and semiconductor device using the composition, and a process of fabrication thereof. The resin composition is less susceptible to air entrapment during provisional placement of semiconductor chips, and excels in workability and reliability.

Abstract: A semiconductor device includes at least bonding wires between electrode pads on a main surface of a semiconductor chip and connection pads on a wiring board. The wires form loop shapes from the electrode pads of the semiconductor chip. The semiconductor device also includes at least forming flat parts on the loop-shaped wires, and using a sealing material to seal the semiconductor chip such as to bury the flat parts.

Abstract: A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has other interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film.