More Than Two Heterojunctions In Same Device Patents (Class 257/97)
  • Patent number: 6127691
    Abstract: A semiconductor laser device comprises a GaAs substrate, a first cladding layer having either one of p-type electrical conductivity and n-type electrical conductivity, a first optical waveguide layer, an In.sub.x2 Ga.sub.1-x2 As.sub.1-y2 P.sub.y2 first barrier layer, an In.sub.x3 Ga.sub.1-x3 As.sub.1-y3 P.sub.y3 quantum well active layer, an In.sub.x2 Ga.sub.1-x2 As.sub.1-y2 P.sub.y2 second barrier layer, a second optical waveguide layer, and a second cladding layer having the other electrical conductivity, the layers being overlaid in this order on the substrate. Each cladding layer and each optical waveguide layer have compositions, which are lattice matched with the substrate. Each of the first and second barrier layers has a tensile strain with respect to the substrate and is set such that a total layer thickness of the barrier layers may be 10 nm to 30 nm, and a product of a strain quantity of the tensile strain and the total layer thickness may be 0.05 nm to 0.2 nm.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: October 3, 2000
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Toshiaki Fukunaga, Mitsugu Wada
  • Patent number: 6111277
    Abstract: A semiconductor device such as a light emitting semiconductor device comprising a mask layer having opening areas and a selective growing layer comprising a semiconductor grown selectively by way of the mask layer, with each of the mask layer and the selective growing layer being disposed by two or more layers alternately. The semiconductor device is manufactured by a step of laminating on a substrate a mask layer having opening areas and a selective growing layer comprising a semiconductor grown selectively way of a mask layer, each by two or more layers alternately and a subsequent step of laminating semiconductor layers thereon. Threading dislocations in the underlying layer are interrupted by the first mask layer and the second mask layer and do not propagate to the semiconductor layer. The density of the threading dislocations is lowered over the entire surface and the layer thickness can be reduced.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: August 29, 2000
    Assignee: Sony Corporation
    Inventor: Masao Ikeda
  • Patent number: 6111275
    Abstract: A gallium nitride group compound semiconductor light-emitting device comprises a substrate and a layered structure provided on the substrate. The layered structure includes: an active layer; an upper cladding layer and a lower cladding layer which is located closer to the substrate than the upper cladding layer, the active layer interposed between the cladding layers; an internal current constricting layer having an opening for constricting a current within a selected region of the active layer, the internal current constricting layer being provided on the upper cladding layer; a surface protecting layer for covering the internal current constricting layer and an exposed surface of the upper cladding layer in the opening of the internal current constricting layer; and a regrowth layer provided on the surface protecting layer. The surface protecting layer serves as a protecting layer for the upper cladding layer and the internal current constricting layer in a step of forming the regrowth layer.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: August 29, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshio Hata
  • Patent number: 6107648
    Abstract: A light emitting layer forming portion is formed of an AlGaInP-based compound semiconductor and having an n-type layer and a p-type layer to form a light emitting layer on the substrate. A large bandgap energy semiconductor layer is provided on a surface of the light emitting layer forming portion to constitute a window layer. A buffer layer is interposed between the light emitting layer forming portion and the large bandgap energy semiconductor layer to relieve lattice mismatch of between the light emitting layer forming portion and the large bandgap energy semiconductor layer. The interposition of this buffer layer provides a light emitting device that is high in light emitting efficiency and excellent in electrical characteristics without degrading the film property of the window layer.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: August 22, 2000
    Assignee: Rohm Co., Ltd.
    Inventors: Yukio Shakuda, Shunji Nakata, Yukio Matsumoto
  • Patent number: 6107647
    Abstract: A semiconductor light emitting device has a light emitting layer forming portion formed on the substrate and having an n-type layer and a p-type layer to provide a light emitting layer. A window layer is formed on a surface side of the light emitting layer forming portion. The window layer is formed of AlyGal-yAs (0.6.ltoreq.y.ltoreq.0.8) auto-doped in a carrier concentration of 5.times.10.sup.18 -3.times.10.sup.19 cm.sup.-3. The resulting semiconductor light emitting device is free of degradation in crystallinity due to p-type impurity doping, thereby provide a high light emitting efficiency and brightness without encountering device degradation or damage.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: August 22, 2000
    Assignee: Rohm Co. Ltd.
    Inventors: Yukio Matsumoto, Shunji Nakata, Yukio Shakuda
  • Patent number: 6104044
    Abstract: Disclosed is an electrode material for Group III-V compound semiconductor represented by the general formula In.sub.x Ga.sub.y Al.sub.z N (provided that x+y+z=1, 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, and 0.ltoreq.z.ltoreq.1) doped with a p-type impurity which is capable of obtaining good ohmic contact, and an electrode using the same, thereby making it possible to reduce a driving voltage of a device using the compound semiconductor. The electrode material is a metal comprising at least Ca and a noble metal, wherein the total amount of the weight of Ca and the noble metal is not less than 50% by weight and not more than 100% by weight based on the weight of the whole electrode material.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: August 15, 2000
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasushi Iyechika, Yoshinobu Ono, Tomoyuki Takada, Katsumi Inui
  • Patent number: 6100546
    Abstract: III-V arsenide-nitride semiconductor are disclosed. Group III elements are combined with group V elements, including at least nitrogen and arsenic, in concentrations chosen to lattice match commercially available crystalline substrates. Epitaxial growth of these III-V crystals results in direct bandgap materials, which can be used in applications such as light emitting diodes and lasers. Varying the concentrations of the elements in the III-V materials varies the bandgaps, such that materials emitting light spanning the visible spectra, as well as mid-IR and near-UV emitters, can be created. Conversely, such material can be used to create devices that acquire light and convert the light to electricity, for applications such as full color photodetectors and solar energy collectors. The growth of the III-V material can be accomplished by growing thin layers of elements or compounds in sequences that result in the overall lattice match and bandgap desired.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: August 8, 2000
    Assignee: SDL, Inc.
    Inventors: Jo S. Major, David F. Welch, Donald R. Scifres
  • Patent number: 6100544
    Abstract: A light emitting diode includes a double hetero structure containing an upper cladding layer with a graded composition. The light emitting diode comprises a GaAs substrate, a first ohmic contact to the substrate, an AlGaInP lower cladding layer formed on the GaAs substrate, an AlGaInP active layer formed on the lower cladding layer, an AlGaInP upper cladding layer formed on the active layer and a second ohmic contact. The AlGaInP upper cladding layer has a graded composition which increases the LED brightness and decreases the forward bias voltage of the light emitting diode. The graded composition can also be used in the upper semiconducting layer of a conventional p-n junction light emitting diode.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: August 8, 2000
    Assignee: Visual Photonics Epitaxy Co., Ltd.
    Inventors: Kun-Chuan Lin, Lung-Chien Chen
  • Patent number: 6097041
    Abstract: A light emitting diode includes a semiconductor substrate of a first conductivity type. A first electrode is formed on a part of the substrate. A reflection stack of the first conductivity type is formed on the substrate. An active layer is then formed on the reflection stack. An anti-reflection stack of a second conductivity type is grown on the active layer, and the anti-reflection stack consists of a plurality of layers, wherein each layer has a thickness of (m+1).lambda./2, where m is zero or a positive integer and .lambda. is a wavelength of radiation generated by the active layer. A window layer of the second conductivity type is formed on the anti-reflection stack. A second electrode is then formed on a part of the window layer.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: August 1, 2000
    Assignee: Kingmax Technology Inc.
    Inventors: Ying-Fu Lin, Liang-Tung Chang, Shiang-Peng Cheng, Kuan-Chu Kuo, Chiao-Yun Lin, Fu-Chou Liu
  • Patent number: 6091083
    Abstract: A gallium nitride type compound semiconductor light-emitting device of the present invention includes: a substrate; a buffer layer, formed on the substrate, having a thick region and a thin region in terms of a thickness taking a surface of the substrate as a reference level; and a semiconductor layered structure, formed on the buffer layer, at least including an undoped gallium nitride type compound semiconductor layer, a gallium nitride type compound semiconductor active layer, and a P-type gallium nitride type compound semiconductor cladding layer.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: July 18, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshio Hata, Satoshi Sugahara, Daisuke Hanaoka
  • Patent number: 6091084
    Abstract: A semiconductor light emitting device has a light emitting chip and a conductive member. A light emitting chip is formed by an insulating substrate. A semiconductor layered portion has semiconductor layers forming a light emitting layer grown on the insulating substrate. A first electrode (p-side electrode) is formed in electrical connection with a first conductivity type semiconductor layer on a surface side of the semiconductor layered portion. A second electrode (n-side electrode) is formed in electrical connection with a second conductivity type semiconductor layer at a position exposed by partly etching the semiconductor layered portion. The light emitting chip is adhered at a backside of the insulating substrate to the conductive member through a conductive adhesive, and the conductive member is electrically connected to the second electrode.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: July 18, 2000
    Assignee: Rohm Co., Ltd.
    Inventor: Takehiro Fujii
  • Patent number: 6087725
    Abstract: On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: July 11, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Yoichi Sasai, Satoshi Kamiyama, Tohru Saitoh, Takashi Nishikawa, Ryoko Miyanaga
  • Patent number: 6081001
    Abstract: A luminous intensity of a semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors is improved by having a thickness d of a light emitting layer (active layer) of the semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors ranging from 0.3 nm to 1.5 nm.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: June 27, 2000
    Assignee: Sony Corporation
    Inventors: Kenji Funato, Tsunenori Asatsuma, Hiroji Kawai
  • Patent number: 6078061
    Abstract: The opening portion as the pattern shift detecting portion is formed in the insulating layer so that an edge of the electrode pattern extends to the opening portion when the electrode pattern shifts and the contact resistivity between the light emitting portion and the electrode pattern increases more than the predetermined value during the patterning process. If the electrode pattern shifts to a direction of the scribe line, the electrode pattern is electrically connected to the P-type diffusion region via the pattern shift detecting portion. As a result, the electrode pattern is shorted an N-type electrode pattern via the P-type diffusion region and the N-type GaAsP/GaAs substrate Therefore, the light emitting diode can precisely detect inferior products without visual inspection.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: June 20, 2000
    Assignee: Oki Data Corporation
    Inventor: Keiichi Koya
  • Patent number: 6072196
    Abstract: Nitrogen-containing III-V alloy semiconductor materials have both a conduction band offset .DELTA.Ec and a valence band offset .DELTA.Ev large enough for the practical applications to light emitting devices. The semiconductor materials are capable of providing laser diodes, having excellent temperature characteristics with emission wavelengths in the red spectral region and of 600 nm or smaller, and high brightness light emitting diodes with emission wavelengths in the visible spectral region. The light emitting device is fabricated on an n-GaAs substrate, which has the direction normal to the substrate surface is misoriented by 15.degree. from the direction normal to the (100) plane toward the [011] direction. On the substrate, there disposed by MOCVD, for example, are an n-GaAs buffer layer, an n-(Al.sub.0.7 Ga.sub.0.3).sub.0.51 In.sub.0.49 P cladding layer, an (Al.sub.0.2 Ga.sub.0.8).sub.0.49 In.sub.0.51 N.sub.0.01 P.sub.0.99 active layer, a p-(Al.sub.0.7 Ga.sub.0.3).sub.0.51 In.sub.0.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: June 6, 2000
    Assignee: Ricoh Company, Ltd.
    Inventor: Shunichi Sato
  • Patent number: 6072202
    Abstract: A layer structure for a II-VI compound semiconductor device is formed on a GaAs substrate of III-V compound, wherein lattice mismatching is prevented by a first layer interposed between the GaAs substrate and a II-VI compound semiconductor active layer and made of III-V compound semiconductor including In element as a constituent element thereof. The thickness of the first layer is less than the critical thickness allowing coherent growth. Alternatively, the III-V compound of the first layer has a lattice constant substantially equal to the lattice constant of the GaAs substrate. The first layer may be a superlattice layer.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: June 6, 2000
    Assignee: NEC Corporation
    Inventor: Koichi Naniwae
  • Patent number: 6069367
    Abstract: The purpose of the present invention is to provide a semiconductor light-emitting element that can reduce an operational voltage by improving a contact construction with a p-side electrode. An n-type clad layer, a first guide layer, an active layer, a second guide layer, a p-type clad layer, a ZnSSe cap layer, a ZnSe cap layer, a compositional gradient super-lattice layer, and a low defect contact layer are sequentially laminated on an n-type substrate. The compositional gradient super-lattice layer is formed by alternately laminating p-type ZnTe layers and p-type ZnSe layers. The p-type ZnTe layers are formed to be thickened toward the side of the low defect contact layer. The thickness of the low defect contact layer must be 5 nm or less. Relaxing lattice distortion reduces defect density of the low defect contact layer. Accordingly, the increase in the operational voltage immediately after energization is suppressed, and the operational voltage becomes lower.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: May 30, 2000
    Assignee: Sony Corporation
    Inventors: Shigetaka Tomiya, Satoru Kijima, Hiroyuki Okuyama, Satoshi Taniguchi, Hironori Tsukamoto
  • Patent number: 6057563
    Abstract: Disclosed is a light transparent window layer for light transmitting diodes. The light transparent window layer is formed by growing a plurality of AlGaInP superlattice layers such that the uniformity of current distribution within LED chip can be enhanced, and the size of light-emitting area can be increased. The manufacturing process is also simplified.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: May 2, 2000
    Assignee: Lite-on Electonics, Inc.
    Inventors: Hsi-Ming Chen, Szutsun S. Ou
  • Patent number: 6057561
    Abstract: A ZnO thin film is fabricated on the c-surface of a sapphire substrate through use of a laser molecular beam epitaxy (MBE) method-which is effective for epitaxial growth of an oxide thin film through control at an atomic level. The thus-formed ZnO thin film has a considerably high crystallinity; the half width of an X-ray rocking curve was 0.06.degree.. The thin film is of an n-type and has a carrier density of 4.times.10.sup.17 /cm.sup.3. The thin film fabricated in a state in which oxygen partial pressure is held constant at 10.sup.-6 Torr has a structure in which hexagon-shaped nanocrystals of uniform size are close-packed, reflecting the crystal behavior of a wurtzite type. Since in each nanocrystal there is observed a spiral structure formed by steps of a unit cell height (0.5 nm), the nanocrystals are considered to grow in a thermodynamically equilibrated state. The lateral size of the nanocrystal can be controlled within the range of approximately 50 to 250 nm.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: May 2, 2000
    Assignee: Japan Science and Technology Corporation
    Inventors: Masashi Kawasaki, Hideomi Koinuma, Akira Ohtomo, Yusaburo Segawa, Takashi Yasuda
  • Patent number: 6057560
    Abstract: A surface light-emitting device includes an active layer and a set of reflectors. The reflectors are arranged on both opposite sides of the active layer such that light can be emitted in a direction perpendicular to the active layer. At least a portion of the reflectors includes a plurality of layers of compound semiconductors at least one of which includes nitrogen. Current is injected into the active layer, and the intensity of the light emitted from the surface light-emitting device is changed by the current modulated in accordance with a signal to be transmitted. At least one of the layers of compound semiconductors may also include aluminum.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: May 2, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mamoru Uchida
  • Patent number: 6055258
    Abstract: A semiconductor laser device is disclosed in which the device comprises one or more ion-implanted regions as a means to decrease the occurrence of device failures attributable to dark-line defects. The ion-implanted regions, which are formed between the laser gain cavity and the regions of probable dark-line defect origination, serve to modify the electrical, optical, and mechanical properties of the device lattice structure, thus reducing or eliminating the propagation of dark-line defects emanating from constituent defects or bulk material imperfections which may be present in the device.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: April 25, 2000
    Assignee: Polaroid Corporation
    Inventors: Dana M. Beyea, Todd Martin Dixon, Edward M. Clausen, Jr.
  • Patent number: 6054724
    Abstract: A compound semiconductor layer of a first conductivity type is formed on a substrate, and a diffusion region of a second conductivity type is formed on the compound semiconductor layer. The light-emitting diode has a high emitted light power, using a large-diameter wafer.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: April 25, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Mitsuhiko Ogihara, Yukio Nakamura, Masumi Taninaka, Hiroshi Hamano
  • Patent number: 6054723
    Abstract: A light emitting diode array includes a light emitting area formed on a semiconductor substrate, a diffusion prevention layer formed on the semiconductor substrate, and an insulating layer formed on the diffusion prevention layer. The diffusion prevention layer has a lower edge and the insulating layer has a level drop at this lower edge. An interconnection conductor extends on the insulating layer and is in ohmic contact with the light emitting region through holes in the insulating layer and the diffusion prevention layer. The interconnection conductor has a stepped portion at the level drop of the insulating layer, the stepped portion being located in a wide-width segment of the interconnection conductor.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: April 25, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Tomoyoshi Tajiri, Takao Kusano, Kazuya Ohkawa
  • Patent number: 6043515
    Abstract: An optical semiconductor device has a structure in which a semiconductor active layer is sandwiched by a p-type semiconductor cladding layer and an n-type semiconductor cladding layer and a p-type contact layer is formed on the p-type semiconductor cladding layer side and an n-type contact layer is formed on the n-type semiconductor cladding layer side, wherein two ferromagnetic layers are formed on the n-type contact layer and two ferromagnetic layers are formed on the p-type contact layer. Magnetization directions of a pair of ferromagnetic layers vertically opposed to each other are set to be parallel to each other, and the magnetization directions of adjacent ferromagnetic layers are inverted to each other.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: March 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuzo Kamiguchi, Yuzo Hirayama, Masashi Sahashi
  • Patent number: 6043514
    Abstract: A group III-V type nitride semiconductor device includes a substrate with a crystal structure of rutile type, CaC.sub.2 type, rock salt type, spinel type, NaFeO.sub.2 (II) type or LiAlO.sub.2 (I) type, and a nitride semiconductor layer epitaxially grown thereon. The substrate is selected so that its lattice constant allows good lattice match with respect to the nitride semiconductor layer, or the substrate is adjusted in composition to have such a lattice constant.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: March 28, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Nobuaki Teraguchi
  • Patent number: 6040590
    Abstract: A semiconductor light-emitting device having one or more depletion regions that are controlled by one or more control electrodes to vary the spatial distribution of the carriers in an active layer. The voltages on the control electrodes can be controlled to modulate the current density in the active layer and the output light intensity. The polarization of a surface emitting diode laser based on this device can be controlled or modulated.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: March 21, 2000
    Assignee: California Institute of Technology
    Inventors: John OBrien, Axel Scherer, Amnon Yariv, Reginald Lee, Yuanjian Xu, Oskar Painter
  • Patent number: 6040588
    Abstract: A semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of In.sub.Y1 Ga.sub.1-Y1 N (Y1.gtoreq.0) and a quantum well layer being made of In.sub.Y2 Ga.sub.1-Y1 N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: March 21, 2000
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Norikatsu Koide, Shinya Asami, Junichi Umezaki, Masayoshi Koike, Shiro Yamasaki, Seiji Nagai
  • Patent number: 6030700
    Abstract: A multicolor organic light emitting device employs vertically stacked layers of double heterostructure devices which are fabricated from organic compounds. The vertical stacked structure is formed on a glass base having a transparent coating of ITO or similar metal to provide a substrate. Deposited on the substrate is the vertical stacked arrangement of three double heterostructure devices, each fabricated from a suitable organic material. Stacking is implemented such that the double heterostructure with the longest wavelength is on the top of the stack. This constitutes the device emitting red light on the top with the device having the shortest wavelength, namely, the device emitting blue light, on the bottom of the stack. Located between the red and blue device structures is the green device structure.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: February 29, 2000
    Assignee: The Trustees of Princeton University
    Inventors: Stephen Ross Forrest, Mark Edward Thompson, Paul Edward Burrows, Linda Susan Sapochak, Dennis Matthew McCarty
  • Patent number: 6020602
    Abstract: An n-cap layer is formed on a top surface of p-type clad layers, the p-type clad layer is a top layer of a stacked structure having a pn-junction for emitting carriers into light-emitting region of a GaN based light-emitting device, thus increasing the activation ratio of acceptor impurities in the p-type clad layers. The n-cap layer is used also as a current blocking layer, thereby constructing a current-blocked structure. The n-cap layer should preferably be made of In.sub.u Al.sub.v Ga.sub.1-u-v N (0<u, v<1) deposited as thick as 1.0 micron or more. The present invention will easily provide a high luminous efficiency GaN based semiconductor light-emitting device without using any complicated processes such as electron-beam irradiation or thermal annealing.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: February 1, 2000
    Assignee: Kabushiki Kaisha Toshba
    Inventors: Hideto Sugawara, Masayuki Ishikawa
  • Patent number: 5998805
    Abstract: An active matrix OED array with an improved device cathode includes a plurality of control transistors formed on a semiconductor substrate with insulating material positioned over the control transistors to form a planar surface. A plurality of contact pads are formed on the planar surface and electrically coupled to the control transistors. A thin (5 .ANG. to 20 .ANG.) electron injecting layer of either alkaline metal oxide or alkaline metal fluoride is positioned on each contact pad and organic material is deposited on the electron injecting layer so as to define an organic light emitting device on each contact pad and electrical and light conducting material is positioned over the organic material to define a second terminal for the OEDs.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: December 7, 1999
    Assignee: Motorola, Inc.
    Inventors: Song Q. Shi, Franky So, Hsing-Chung Lee
  • Patent number: 5995529
    Abstract: An infrared light source is disclosed that comprises a layered semiconductor active region having a semimetal region and at least one quantum-well layer. The semimetal region, formed at an interface between a GaAsSb or GalnSb layer and an InAsSb layer, provides electrons and holes to the quantum-well layer to generate infrared light at a predetermined wavelength in the range of 2-6 .mu.m. Embodiments of the invention can be formed as electrically-activated light-emitting diodes (LEDs) or lasers, and as optically-pumped lasers. Since the active region is unipolar, multiple active regions can be stacked to form a broadband or multiple-wavelength infrared light source.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: November 30, 1999
    Assignee: Sandia Corporation
    Inventors: Steven R. Kurtz, Robert M. Biefeld, Andrew A. Allerman
  • Patent number: 5990496
    Abstract: A light emitting device includes a cladding layer composed of a III-V group nitride system semiconductor of a first conductivity type, an active layer formed on the cladding layer of the first conductivity type and composed of a III-V group nitride system semiconductor containing In, an undoped cap layer formed on the active layer and composed of a III-V group nitride system semiconductor, and a cladding layer formed on the cap layer and composed of a III-V group nitride system semiconductor of a second conductivity type.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: November 23, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tatsuya Kunisato, Takashi Kano, Yasuhiro Ueda, Yasuhiko Matsushita, Katsumi Yagi
  • Patent number: 5990497
    Abstract: A semiconductor light emitting element exhibiting a characteristic of deflected luminous intensity distribution, a semiconductor light emitting device capable of making, even when the element is off the center, a luminous center close to the center, and an element scribing method having a high element separation rate without causing a crack and chipping of pellet edges. The semiconductor light emitting element involves the use of a scribed pellet 10 into which a wafer including a semiconductor layer such as a luminous layer that is stacked on a compound semiconductor substrate inclined at 5.degree. through 20.degree. to a surface (100) in a orientation [011], is subjected to an element separation process by a scribing method.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: November 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takanobu Kamakura, Takafumi Nakamura, Makoto Yamamura, Yoshio Ariizumi, Kazuhiro Tamura, Shinichi Sanda, Takumi Komoto, Yukio Watanabe
  • Patent number: 5981977
    Abstract: A nitride compound semiconductor light emitting element comprises a substrate, a nitride compound semiconductor n-type layer, a mask layer having a predetermined opening, a nitride compound semiconductor buffer layer epitaxially grown on said n-type layer exclusively at said opening. The buffer layer has a recess on its top face so that a thickness of said buffer layer is thinner above a central portion of the opening and thicker above edge portions of the opening. A nitride compound semiconductor active layer is selectively formed on the recess of the buffer layer to be thicker at the central portion of the recess and thinner at the edges of the recess. A nitride compound semiconductor burying layer overlays the mask layer and the active layer to cover the active layer.
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: November 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chisato Furukawa, Hideto Sugawara, Masayuki Ishikawa, Nobuhiro Suzuki
  • Patent number: 5981978
    Abstract: A superluminiscent diode includes: a semiconductor substrate of a first conductivity type lower cladding layer of the first conductivity type is provided on the semiconductor substrate. An active layer is provided on the lower cladding layer. An upper cladding layer of a second conductivity type opposite to the first conductivity type bis provided on the active layer. A current blocking layer of the first conductivity type, buried in the upper cladding layer. The current blocking layer has a stripe-shaped groove serving as a current-injection region. The current-injection region is formed in a manner that is extends from an end face of a chip to the inside of the chip, and has a length shorter than that of the chip. The current blocking layer is made of a material having a band gap energy not greater than that of the active layer and a refractive index not smaller than that of the active layer so that light advancing in the active layer is absorbable.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: November 9, 1999
    Assignee: Rohm Co., Ltd.
    Inventors: Masato Mushiage, Tatsuo Yamauchi, Yukio Shakuda
  • Patent number: 5973336
    Abstract: An LED having improved light emission characteristics by allowing radiation generated to be guided towards the side faces of the LED by means of a relatively thick waveguide comprised of a transmissive material, specifically in such a way that as many modes as possible can propagate.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: October 26, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Christian Hanke, Bernhard Stegmueller
  • Patent number: 5955748
    Abstract: An end facet light emitting type LED has a slanted light emitting side wall relative to a substrate surface. A method for manufacturing end facet light emitting type light emitting devices prevents the pn-junction regions of the devices from being damaged while a semiconductor wafer is diced to separate light emitting devices from one another. A recess is formed on the semiconductor wafer having a depth which is deeper than the pn-junction. A portion to be cut during dicing of the wafer is vertically and horizontally separated from the pn-junction regions, so that if cracks occur when the wafer is diced, the cracks do not affect the light emitting characteristics of the devices.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: September 21, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yukio Nakamura, Mitsuhiko Ogihara, Masumi Taninaka, Takao Kusano, Masumi Koizumi, Hiroyuki Fujiwara, Makoto Ishimaru, Masaharu Nobori, Tsutomu Nomoto
  • Patent number: 5949093
    Abstract: A semiconductor light emitting device comprises: a plurality of II-VI compound semiconductor layers stacked on a semiconductor substrate; a contact layer formed on the II-VI compound semiconductor layers; a first first-conduction-type-side electrode and a second first-conduction-type-side electrode formed on the contact layer; and a second-conduction-type-side electrode formed on a bottom surface of the semiconductor substrate, at least a portion of the contact layer underlying the second first-conduction-type-side electrode being changed to a high-resistance region by application of an electric field between the second first-conduction-type-side electrode and the second-conduction-type-side electrode, and the high-resistance region behaving as a current blocking region.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: September 7, 1999
    Assignee: Sony Corporation
    Inventor: Koshi Tamamura
  • Patent number: 5945690
    Abstract: The present invention includes a process of growing a compound semiconductor layer locally, after applying radical particles that do not become an etchant of a compound semiconductor layer to an insulating mask so as to terminate the surface of the insulating mask in a state that the compound semiconductor layer is covered with the insulating mask, on the surface of the compound semiconductor layer exposed from the insulating mask.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: August 31, 1999
    Assignee: Fujitsu Limited
    Inventors: Junji Saito, Toshihide Kikkawa, Hirosato Ochimizu
  • Patent number: 5939734
    Abstract: A method of fabricating a semiconductor light emitting device includes fabricating, semiconductor light emitting devices on a large scale by forming desirable end surfaces of resonators using an etching process. The method includes the steps of forming, on a base body, semiconductor layers for constituting a plurality of semiconductor light emitting devices; grooving the semiconductor layers formed on the base body in the direction from a front surface of the semiconductor layers to the base body, to form stripe-like grooves; and forming a semiconductor film in the grooves by epitaxial growth; wherein a side surface of each of the grooves, which side surface finally forms an end surface of a resonator of each of the semiconductor light emitting devices, is a crystal plane being later in epitaxial growth rate than a bottom surface of the groove.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: August 17, 1999
    Assignee: Sony Corporation
    Inventor: Yuichi Hamaguchi
  • Patent number: 5939733
    Abstract: A compound semiconductor device includes a substrate and a group III-V compound semiconductor layer provided on the substrate, wherein the group III-V compound semiconductor layer contains As as a group V element and Tl as a group III element.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: August 17, 1999
    Assignee: Ricoh Company, Ltd.
    Inventor: Shunichi Sato
  • Patent number: 5936266
    Abstract: Semiconductor devices and methods are disclosed in which the amount of p-type material can be minimized, with attendant advantages in electrical, thermal, and optical performance, and in fabrication. A form of the disclosure is directed to a generally planar semiconductor device wherein a layer of p-type semiconductor material is disposed over a layer of n-type semiconductor material, and an electric potential is coupled between the p-type layer and the n-type layer, and wherein current in the device that is lateral to the plane of the layers is coupled into the p-type layer. A tunnel junction is adjacent the p-type layer for converting the lateral current into hole current. In an embodiment of this form of the disclosure, the tunnel junction is an n+/p+ junction oriented with the p+ portion thereof adjacent the p-type layer. The lateral current can be electron current in the n+ layer and/or electron current in a further layer of n-type material disposed over the tunnel junction.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: August 10, 1999
    Assignee: The Board of Trustees of The University of Illinois
    Inventors: Nick Holonyak, Jr., Jonathan J. Wierer, Peter W. Evans
  • Patent number: 5932896
    Abstract: The present invention provides a nitride system semiconductor device which decreases cost and improves productivity without heat treatment after the growth and which increases in lifetime and reliability by enhancing the quality of a p-type conductive layer, and a method for manufacturing the nitride system semiconductor device. The nitride system semiconductor device has a multilayer structure of an n-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n (0.ltoreq.x, 0.ltoreq.y, 0.ltoreq.z, 0.ltoreq.x+y+z.ltoreq.1, 0<m, 0.ltoreq.n, 0<m+n.ltoreq.1) layer, a p-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n (0.ltoreq.x, 0.ltoreq.y, 0.ltoreq.z, 0.ltoreq.x+y+z.ltoreq.1, 0<m, 0.ltoreq.n, 0<m+n.ltoreq.1) layer, and an electrode 22 formed on a substrate. The oxygen concentration of the surface of the p-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n layer is 5.times.10.sup.18 cm.sup.-3 or lower.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Lisa Sugiura, Mariko Suzuki, Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, John Rennie, Hideto Sugawara
  • Patent number: 5932899
    Abstract: A semiconductor having enhanced acceptor activation is disclosed. The semiconductor comprises a ternary compound having a non-abruptly varying composition that is uniformly doped. The modulation of the chemical composition leads to a variation of the valence band energy. The modulation of the valence band results in a strong enhancement of the acceptor activation. A method for making a semiconductor having enhanced acceptor activation comprises two steps. They are (1) forming a ternary compound semiconductor having a non-abruptly varying composition, and (2) uniformly doping said semiconductor with a dopant. These two steps may be conducted simultaneously.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: August 3, 1999
    Assignee: Trustees of Boston University
    Inventor: E. Fred Schubert
  • Patent number: 5929466
    Abstract: A semiconductor device comprises a single crystal substrate, a nucleus formation buffer layer formed on the single crystal substrate, and a lamination layer including a plurality of Al.sub.1-x-y Ga.sub.x In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) layers laminated above the nucleus formation buffer layer. The nucleus formation buffer layer is formed of Al.sub.1-s-t Ga.sub.s In.sub.t N (0.ltoreq.s.ltoreq.1, 0.ltoreq.t.ltoreq.1, s+t.ltoreq.1) and is formed on a surface of the substrate such that the nucleus formation buffer layer has a number of pinholes for control of polarity and formation of nuclei. A method of fabricating a semiconductor device comprises the steps of: forming, above an Al.sub.1-x-y Ga.sub.x In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: July 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Ako Hatano
  • Patent number: 5920079
    Abstract: The present invention provides a semiconductive light-emitting device involving a light-emitting layer of the multilayer strained quantum well structure that has a plurality of quantum well layers and a plurality of barrier layers, where each of said quantum well layers is constituted of a semiconductive crystal subjected to intraplanar compressive strain; each of the barrier layers is constituted of semiconductor crystal of AlInAs, AlGaInAs or AlGaInAsP. For high differential gain, each quantum well layer is 6nm thick or less, and the summed quantum well layers measure 13 to 1000 nm in thickness.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: July 6, 1999
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Hitoshi Shimizu, Kazuaki Nishikata, Toru Fukushima, Michinori Irikawa
  • Patent number: 5917195
    Abstract: A structure of periodically varying density is provided, that acts as a phonon resonator for phonons capable of participating in phonon-electron interactions. Specifically, a phonon resonator that is resonant for phonons of appropriate momentum to participate in indirect radiative transitions and/or inter zone intervalley scattering events is provided. Preferably, the structure is an isotope superlattice, most preferably of silicon. The structure of the present invention has improved optical, electrical, and/or heat transfer properties. A method of preparing a the structure of the present invention is also provided.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: June 29, 1999
    Assignee: B.A. Painter, III
    Inventor: Thomas G. Brown
  • Patent number: 5912475
    Abstract: An optical semiconductor device includes an n-type InP substrate having top and bottom surfaces; a stripe-shaped mesa structure including an n-type cladding layer, a multi quantum well layer, and a p-type first upper cladding layer disposed on the top surface of the substrate; a first layer of a semi-insulating material, an n-type InP hole blocking layer having a carrier concentration equal to or less than 4.times.10.sup.18 cm.sup.-3 and more than 1.times.10.sup.18 cm.sup.-3, and a second layer of the semi-insulating material disposed burying the mesa structure; a second p-type cladding layer and a p-type contact layer disposed on the mesa structure and on the second layer of the semi-insulating material, and p side electrodes spaced from each other in a stripe direction of the mesa structure, disposed on the p-type contact layer; and an n side electrode disposed on the bottom surface of the substrate.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: June 15, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takushi Itagaki, Daisuke Suzuki, Tatsuya Kimura
  • Patent number: 5909040
    Abstract: A semiconductor device comprises a single crystal substrate, a nucleus formation buffer layer formed on the single crystal substrate, and a lamination layer including a plurality of Al.sub.1-x-y Ga.sub.x In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) layers laminated above the nucleus formation buffer layer. The nucleus formation buffer layer is formed of Al.sub.1-s-t Ga.sub.s In.sub.t N (0.ltoreq.s.ltoreq.1, 0.ltoreq.t.ltoreq.1, s+t.ltoreq.1) and formed on a surface of the substrate with an average film thickness of 5 nm to 20 nm such that the nucleus formation buffer layer has a number of pinholes for control of polarity and formation of nuclei. The pinholes are formed among loosely formed small crystals of Al.sub.1-s-t Ga.sub.s In.sub.t N (0.ltoreq.s.ltoreq.1, 0.ltoreq.t.ltoreq.1, s+t.ltoreq.1).
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: June 1, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Ako Hatano
  • Patent number: 5903017
    Abstract: A gallium nitride (GaN)-based semiconductor device comprises a substrate, a single-crystal layer consisting mainly of GaN with a magnesium (Mg) concentration of N.sub.bg1 cm.sup.-3, the single-crystal layer being provided near the substrate and having a thickness of d.sub.1 .mu.m, and a semiconductor layer consisting mainly of Ga.sub.1-x Al.sub.x N having an Al composition x of at least 0.02 and not higher than 1 and having a thickness of d.sub.2 .mu.m. The single-crystal layer is situated between the substrate and the semiconductor layer, and Mg is added to the semiconductor layer at a concentration of N.sub.Mg cm.sup.-3. The Al composition x, the concentration N.sub.Mg, the concentration N.sub.bg1, the thickness d.sub.1 and the thickness d.sub.2 have the following relationshipd.sub.1 /(1600.times.x)<d.sub.2 <3.6.times.10.sup.-3 .times.logN/(x+0.02)+0.02wherein when N.sub.Mg >N.sub.bg1, N cm.sup.-3 =N.sub.Mg -N.sub.bg1, and when N.sub.Mg .ltoreq.N.sub.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: May 11, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, Mariko Suzuki, Lisa Sugiura