More Than Two Heterojunctions In Same Device Patents (Class 257/97)
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Patent number: 7196348Abstract: Although there is provided a high light transmittance of an emitted light by a ITO electrode film conventionally employed, there occurs a formation of a Schottky type contact between the ITO electrode film and a p type GaN system semiconductor layer, thus resulting in a not uniform flow of an electric current. It is an object of the present invention to provide a semiconductor light emitting device constituted by forming a transparent electrode, which facilitates acquiring an ohmic property, to be replaced by an ITO electrode film, at the light extracting or light exit side of the GaN system semiconductor light emitting device, so as to improve a light emission efficiency and a radiation extracting efficiency or a light exit efficiency of a GaN system semiconductor light emitting device.Type: GrantFiled: January 21, 2004Date of Patent: March 27, 2007Assignee: Rohm Co., Ltd.Inventor: Ken Nakahara
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Patent number: 7183584Abstract: A semiconductor element excellent in luminous efficiency which sufficiently eliminates the effect of a piezo-electric field with the crystallinity of an active layer well retained. A quantum well active layer has a laminated structure in which a barrier layer undoped region ((In0.02Ga0.98N layer 702), a quantum well layer (undoped In0.02Ga0.8N layer 703) and a barrier layer n-type region (n-type In0.02Ga0.98N layer 701) are formed in this order. The Si concentration of a barrier layer n-type region is up to 5E18 cm?3.Type: GrantFiled: January 31, 2003Date of Patent: February 27, 2007Assignee: NEC CorporationInventor: Noriyuki Futagawa
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Patent number: 7176479Abstract: A nitride compound semiconductor element having improved characteristics, productivity and yield. A nitride compound semiconductor element includes: a sapphire substrate; a first single crystalline layer of AlN formed on said sapphire substrate; a second single crystalline layer formed on said first single crystalline layer, said second single crystalline layer being made of AlxGa1-xN (0.8?x?0.97) and having a thickness of equal to or more than 0.3 ?m and equal to or less than 6 ?m; and a device structure section of a nitride semiconductor formed on said second single crystalline layer.Type: GrantFiled: February 9, 2004Date of Patent: February 13, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Yasuo Ohba
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Patent number: 7154125Abstract: The nitride-based semiconductor light-emitting device and manufacturing method thereof are disclosed: the nitride-based semiconductor light-emitting device includes a reflective layer formed on a support substrate, a p-type nitride-based semiconductor layer, a light-emitting layer and an n-type nitride-based semiconductor layer successively formed on the reflective layer, wherein irregularities are formed on a light extracting surface located above the n-type nitride-based semiconductor layer.Type: GrantFiled: April 23, 2003Date of Patent: December 26, 2006Assignee: Sharp Kabushiki KaishaInventors: Norikatsu Koide, Toshio Hata, Mayuko Fudeta, Daigaku Kimura
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Patent number: 7148518Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.Type: GrantFiled: March 23, 2004Date of Patent: December 12, 2006Inventors: Hideto Sugawara, Tsunenori Hiratsuka
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Patent number: 7148519Abstract: A GaN LED structure with a short period superlattice contacting layer is provided. The LED structure comprises, from the bottom to top, a substrate, a double buffer layer, an n-type GaN layer, a short period superlattice contacting layer, an active layer, a p-type shielding layer, and a contacting layer. The feature is to avoid the cracks or pin holes in the thick n-type GaN layer caused during the fabrication of heavily doped (n>1×1019 cm?3) thick n-type GaN contacting layer, so that the quality of the GaN contacting layer is assured. In addition, by using short period heavily silicon doped Al1-x-yGaxInyN (n++-Al1-x-yGaxInyN) to grow a superlattice structure to become a short period superlattice contacting layer structure, which is used as a low resistive n-type contacting layer in a GaInN/GaN MQW LED. In the following steps, it is easier to form an n-type ohmic contacting layer, and the overall electrical characteristics are improved.Type: GrantFiled: December 19, 2005Date of Patent: December 12, 2006Assignee: Formosa Epitaxy IncorporationInventors: Liang-Wen Wu, Cheng-Tsang Yu, Tzu-Chi Wen, Fen-Ren Chien
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Patent number: 7145180Abstract: In the fabricating of a light emitting device, a light emitting layer portion 24 and a current spreading layer 7, respectively composed of a Group III-V compound semiconductor, are stacked on a single crystal substrate. The light emitting layer portion 24 is formed by a metal organic vapor-phase epitaxy process, and the current spreading layer 7, on such light emitting layer portion 24, is formed to have conductivity type of n-type by a hydride vapor-phase epitaxy process.Type: GrantFiled: July 28, 2003Date of Patent: December 5, 2006Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Masayuki Shinohara, Masato Yamada
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Patent number: 7135710Abstract: A first cladding layer of a first conductivity type formed above a crystal substrate, an active layer formed above the first cladding layer, a diffusion prevention layer formed on the active layer and preventing an impurity from diffusing into the active layer, an overflow prevention layer of a second conductivity type, the second conductivity type being different from the first conductivity type, which is formed on the diffusion prevention layer and prevents an overflow of carriers implanted into the active layer, and a second cladding layer of the second conductivity type formed above the overflow prevention layer are provided.Type: GrantFiled: February 22, 2005Date of Patent: November 14, 2006Assignee: Kyowa Patent and Law OfficeInventors: Akira Tanaka, Masaaki Onomura
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Patent number: 7132677Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.Type: GrantFiled: February 13, 2004Date of Patent: November 7, 2006Assignee: Dongguk UniversityInventors: Hwa-Mok Kim, Tae-Won Kang, Kwan-Soo Chung
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Patent number: 7122846Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.Type: GrantFiled: February 16, 2005Date of Patent: October 17, 2006Assignee: Infinera CorporationInventors: Fred A. Kish, Jr., Sheila Hurtt, Charles H. Joyner, Richard P. Schneider
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Patent number: 7119359Abstract: The design and operation of a p-i-n device, operating in a sequential resonant tunneling condition for use as a photodetector and an optically pumped emitter, is disclosed. The device contains III-nitride multiple-quantum-well (MQW) layers grown between a III-nitride p-n junction. Transparent ohmic contacts are made on both p and n sides. The device operates under a certain electrical bias that makes the energy level of the first excitation state in each well layer correspond with the energy level of the ground state in the adjoining well layer. The device works as a high-efficiency and high-speed photodetector with photo-generated carriers transported through the active MQW region by sequential resonant tunneling. In a sequential resonant tunneling condition, the device also works as an optically pumped infrared emitter that emits infrared photons with energy equal to the energy difference between the first excitation state and the ground state in the MQWs.Type: GrantFiled: December 5, 2003Date of Patent: October 10, 2006Assignee: Research Foundation of the City University of New YorkInventors: Robert R. Alfano, Shengkun Zhang, Wubao Wang
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Patent number: 7102175Abstract: Projections/depressions of a two-dimensional periodic structure are formed in a p-GaN layer (4) such that the period of the projections/depressions is 1 to 20 times the wavelength of light radiated from an active layer (3) in a semiconductor. As a result, a diffractive effect achieved by the projections/depressions of the two-dimensional periodic structure change the direction in which the light radiated from the active layer (3) travels. If the projections/depressions are not provided, light at a radiation angle which satisfies conditions for total reflection at the interface between a semiconductor device and an air cannot be extracted to the outside of the semiconductor device so that the light emission efficiency of the device is low.Type: GrantFiled: April 8, 2004Date of Patent: September 5, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kenji Orita
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Patent number: 7098484Abstract: In order to improve light-emission efficiency without degrading protection performance of a light-emitting layer structure a three p-type layer structure composed of first to third layers is provided in contact with a light-emitting layer structure. The first layer is an n-type AlGaN layer that serves as a protective layer, the third layer is a GaN:Mg layer that serves as a contact layer and the second layer is an AlGaN:Mg layer formed between these layers as an intermediate layer. The provision of the intermediate layer enables an InGaN layer to be thoroughly protected from heat during growth of layers above even if the n-type AlGaN layer is made thin, whereby the GaN:Mg layer can be brought near the light-emitting layer structure to enhance the efficiency of hole injection into the light-emitting layer structure and thus increase the light-emission efficiency.Type: GrantFiled: July 8, 2003Date of Patent: August 29, 2006Assignee: Sumitomo Chemical Company LimitedInventors: Sadanori Yamanaka, Yoshihiko Tsuchida, Yoshinobu Ono, Yasushi Iyechika
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Patent number: 7095041Abstract: A high-efficiency light emitting diode is provided. The light emitting diode includes a substrate; a first compound semiconductor layer formed on the top surface of the substrate; a first electrode formed on a region of the first compound semiconductor layer; an active layer formed on a region of the first compound semiconductor layer excluding the region with the first electrode layer, in which 430-nm or less wavelength light is generated; a second compound semiconductor layer formed on the active layer; and a second electrode formed on the second compound semiconductor layer, with a filling ratio of 20–80% with respect to the area of the top surface of the substrate. The light emission of a 430-nm or less light emitting diode can be enhanced by adjusting the size of the p-type second electrode within the range of 20–80%.Type: GrantFiled: April 23, 2003Date of Patent: August 22, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hee Cho, Hye-jeong Oh
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Patent number: 7087924Abstract: Disclosed is a multi-quantum-well light emitting diode, which makes enormous adjustments and improvements over the conventional light emitting diode, and further utilizes a transparent contact layer of better transmittance efficiency, so as to significantly raise the illuminance of this light emitting diode and its light emission efficiency. The multi-quantum-well light emitting diode has a structure including: substrate, buffer layer, n-type gallium-nitride layer, active light-emitting-layer, p-type cladding layer, p-type contact layer, barrier buffer layer, transparent contact layer, and the n-type electrode layer.Type: GrantFiled: September 16, 2004Date of Patent: August 8, 2006Assignee: Formosa Epitaxy IncorporationInventors: Liang-Wen Wu, Ru-Chin Tu, Cheng-Tsang Yu, Tzu-Chi Wen, Fen-Ren Chien
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Patent number: 7087449Abstract: An active semiconductor device, such as, buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices, comprise a plurality of semiconductor layers formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III–V compound, i.e., an Al-III–V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III–V layer. An example of a material system for this invention useful at optical telecommunication wavelengths is InGaAsP/InP where the Al-III–V layer comprises InAlAs:O or InAlAs:O:Fe.Type: GrantFiled: June 24, 2004Date of Patent: August 8, 2006Assignee: Infinera CorporationInventors: Fred A. Kish, Jr., Sheila K. Mathis, Charles H. Joyner, Richard P. Schneider
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Patent number: 7084433Abstract: In this semiconductor laser device, an InGaP etching block layer 11 as an etching selection layer having etching selectivity for an n-type AlInP current block layer 10, which is a non-optical-absorption layer, is formed on the n-type current block layer 10. Since this etching block layer 11 prevents the current block layer 10 on both sides of a ridge 20 from being etched during manufacture, a contact layer 12 can be prevented from entering gaps between the sides of this ridge 20 and the current block layer 10. Therefore, light oscillating in an active layer 4 is taken out from a device end surface without being absorbed in the contact layer 12. According to this semiconductor laser device, an oscillation threshold current and an operation current can be maintained low, deterioration of differential quantum efficiency can be prevented and reliability can be improved.Type: GrantFiled: March 4, 2003Date of Patent: August 1, 2006Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Hosoba, Atsuo Tsunoda, Hiroshi Hayashi
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Patent number: 7078738Abstract: A light-emitting device has two light-emitting element. In a substrate portion of the light-emitting device having a first internal positive electrode connected to the positive electrode side of a first light-emitting element, a first internal negative electrode connected to the negative electrode side of the first light-emitting element, a second internal positive electrode connected to the positive electrode side of a second light-emitting element, and a second internal negative electrode connected to the negative electrode side of the second light-emitting element, these electrodes are provided so that homopolar electrodes are disposed diagonally.Type: GrantFiled: February 11, 2004Date of Patent: July 18, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Mitsuhiro Nawashiro, Satoshi Inagaki, Yasumasa Tatewaki, Takahide Oshio, Hisao Yamaguchi
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Patent number: 7071407Abstract: A method and a multijunction solar device having a high band gap heterojunction middle solar cell are disclosed. In one embodiment, a triple-junction solar device includes bottom, middle, and top cells. The bottom cell has a germanium (Ge) substrate and a buffer layer, wherein the buffer layer is disposed over the Ge substrate. The middle cell contains a heterojunction structure, which further includes an emitter layer and a base layer that are disposed over the bottom cell. The top cell contains an emitter layer and a base layer disposed over the middle cell.Type: GrantFiled: October 31, 2002Date of Patent: July 4, 2006Assignee: Emcore CorporationInventors: Navid Faterni, Daniel J. Aiken, Mark A. Stan
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Patent number: 7067847Abstract: On a substrate made of e.g., sapphire single crystal is formed an Al underlayer having FWHM X-ray rocking curve value of 90 seconds or below. A buffer layer is formed on the AlN underlayer and has a composition of AlpGaqIn1?p?qN (0?p?1, 0?y?q). A GaN-based semiconductor layer group is formed on the buffer layer.Type: GrantFiled: December 14, 2001Date of Patent: June 27, 2006Assignee: NGK Isulators, Ltd.Inventors: Tomohiko Shibata, Keiichiro Asai, Yukinori Nakamura, Mitsuhiro Tanaka
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Patent number: 7057211Abstract: The object of this invention is to provide a high-output type nitride semiconductor laser device comprising a pair of end faces of a resonator. The nitride semiconductor laser device comprises an n-type nitride semiconductor layer or layers, a p-type nitride semiconductor layer or layers and a resonator, provided with an active layer comprising nitride semiconductor containing In therebetween, wherein at least light emitting end face of the resonator is covered with an end face film of single crystal AlxGa1-xN (0?x?1) formed at a low temperature not causing damage to the active layer comprising nitride semiconductor containing In.Type: GrantFiled: October 28, 2002Date of Patent: June 6, 2006Assignees: Ammono SP. ZO.O, Nichia CorporationInventors: Robert Dwilinski, Roman Doradzinski, Jerzy Garczynski, Leszek Sierzputowski, Yasuo Kanbara
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Patent number: 7053418Abstract: The present invention provides a nitride semiconductor device comprising an active layer of a quantum well structure, a first conductive clad layer and a second conductive clad layer. The first conductive clad layer is made of the quaternary nitride semiconductor InAlGaN having a lattice constant equal to or larger than that of the active layer and includes a first nitride semiconductor layer having an energy band gap larger than that of the active layer, a second nitride semiconductor layer having an energy band gap smaller than that of the first nitride semiconductor layer and a third nitride semiconductor layer having an energy band gap larger than that of the second nitride semiconductor layer, sequentially closer to the active layer.Type: GrantFiled: September 14, 2004Date of Patent: May 30, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sun Woo Kim, Jeong Tak Oh, Je Won Kim
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Patent number: 7049638Abstract: A GaN-based LED structure is provided so that the brightness and luminous efficiency of the GaN-based LED are enhanced effectively. The greatest difference between the GaN-based LEDs according to the invention and the prior arts lies in the addition of a masking buffer layer on top of the p-type contact layer and a p-type roughened contact layer on top of the masking buffer layer. The masking buffer layer could be formed using MOCVD to deposit SixNy (x,y?1), MgwNz (w,z?1), or AlsIntGa1-s-tN (0?s,t<1, s+t?1) heavily doped with Si and/or Mg. The masking buffer layer is actually a mask containing multiple randomly distributed clusters. Then, on top of the masking buffer layer, a p-type roughened contact layer made of p-type AluInGa1-u-vN (0?u,v<1, u+v?1) is developed. The p-type roughened contact layer does not grow directly on top of the masking buffer layer.Type: GrantFiled: January 5, 2005Date of Patent: May 23, 2006Assignee: Formosa Epitaxy IncorporationInventors: Liang-Wen Wu, Ru-Chin Tu, Cheng-Tsang Yu, Tzu-Chi Wen, Fen-Ren Chien
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Patent number: 7042017Abstract: A light emitting device includes an active layer, having a multiple quantum well structure, sandwiched between an n-type semiconductor layer and a p-type semiconductor layer. The active layer includes first and second well layers made of a nitride compound semiconductor containing In, where the second well layer emits light having a main peak wavelength which is longer than that of the first well layer, and where the growth number of the first well layer is more than the growth number of the second well layer.Type: GrantFiled: May 30, 2003Date of Patent: May 9, 2006Assignee: Nichia CorporationInventor: Motokazu Yamada
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Patent number: 7042019Abstract: A structure for the n-type contact layer in the GaN-based MQW LEDs is provided. Instead of using Si-doped GaN as commonly found in conventional GaN-based MQW LEDs, the n-type contact layer provided by the present invention achieves high doping density (>1×1019 cm?3) and low resistivity through a superlattice structure combining two types of materials, AlmInnGa1-m-nN and AlpInqGa1-p-qN (0?m,n<1, 0<p,q<1, p+q?1, m<p), each having its specific composition and doping density. In addition, by controlling the composition of Al, In, and Ga in the two materials, the n-type contact layer would have a compatible lattice constant with the substrate and the epitaxial structure of the GaN-based MQW LEDs. This n-type contact layer, therefore, would not chap from the heavy Si doping, have a superior quality, and reduce the difficulties of forming n-type ohmic contact electrode. In turn, the GaN-based MQW LEDs would require a lower operation voltage.Type: GrantFiled: October 12, 2004Date of Patent: May 9, 2006Assignee: Formosa Epitaxy IncorporationInventors: Liang-Wen Wu, Ru-Chin Tu, Cheng-Tsang Yu, Tzu-Chi Wen, Fen-Ren Chien
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Patent number: 7042018Abstract: A GaN LED structure with a short period superlattice digital contacting layer is provided. The LED structure comprises, from the bottom to top, a substrate, a double buffer layer, an n-type GaN layer, a short period superlattice digital contacting layer, an active layer, a p-type shielding layer, and a contacting layer. The feature is to avoid the cracks or pin holes in the thick n-type GaN layer caused during the fabrication of heavily doped (n>1×1019cm?3) thick n-type GaN contacting layer, so that the quality of the GaN contacting layer is assured. In addition, by using short period heavily doped silicon Al1-x-yGaxInyN (n++-Al1-x-yGaxInyN) to grow a superlattice structure to become a short period superlattice digital contacting layer structure, which is used as a low resistive n-type contacting layer in a GaInN/GaN MQW LED. In the following steps, it is easier to form an n-type ohmic contacting layer, and the overall electrical characteristics are improved.Type: GrantFiled: September 22, 2004Date of Patent: May 9, 2006Assignee: Formosa Epitaxy IncorporationInventors: Ru-Chin Tu, Liang-Wen Wu, Cheng-Tsang Yu, Tzu-Chi Wen, Fen-Ren Chien
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Patent number: 7034328Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.Type: GrantFiled: April 3, 2002Date of Patent: April 25, 2006Assignee: Cree, Inc.Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.
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Patent number: 7023020Abstract: A groove is formed in a semiconductor laminate portion containing a light-emitting layer so that the groove starts from a light emission observation surface of the semiconductor laminate portion to reach at least the light-emitting layer. In such a manner, light is released from an opening portion of the groove.Type: GrantFiled: July 10, 2001Date of Patent: April 4, 2006Assignee: Toyoda Gosei Co., Ltd.Inventor: Toshiya Uemura
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Patent number: 7019333Abstract: A photon source comprising: a quantum dot (21) having a first confined energy level capable of being populated with an electron and a second confined energy level capable of being populated by a hole; and supply means (23) for supplying carriers to the said energy levels, wherein the supply means are configured to supply a predetermined number of carriers to at least one of the energy levels to allow recombination of a predetermined number of carriers in said quantum dot to emit at least one photon.Type: GrantFiled: November 16, 2000Date of Patent: March 28, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Andrew J. Shields, Richard A. Hogg
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Patent number: 7015511Abstract: For a light emitting device using gallium nitride (GaN), on a substrate are sequentially formed a GaN-based layer, an AlGaN-based layer, and a light emitting layer. To prevent cracks in the AGaN-based layer, the AlGaN-based layer is formed before planarization of the surface of the GaN layer on a surface of the GaN layer which is not planar. For a laser, the AlGaN-based layers serve as clad layers which sandwich the light emitting layer.Type: GrantFiled: June 27, 2002Date of Patent: March 21, 2006Assignees: Nitride Semiconductors Co., Ltd., Shiro SakaiInventors: Shiro Sakai, Tao Wang
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Patent number: 7012284Abstract: Disclosed herein is a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises an n-type nitride semiconductor layer on a substrate, an active layer formed on the n-type nitride semiconductor layer so that a portion of the n-type nitride semiconductor layer is exposed, a p-type nitride semiconductor layer formed on the active layer, a high-concentration dopant area on the p-type nitride semiconductor layer, a counter doping area on the high-concentration dopant areas, an n-side electrode formed on an exposed portion of the n-type nitride semiconductor layer, and a p-side electrode formed on the counter doping area. A satisfactory ohmic contact for the p-side electrode is provided by an ion implantation process and heat treatment.Type: GrantFiled: May 4, 2004Date of Patent: March 14, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seok Beom Choi, Bang Won Oh, Hee Seok Choi
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Patent number: 7012283Abstract: According to an aspect of the present invention, a nitride semiconductor light emitting device includes a light emitting layer (106) having a quantum well structure with quantum well layers and barrier layers laminated alternately. The well layer is formed of a nitride semiconductor containing In, and the barrier layer is formed of a nitride semiconductor layer containing As, P or Sb. According to another aspect of the present invention, a nitride semiconductor light emitting device includes a light emitting layer having a quantum well structure with quantum well layers and barrier layers laminated alternately. The well layer is formed of GaN1?x?y?zAsxPySbz (0<x+y+z?0.3), and the barrier layer is formed of a nitride semiconductor containing In.Type: GrantFiled: September 17, 2001Date of Patent: March 14, 2006Assignee: Sharp Kabushiki KaishaInventors: Yuhzoh Tsuda, Shigetoshi Ito, Masahiro Araki
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Patent number: 7009199Abstract: A light engine comprises a pair of LED active elements mounted on a common header having first and second terminals. The first terminal is connected to the cathode of the first LED active element and the anode of the second LED active element, while the second terminal is connected to the anode of the first LED active element and the cathode of the second LED active element, thereby connecting the LEDs in an anti-parallel arrangement. A light engine having a single insulating or semi-insulating substrate having formed thereon plural LED active elements with associated p- and n-type contacts forming cathode and anode contacts, respectively, for each LED active element is also provided. The LED active elements may be mounted in a flip-chip configuration on a header having a plurality of leads.Type: GrantFiled: October 22, 2002Date of Patent: March 7, 2006Assignee: Cree, Inc.Inventor: David Charles Hall
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Patent number: 7005682Abstract: A semiconductor light emitting element of a monolithic structure, including: a first-conductivity-type semiconductor substrate; an active layer formed on the first-conductivity-type semiconductor substrate; a second-conductivity-type clad layer formed on the active layer; and a current diffusion layer formed on the second-conductivity-type clad layer, wherein the active layer is of a first conductivity type.Type: GrantFiled: January 27, 2004Date of Patent: February 28, 2006Assignee: Sharp Kabushiki KaishaInventors: Kiyohisa Ohta, Hiroshi Nakatsu, Kazuaki Sasaki, Junichi Nakamura
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Patent number: 7005685Abstract: A GaN-based compound semiconductor device formed by sequentially forming, on a substrate, a GaN-based buffer layer and a GaN-based compound semiconductor layer. AlxGa1-xN1-yPy or AlxGa1-xN1-yAsy (0?x?1, 0<y<1) is used as the GaN-based buffer layer. N in AlxGa1-xN is partially substituted by P or As, whereby a buffer layer is grown at a high temperature. Thus, a difference in processing temperature between the process for growing a buffer layer and processes before and after the process is reduced. The GaN-based compound semiconductor layer formed on the buffer layer comprises a GaN-based layer, an n-type clad layer, a light-emitting layer, and a p-type clad layer. A multiple quantum well (MQW) layer formed from GaNP or GaNAs and GaN is inserted between the GaN-based layers, thereby reducing a dislocation density of the GaN-based layers.Type: GrantFiled: February 28, 2003Date of Patent: February 28, 2006Assignees: Nitride Semiconductors Co., Ltd.Inventors: Shiro Sakai, Yoshiki Naoi, Masashi Tsukihara
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Patent number: 7002184Abstract: In the light-emitting gallium-nitride-group compound semiconductor devices using a substrate, the operating voltage is lowered and at the same time the occurrence of crack during crystal growth is suppressed, resulting in an improved manufacturing yield rate. The device includes a stacked structure of an n-type layer, a light-emitting layer and a p-type layer formed in the foregoing order on a substrate, and an n-side electrode formed on the surface of the n-type layer. The n-type layer is a laminate layer composed of, in the order from the substrate, first n-type layer and a second n-type layer having a carrier concentration higher than that of the first n-type layer. As the contact resistance between the n-type layer and the n-side electrode formed thereon is reduced, the operating voltage of a light-emitting device is lowered, and the power consumption decreased.Type: GrantFiled: December 28, 2004Date of Patent: February 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasunari Oku, Hidenori Kamei
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Patent number: 6995403Abstract: A light emitting device is disclosed. The light emitting device comprises a contact layer and an oxide transparent layer located directly on the contact layer. The contact layer has a stacked structure formed by alternately stacking a plurality of nitride semiconductor layers having a wider bandgap and a plurality of nitride semiconductor layers having a narrower bandgap.Type: GrantFiled: September 3, 2003Date of Patent: February 7, 2006Assignee: United Epitaxy Company, Ltd.Inventors: Chuan-Cheng Tu, Cheng-Chung Young, Pao-I Huang, Jen-Chau Wu
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Patent number: 6992318Abstract: Provided are a semiconductor device having a superlattice semiconductor layer and a method of fabricating the same. The semiconductor device includes a superlattice semiconductor layer in which first material layers and second material layers formed of different materials are alternately stacked. A plurality holes are formed in the first material layers and the second material layers forming a superlattice structure, and the holes are filled with materials of the adjacent material layers. The provided superlattice structure reduces a driving voltage by transferring charges through the holes in the first material layers and the second material layers while maintaining a predetermined optical confinement characteristic.Type: GrantFiled: June 29, 2004Date of Patent: January 31, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Won-seok Lee, Kyoung-ho Ha, Joon-seop Kwak, Ho-sun Paek, Sung-nam Lee, Tan Sakong
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Patent number: 6987286Abstract: A light-emitter structure is provided. The light emitter structure includes a platform. An Inx(AlyGa1-y)1-xP lower clad region is formed on the platform and has a lattice constant between approximately 5.49 ? and 5.62 ?. A strained quantum-well active region is formed on the lower clad region. An Inx(AlyGa1-y)1-xP upper clad region is formed on the strained quantum well active region.Type: GrantFiled: August 1, 2003Date of Patent: January 17, 2006Assignee: Massachusetts Institute of TechnologyInventors: Lisa McGill, Eugene A. Fitzgerald
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Patent number: 6984850Abstract: A light-emitting diode includes: a semiconductor substrate; and a layered structure, made of an AlGaInP type compound semiconductor material and provided on the semiconductor substrate. The layered structure includes: a light-emitting structure composed of a pair of cladding layers and an active layer for emitting light provided between the pair of cladding layers; and a current diffusion layer which is lattice-mismatched with the light-emitting structure. A lattice mismatch ? a/a of the current diffusion layer with respect to the light-emitting structure defined by the following expression is ?1% or smaller: ?a/a=(ad?ae)/ae where ad is a lattice constant of the current diffusion layer, and ae is a lattice constant of the light-emitting structure.Type: GrantFiled: November 7, 2003Date of Patent: January 10, 2006Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Nakatsu, Osamu Yamamoto
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Patent number: 6979844Abstract: A low-resistance silicon baseplate (11) has formed thereon a buffer layer 12 in the form of an alternating lamination of AlN sublayers (12a) and GaN sublayers (12b). On this buffer layer there are formed an n-type semiconductor region (13) of gallium nitride, an active layer (14) of gallium indium nitride, and a p-type semiconductor region (15) of gallium nitride, in that order. An anode (17) is formed on the p-type semiconductor region (15), and a cathode (18) on the baseplate (11).Type: GrantFiled: March 21, 2003Date of Patent: December 27, 2005Assignee: Sanken Electric Co., Ltd.Inventors: Tetsuji Moku, Kohji Ohtsuka, Masataka Yanagihara, Masaaki Kikuchi
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Patent number: 6972437Abstract: Disclosed is an AlGaInN LED with improved external quantum efficiency, in which a chip employing the LED has a horizontal plane formed in a lozenge shape so that the amount of total reflection of light is reduced when the light generated from an active layer interposed between hetero-semiconductor layers with different band gaps is emitted to the outside. Since the horizontal plane of the LED is formed to have a lozenge shape so that the amount of total reflection of light generated in the LED is reduced, it is possible to maximize external quantum efficiency determined by the degree of emission of the light generated in the active layer. The cleaved plane of the LED coincides with the crystal orientation of a wafer made of GaN or sapphire, thus improving the yield of the LED when the LED is cut and produced.Type: GrantFiled: May 27, 2003Date of Patent: December 6, 2005Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Chang-Tae Kim
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Patent number: 6960779Abstract: A photon source for emitting entangled photons, the source comprising: at least one quantum dot having a degenerate exciton level; and exciton creation means to create a biexciton or higher order exciton within the at least one quantum dot.Type: GrantFiled: March 11, 2003Date of Patent: November 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Andrew James Shields, Richard Mark Stevenson
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Patent number: 6958497Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well structure. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.Type: GrantFiled: May 7, 2002Date of Patent: October 25, 2005Assignee: Cree, Inc.Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Jr., Amber Christine Abare
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Patent number: 6952024Abstract: A semiconductor structure for light emitting devices includes a Group III nitride active layer positioned between a silicon carbide cladding layer and a Group III nitride cladding layer, wherein the silicon carbide cladding layer and the Group III nitride cladding layer have opposite conductivity types. Moreover, the silicon carbide cladding layer and the Group III nitride cladding layer have respective bandgaps that are larger than the bandgap of the active layer.Type: GrantFiled: February 13, 2003Date of Patent: October 4, 2005Assignee: Cree, Inc.Inventors: John Adam Edmond, Kathleen Marie Doverspike, Hua-Shuang Kong, Michael John Bergmann
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Patent number: 6936858Abstract: A light-emitting diode includes: a semiconductor substrate; and a layered structure, made of an AlGaInP type compound semiconductor material and provided on the semiconductor substrate. The layered structure includes: a light-emitting structure composed of a pair of cladding layers and an active layer for emitting light provided between the pair of cladding layers; and a current diffusion layer which is lattice-mismatched with the light-emitting structure. A lattice mismatch ?a/a of the current diffusion layer with respect to the light-emitting structure defined by the following expression is ?1% or smaller: ?a/a=(ad?ae)/ae where ad is a lattice constant of the current diffusion layer, and ae is a lattice constant of the light-emitting structure.Type: GrantFiled: August 13, 1999Date of Patent: August 30, 2005Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Nakatsu, Osamu Yamamoto
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Patent number: 6936851Abstract: Semiconductor light emitting device and methods for its manufacture comprises a plurality of textured district defined on the surface of the substrate. The initial inclined layer deposition serves to guide the extended defects to designated gettering centers in the trench region where the defects combine with each other. As a result, the defect density in the upper section of the structure is much reduced. By incorporating a blocking mask in the structure, the free propagation of extended defects into the active layer is further restricted. The present invention is useful in the fabrication of semiconductor light emitting devices in misfit systems.Type: GrantFiled: March 21, 2003Date of Patent: August 30, 2005Inventor: Tien Yang Wang
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Patent number: 6936860Abstract: An LED includes an insulating substrate; a buffer layer positioned on the insulating substrate; an n+-type contact layer positioned on the buffer layer, the contact layer having a first surface and a second surface; an n-type cladding layer positioned on the first surface of the n+-type contact layer; a light-emitting layer positioned on the n-type cladding layer; a p-type cladding layer positioned on the light-emitting layer; a p-type contact layer positioned on the p-type cladding layer; an n+-type reverse-tunneling layer positioned on the p-type contact layer; a p-type transparent ohmic contact electrode positioned on the n+-type reverse-tunneling layer; and an n-type transparent ohmic contact electrode positioned on the second surface of the n+-type contact layer. The p-type transparent ohmic contact electrode and the n-type transparent ohmic contact electrode are made of the same materials.Type: GrantFiled: May 16, 2002Date of Patent: August 30, 2005Assignee: Epistar CorporationInventors: Shu-Wen Sung, Chin-Fu Ku, Chia-Cheng Liu, Min-Hsun Hsieh, Chao-Nien Huang, Chen Ou, Chuan-Ming Chang
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Patent number: 6933537Abstract: Disclosed is a technique for increasing the shelf life of devices, such as OLED which requires hermetic sealing from moisture and oxygen with out increasing the bonding width. In one embodiment, the permeation path of moisture or oxygen is increased without increasing the bonding width. This is achieved by using a grooved interface between the cap and substrate on which the components of the device are formed. The grooved interface can comprise various geometric shapes.Type: GrantFiled: September 28, 2001Date of Patent: August 23, 2005Assignees: Osram Opto Semiconductors GmbH, Institute of Materials Research & EngineeringInventors: Low Hong Yee, Ewald Guenther, Chua Soo Jin
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Patent number: RE38805Abstract: A semiconductor device comprises a single crystal substrate, a nucleus formation buffer layer formed on the single crystal substrate, and a lamination layer including a plurality of Al1-x-yGaxInyN (0?x?1, 0?y?1, x+y?1) layers laminated above the nucleus formation buffer layer. The nucleus formation buffer layer is formed of Al1-s-tGasIntN (0?s?1, 0?t?1, s+t?1) and is formed on a surface of the substrate such that the nucleus formation buffer layer has a number of pinholes for control of polarity and formation of nuclei. A method of fabricating a semiconductor device comprises the steps of: forming, above an Al1-x-yGaxInyN (0?x?1, 0?y?1, x+y?1) semiconductor layer doped with a p-type dopant, a cap layer for preventing evaporation of a constituent element of the semiconductor layer, the cap layer being formed of one of AlN in which a p-type dopant is added and Al2O3, subjecting the semiconductor layer to heat treatment, and removing at least a part of the cap layer.Type: GrantFiled: July 27, 2001Date of Patent: October 4, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yasuo Ohba, Ako Hatano