More Than Two Heterojunctions In Same Device Patents (Class 257/97)
  • Patent number: 6927424
    Abstract: A light emitting diode is composed of a generally T-shaped body section (36) and a resin forming section (37) projected on a front surface of the body section (36). The body section (36) has an upright portion (32) inserted into a hole (51) provided in a motherboard (50) and base portions (31a and 31b) which extend from the upright portion and which are mounted on a peripheral edge of the hole (51). The resin forming section (37) includes a non-translucent frame (40) extending from a front surface of the upright portion (32) and an extension part (41) further projecting forwardly larger than the frame. The extension part (41) has a mounted portion (42) mounted on the peripheral edge of the hole (51) of the motherboard (50). Mounted in the concave portion (44) provided in the frame (40) is a light emitting diode element (34), which is sealed by a sealing body (45) of a translucent resin.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: August 9, 2005
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Hidemoto Uekusa
  • Patent number: 6924512
    Abstract: A nitride semiconductor light emitting device includes an emission layer (106) having a multiple quantum well structure where a plurality of quantum well layers and a plurality of barrier layers are alternately stacked. The quantum well layer is formed of XN1-x-y-zAsxPySbz (0?x?0.15, 0?y?0.2, 0?z?0.05, x+y+z>0) where X represents one or more kinds of group III elements. The barrier layer is formed of a nitride semiconductor layer containing at least Al.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: August 2, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuhzoh Tsuda, Takayuki Yuasa, Shigetoshi Ito
  • Patent number: 6921925
    Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: July 26, 2005
    Inventors: Fred A. Kish, Jr., Sheila K. Mathis, Charles H. Joyner, Richard P. Schneider
  • Patent number: 6919585
    Abstract: A light-emitting diode is based on an undoped intrinsic SiC substrate on which are grown: an insulating buffer or nucleation structure; a light-emitting structure; window layers; a semi-transparent conductive layer; a bond pad adhesion layer; a p-type electrode bond pad; and an n-type electrode bond pad. In one embodiment, the light-emitting surface of the substrate is roughened to maximize light emission.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: July 19, 2005
    Assignee: Lumei Optoelectronics, Inc.
    Inventor: Heng Liu
  • Patent number: 6911675
    Abstract: A semiconductor device reduced in size is provided in which the surface area outside of a display portion required for IC chips to mounted is reduced in a semiconductor device having an active matrix display portion. Further, signal wiring connection defects that accompany IC chip mounting are reduced. By manufacturing TFTs on an opposing substrate in a reflecting active matrix semiconductor device, thus manufacturing a desired logic circuit, the logic circuit, conventionally mounted externally, is formed on the opposing substrate. Further, the semiconductor device is made high speed and high performance by using suitable TFT structures and electric power source voltages for pixels and driver circuits on a pixel substrate and for the logic circuit on the opposing substrate.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: June 28, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tadafumi Ozaki, Kohei Mutaguchi
  • Patent number: 6906358
    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. At least one extraction region is disposed on a first side of the active region and has a majority carrier of the second conductivity type. Carriers of the second conductivity type are extracted from the active region and into the extraction region under a condition of reverse bias. At least one exclusion region is disposed on a second side of the active region and has a majority carrier of the first conductivity type. The exclusion region prevents entry of its minority carriers, which are of the second conductivity type, into the active region while in a condition of reverse bias. The exclusion region includes a superlattice with a plurality of layers.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: June 14, 2005
    Assignee: EPIR Technologies, Inc.
    Inventors: Christoph H. Grein, Silviu Velicu, Sivalingam Sivananthan
  • Patent number: 6906352
    Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The structure includes a first n-type cladding layer of AlxInyGa1?x?yN, where 0?x?1 and 0?y<1 and (x+y)?1; a second n-type cladding layer of AlxInyGa1?x?yN, where 0?x?1 and 0?y<1 and (x+y)?1, wherein the second n-type cladding layer is further characterized by the substantial absence of magnesium; an active portion between the first and second cladding layers in the form of a multiple quantum well having a plurality of InxGa1?xN well layers where 0<x<1 separated by a corresponding plurality of AlxInyGa1?x?yN barrier layers where 0?x?1 and 0?y?1; a p-type layer of a Group III nitride, wherein the second n-type cladding layer is positioned between the p-type layer and the multiple quantum well; and wherein the first and second n-type cladding layers have respective bandgaps that are each larger than the bandgap of the well layers.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: June 14, 2005
    Assignee: Cree, Inc.
    Inventors: John Adam Edmond, Kathleen Marie Doverspike, Hua-Shuang Kong, Michael John Bergmann, David Todd Emerson
  • Patent number: 6903379
    Abstract: A light emitting diode incorporating an active emitting layer (14) overlying a transparent substrate (10) is provided with a reflective diffraction grating (30) on the bottom surface of the substrate. Emitted light passing downwardly through the substrate is diffracted outwardly toward edges (21) of the substrate and passes out of the die through the edges. This effect enhances the external quantum efficiency of the diode.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: June 7, 2005
    Assignee: GELcore LLC
    Inventors: Michael Wang, Hari Venugopalan
  • Patent number: 6900466
    Abstract: A semiconductor component for generating a polychromatic electromagnetic radiation has a semiconductor chip with a first semiconductor layer and a second semiconductor layer, which is provided adjacent to the first semiconductor layer and has an electroluminescent region. The electroluminescent region emits electromagnetic radiation of a first wavelength. The first semiconductor layer includes a material which, when excited with the electromagnetic radiation of the first wavelength, re-emits radiation with a second wavelength which is longer than the first wavelength.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: May 31, 2005
    Assignee: Osram GmbH
    Inventors: Detlef Hommel, Helmut Wenisch
  • Patent number: 6898340
    Abstract: A semiconductor light-emitting element 10 includes a silicon single crystal substrate 20 having a first and a second surfaces 20a, 20b in head-tail relationship with each other, a GaN-based semiconductor laminate 40 formed on a selected region of the first surface with a predetermined conductive intermediate layer 25 interposed therebetween, a first electrode layer 51 having a portion in contact with an uppermost layer of the GaN-based semiconductor laminate 40 and insulated from the monocrystal silicon substrate, and a second electrode layer 52 formed on a suitable portion of the monocrystal silicon substrate. The monocrystal silicon substrate 20 is formed with a light guide 30 for directing light emitted from the GaN-based semiconductor laminate 40 toward the second surface 20b.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: May 24, 2005
    Assignee: Rohm Co., Ltd.
    Inventor: Haruo Tanaka
  • Patent number: 6891202
    Abstract: An active semiconductor device, such as, buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices, comprise a plurality of semiconductor layers formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer. An example of a material system for this invention useful at optical telecommunication wavelengths is InGaAsP/InP where the Al-III-V layer comprises InAlAs:O or InAlAs:O:Fe.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: May 10, 2005
    Assignee: Infinera Corporation
    Inventors: Fred A. Kish, Jr., Sheila K. Mathis, Charles H. Joyner, Richard P. Schneider
  • Patent number: 6878563
    Abstract: This invention describes a radiation-emitting semiconductor component based on GaN, whose semiconductor body is made up of a stack of different GaN semiconductor layers (1). The semiconductor body has a first principal surface (3) and a second principal surface (4), with the radiation produced being emitted through the first principal surface (3) and with a reflector (6) being produced on the second principal surface (4). The invention also describes a production method for a semiconductor component pursuant to the invention. An interlayer (9) is first applied to a substrate (8), and a plurality of GaN layers (1) that constitute the semiconductor body of the component are then applied to this. The substrate (8) and the interlayer (9) are then detached and a reflector (6) is produced on a principal surface of the semiconductor body.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: April 12, 2005
    Assignee: Osram GmbH
    Inventors: Stefan Bader, Berthold Hahn, Volker Härle, Hans-Jürgen Lugauer, Manfred Mundbrod-Vangerow, Dominik Eisert
  • Patent number: 6876149
    Abstract: A double-faced LED device includes a substrate having opposed faces, a central recess formed in each of the opposed faces, a pair of electrode layers formed on each of the opposed faces, the electrode layer having a surface within the central recess formed into a reflector surface, and an LED securely mounted on the electrode layer within the central recess of each of the opposed faces, to which electric current may be applied to emit light from both of the opposed faces.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: April 5, 2005
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Shinichi Miyashita
  • Patent number: 6876002
    Abstract: A semiconductor laser element includes, on a substrate, at least a first conductive type first clad layer, an active layer, a second conductive type second clad layer, a current block layer having a stripe-shaped deficient portion extending in a direction of a resonator, a second conductive type third clad layer buried in the stripe-shaped deficient portion of the current block layer and a second conductive type protection layer provided on the third clad layer. The active layer includes at least a window region adjacent to its one end surface and an internal region having a quantum well structure, and a portion opposite to the internal region is irradiated with an ionized atom from a surface of a layer arranged on the second conductive type second clad layer side and thereafter subjected to heat treatment to form the window region.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: April 5, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mitsuhiro Matsumoto, Fumihiro Konushi, Shinichi Kawato
  • Patent number: 6872965
    Abstract: An undercoat layer inclusive of a metal nitride layer is formed on a substrate. Group III nitride compound semiconductor layers are formed on the undercoat layer continuously.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: March 29, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Jun Ito, Toshiaki Chiyo, Naoki Shibata, Hiroshi Watanabe, Shizuyo Asami, Shinya Asami
  • Patent number: 6870178
    Abstract: A quantum dot (QD) laser having greatly reduced temperature sensitivity employs resonant tunnel-injection of carriers into the QDs from a pair of quantum wells (QWs). The carriers are injected through barrier layers. Because the tunnel-injection process is essentially temperature-independent, and because the tunnel-injection of carriers is the dominant source of current through the device, temperature-dependent currents are virtually eliminated, resulting in a device having a temperature-independent threshold current. In an additional device, carriers are injected into QDs from a pair of optical confinement layers (OCLs), either by tunnelling or thermionic emission. Each barrier layer is designed to have a low barrier height for carriers entering the QDs, and a high barrier height for carriers exiting the QDs. As a result, parasitic current from carriers leaving the QDs is greatly reduced, which enables the device to have low temperature sensitivity even without using resonant tunnel-injection and/or QWs.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: March 22, 2005
    Inventors: Levon V. Asryan, Serge Luryi
  • Patent number: 6864501
    Abstract: A photon source includes a photon source body including quantum dots, a non-insulating layer overlying and in contact with the quantum dots, and an electrical contact that allows electrically activated emission of radiation from at least one of the quantum dots. An active region is defined within the photon source body such that emission is only collected from a dot or a limited number of dots within the active region.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: March 8, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Andrew James Shields, Richard Mark Stevenson, Beata Ewa Kardynal, Zhiliang Yuan
  • Patent number: 6858877
    Abstract: A facet-forming layer made of nitride semiconductor containing at least aluminum is formed on a substrate made of gallium nitride (GaN). A facet surface inclined with respect to a C-surface is formed on the surface of the facet-forming layer, and a selective growth layer laterally grows from the inclined facet surface. As a result, the selective growth layer can substantially lattice-match an n-type cladding layer made of n-type AlGaN and grown on the selective growth layer. For example, a laser structure without cracks being generated can be obtained by crystal growth.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: February 22, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasutoshi Kawaguchi, Akihiko Ishibashi, Ayumu Tsujimura, Nobuyuki Otsuka
  • Patent number: 6852993
    Abstract: An integrated circuit includes a semiconductor device forming a single photon source, and includes a MOS transistor on a silicon substrate. The MOS transistor has a mushroom shaped gate for outputting a single electron on its drain in a controlled manner in response to a control voltage applied to its gate. The transistor also includes at least one silicon compatible quantum box. The quantum box is electrically coupled to the drain region of the transistor, and is capable of outputting a single photon on reception of a single electron emitted by the transistor.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: February 8, 2005
    Assignee: STMicroelectronics SA
    Inventors: Stéphane Monfray, Didier Dutartre, Frédéric Boeuf
  • Patent number: 6853008
    Abstract: A semiconductor device has a structure in which a GaAs substrate and an InP substrate, different in lattice constant, are bonded to each other. An amorphous layer made of constituent atoms of the GaAs and InP substrates is formed at the interface between the GaAs and InP substrates. Forming the amorphous layer makes it possible to prevent a reduction of light-emitting efficiency caused by a thermal stress at the interface, even when a light-emitting layer by laser oscillation is formed near the interface. Besides, a linear current-voltage characteristic can be obtained at the interface.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: February 8, 2005
    Assignee: Fujitsu Limited
    Inventor: Norihiko Sekine
  • Patent number: 6849862
    Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: February 1, 2005
    Assignee: Technologies and Devices International, Inc.
    Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
  • Patent number: 6847046
    Abstract: A light-emitting device and a method for manufacturing the same are described, by forming a SiN/Al1-x-yInxGayN(0?x?1, 0?y?1, x+y?1) superlattice layer between a substrate and an undoped GaN as a buffer layer, so as to reduce dislocation density of the buffer layer. In the SiN/Al1-x-yInxGayN(0?x?1, 0?y?1, x+y?1) superlattice layer, Al1-x-yInxGayN(0?x?1, 0?y?1, x+y?1) can be n-type, p-type or undoped.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: January 25, 2005
    Assignees: Epitech Corporation, Ltd.
    Inventors: Shih-Chen Wei, Yung-Hsin Shie, Wen-Liang Li, Shi-Ming Chen
  • Patent number: 6844227
    Abstract: In a field effect transistor, an Si layer, an SiC (Si1-yCy) channel layer, a CN gate insulating film made of a carbon nitride layer (CN) and a gate electrode are deposited in this order on an Si substrate. The thickness of the SiC channel layer is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region and a drain region are formed on opposite sides of the SiC channel layer, and a source electrode and a drain electrode are provided on the source region and the drain region, respectively.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: January 18, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
  • Patent number: 6844565
    Abstract: According to the invention, a semiconductor component for the emission of electromagnetic radiation, especially light, is made that has the following features: an active layer for producing radiation, a p-type contact that is electrically connected to the active layer, an n-type contact that is electrically connected to the active layer, and a current-confining structure to define a current path, with the current-confining structure being provided between the n-type contact and the active layer.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: January 18, 2005
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Alfred Lell, Volker Härle, Berthold Hahn, Johann Luft
  • Patent number: 6844569
    Abstract: The present invention relates to a fabrication method of nitride-based semiconductors and a nitride-based semiconductor fabricated thereby. In the fabrication method of the invention, a self-organizing metal layer is formed on a sapphire substrate. The sapphire substrate having the self-organizing metal layer is heated so that self-organizing metal coalesces into nanoscale clusters to irregularly expose an upper surface of the sapphire substrate. Exposed portions of the sapphire substrate is plasma etched using the self-organized metal clusters as a mask to form a nanoscale uneven structure on the sapphire substrate. A resultant structure is wet etched to remove the self-organized metal clusters. The nanoscale uneven structure formed on the sapphire substrate decreases the stress and resultant dislocation between the sapphire substrate and a nitride-based semiconductor layer as well as increases the quantum efficiency between the same.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: January 18, 2005
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyu Han Lee, Sun Woon Kim, Je Won Kim
  • Patent number: 6841800
    Abstract: In the light-emitting gallium-nitride-group compound semiconductor devices using a substrate, the operating voltage is lowered and at the same time the occurrence of crack during crystal growth is suppressed, resulting in an improved manufacturing yield rate. The device includes a stacked structure of an n-type layer, a light-emitting layer and a p-type layer formed in the foregoing order on a substrate, and an n-side electrode formed on the surface of the n-type layer. The n-type layer is a laminate layer composed of, in the order from the substrate, first n-type layer and a second n-type layer having a carrier concentration higher than that of the first n-type layer. As the contact resistance between the n-type layer and the n-side electrode formed thereon is reduced, the operating voltage of a light-emitting device is lowered, and the power consumption decreased.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: January 11, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunari Oku, Hidenori Kamei
  • Patent number: 6841860
    Abstract: Disclosed are a flip-chip bonding structure for improving the vertical alignment of an optical device relative to a PLC and a flip-chip bonding method for achieving this structure. The flip-chip bonding structure includes: a semiconductor substrate; a lower-clad layer formed on the upper surface of the semiconductor substrate, wherein the lower-clad layer is depressed on a designated area for mounting an optical device; vertical alignment structures formed on a part of the upper surface of the depressed area of the lower-clad layer and determining a vertical alignment position of the optical device on the semiconductor substrate; electrodes formed on another part of the upper surface of the depressed area of the lower-clad layer; a solder bump formed on the upper surfaces of the electrodes; and, an optical device bonded to the substrate by a flip-chip bonding method using the solder bump.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: January 11, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Hoon Lee, Duk-Yong Choi, Dong-Su Kim
  • Patent number: 6838705
    Abstract: The present invention provides a nitride semiconductor light emitting device with an active layer of the multiple quantum well structure, in which the device has an improved luminous intensity and a good electrostatic withstanding voltage, thereby allowing the expanded application to various products. The active layer 7 is formed of a multiple quantum well structure containing InaGa1?aN (0?a<1). The p-cladding layer 8 is formed on said active layer containing the p-type impurity. The p-cladding layer 8 is made of a multi-film layer including a first nitride semiconductor film containing Al and a second nitride semiconductor film having a composition different from that of said first nitride semiconductor film. Alternatively, the p-cladding layer 8 is made of single-layered layer made of AlbGa1?bN (0?b?1). A low-doped layer 9 is grown on the p-cladding layer 8 having a p-type impurity concentration lower than that of the p-cladding layer 8.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: January 4, 2005
    Assignee: Nichia Corporation
    Inventor: Koji Tanizawa
  • Patent number: 6835962
    Abstract: A stacked layer structure including a single crystal substrate; an amorphous or polycrystalline buffer layer formed from a boron-containing Group III-V compound semiconductor. The buffer layer is provided on the substrate; a cladding layer formed from a boron-containing Group III-V compound semiconductor is provided on the buffer layer; and a light-emitting layer having a quantum well structure including a barrier layer formed from a boron-containing Group III-V compound semiconductor and a well layer formed from a Group III nitride semiconductor is provided on the cladding layer. The barrier layer is formed from a boron-containing Group III-V compound semiconductor having the same lattice constant as a boron-containing Group III-V compound semiconductor constituting the cladding layer.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: December 28, 2004
    Assignee: Showa Denko Kabushiki Kaisha
    Inventor: Takashi Udagawa
  • Publication number: 20040232433
    Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.
    Type: Application
    Filed: April 3, 2002
    Publication date: November 25, 2004
    Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-Shuang Kong, Heidi Marie Dieringer, David B. Slater
  • Patent number: 6815731
    Abstract: A light emitting semiconductor device, which includes a Ga0.9In0.1As0.97 active layer disposed between lower n-Ga0.5In0.5P and upper p-Ga0.5In0.5P cladding layers, being provided with lower and upper GaAs spacing layers each intermediate the active layer and the cladding layer. The active layer is approximately lattice-matched to a GaAs substrate and has a thickness of about 0.1 &mgr;m with a photoluminescence peak wavelength of approximately 1.3 &mgr;m, and the GaAs spacing layers each have a thickness of about 2 nm.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 9, 2004
    Assignee: Ricoh Company Ltd.
    Inventor: Shunichi Sato
  • Publication number: 20040206969
    Abstract: Projections/depressions of a two-dimensional periodic structure are formed in a p-GaN layer (4) such that the period of the projections/depressions is 1 to 20 times the wavelength of light radiated from an active layer (3) in a semiconductor. As a result, a diffractive effect achieved by the projections/depressions of the two-dimensional periodic structure change the direction in which the light radiated from the active layer (3) travels. If the projections/depressions are not provided, light at a radiation angle which satisfies conditions for total reflection at the interface between a semiconductor device and an air cannot be extracted to the outside of the semiconductor device so that the light emission efficiency of the device is low.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 21, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Kenji Orita
  • Patent number: 6803243
    Abstract: A method for forming an ohmic contact to silicon carbide for a semiconductor device comprises implanting impurity atoms into a surface of a silicon carbide substrate thereby forming a layer on the silicon carbide substrate having an increased concentration of impurity atoms, annealing the implanted silicon carbide substrate, and depositing a layer of metal on the implanted surface of the silicon carbide. The metal forms an ohmic contact “as deposited” on the silicon carbide substrate without the need for a post-deposition anneal step.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: October 12, 2004
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Alexander Suvorov
  • Patent number: 6800876
    Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a Group III nitride active layer positioned between a first n-type Group III nitride cladding layer and a second n-type Group III nitride cladding layer, the respective bandgaps of the first and second n-type cladding layers being greater than the bandgap of the active layer. The semiconductor structure further includes a p-type Group III nitride layer, which is positioned in the semiconductor structure such that the second n-type cladding layer is between the p-type layer and the active layer.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: October 5, 2004
    Assignee: Cree, Inc.
    Inventors: John Adam Edmond, Kathleen Marie Doverspike, Hua-shuang Kong, Michael John Bergmann
  • Patent number: 6797986
    Abstract: Is provided a resonant cavity type light emitting diode having excellent humidity durability and a light output unsaturated even several 10 mA., which is suitable for mass production. The semiconductor light emitting element has a resonator formed by one set of multi-layer reflecting films disposed at a constant distance on a GaAs substrate inclined at an angle of not less than 2 degrees in the direction [011] or [0-1-1] from the plane (100) and a light emitting layer disposed at a loop position of a standing wave in the resonator, wherein a multi-layer reflecting film disposed on the GaAs substrate side is composed of plural layers of AlxGa1-xAs (0 ≦x≦1) and a multi-layer reflecting film disposed on the opposite side of the GaAs substrate is composed of plural layers of AlyGazIn1-y-zP (0≦y≦1, 0≦z≦1), thereby achieving an improved humidity durability and an increased reflection factor by increasing the number of the reflection layers.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 28, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takahisa Kurahashi, Hiroshi Nakatsu, Hiroyuki Hosoba, Tetsurou Murakami
  • Patent number: 6787383
    Abstract: The light-emitting device 100 has an ITO electrode layer 8 for applying drive voltage for light emission to a light emitting layer section 24, where the light from the light emitting layer section 24 is extracted as being passed through the ITO electrode layer 8. Between the light emitting layer section 24 and the ITO electrode layer 8, an electrode contact layer 7 composed of In-containing GaAs is located so as to contact with such ITO electrode layer 8, where occupied areas and unoccupied areas for the electrode contact layer 7 are arranged in a mixed manner on the contact interface with the transparent electrode layer 8. The electrode contact layer 7 can be obtained by annealing a stack 13, which comprises a GaAs layer 7″ formed on the light emitting layer section 24 and the ITO electrode layer 8 formed so as to contact with the GaAs layer 7″, to thereby allow In to diffuse from the ITO electrode layer to the GaAs layer 7″.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: September 7, 2004
    Assignees: Shin-Etsu Hanotai Co., Ltd., Nanoteco Corporation
    Inventors: Shunichi Ikeda, Masato Yamada, Nobuhiko Noto, Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
  • Patent number: 6784462
    Abstract: A high extraction efficiency, light-emitting diode having a reflective submount and methods for forming the LED. A light-emitting region is disposed between a top contact and a conductive holder. The region extends beyond an area underlying the top contact. An omni-directional reflector is disposed between the light-emitting region and the conductive holder. According to one embodiment, the reflector comprises one or more electrically conductive contacts configured to correspond to an area beyond the area underlying the top contact. According to one embodiment, the reflector comprises a dielectric layer having a refractive index of between about 1.10 and 2.25, contacts extending through the reflector, and a reflective conductive film.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Rensselaer Polytechnic Institute
    Inventor: E. Fred Schubert
  • Patent number: 6784461
    Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a first cladding layer of a Group III nitride, a second cladding layer of a Group III nitride, and an active layer of a Group III nitride that is positioned between the first and second cladding layers, and whose bandgap is smaller than the respective bandgaps of the first and second cladding layers. The semiconductor structure is characterized by the absence of gallium in one or more of these structural layers.
    Type: Grant
    Filed: March 1, 2003
    Date of Patent: August 31, 2004
    Assignee: Cree, Inc.
    Inventors: John Adam Edmond, Kathleen Marie Doverspike, Hua-shuang Kong, Michael John Bergmann
  • Patent number: 6781158
    Abstract: A GaAsP-base light emitting element capable of sustaining an excellent light emission property for a long period, and a method for manufacturing thereof are provided. The light emitting element 1 has a p-n junction interface responsible for light emission formed between a p-type GaAs1-aPa layer 9 and an n-type GaAs1-aPa layer 8, and has a nitrogen-doped zone 8c formed in a portion including the p-n junction interface between such p-type GaAs1-aPa layer 9 and n-type GaAs1-aPa layer 8. Such element can be manufactured by fabricating a plurality of light emitting elements by varying nitrogen concentration Y of the nitrogen-doped zone 8c while keeping a mixed crystal ratio a of the p-type GaAs1- aPa layer 9 and n-type GaAs1-aPa layer 8 constant; finding an emission luminance/nitrogen concentration relationship by measuring emission luminance of the individual light emitting elements; and adjusting the nitrogen concentration of the nitrogen-doped zone 8c so as to fall within a range from 1.05Yp to 1.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: August 24, 2004
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Akio Nakamura, Masayuki Shinohara, Masahisa Endo
  • Patent number: 6777768
    Abstract: A semiconductor optical component is disclosed which includes a semiconductor material confinement layer containing acceptor dopants such that the doping is p-type doping. The confinement layer is deposited on another semiconductor layer and defines a plane parallel to the other semiconductor layer. Furthermore, the p-type doping concentration of the confinement layer has at least one gradient significantly different from zero in one direction in the plane. A method of fabricating the component is also disclosed.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: August 17, 2004
    Assignee: Avanex Corporation
    Inventors: Léon Goldstein, Christophe Ougier, Denis Leclerc, Jean Decobert
  • Patent number: 6773948
    Abstract: A semiconductor light emitting device of the present invention includes: a substrate; a light emitting layer; a semiconductor layer of a hexagonal first III-group nitride crystal; and a cladding layer of a second III-group nitride crystal. A stripe groove is provided in the semiconductor layer along a <1, 1, −2, 0> direction.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinji Nakamura, Masahiro Ishida, Masaaki Yuri, Osamu Imafuji, Kenji Orita
  • Patent number: 6774410
    Abstract: The present invention provides a semiconductor device with reducing dislocation density. The semiconductor device includes multiple nucleuses between a substrate and an AlGaInN compound semiconductor. The dislocation density that is induced by crystal lattice differences between the substrate and the AlGaInN compound semiconductor is significantly reduced and the growth of the AlGaInN compound semiconductor is improved.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: August 10, 2004
    Assignee: United Epitaxy Company
    Inventors: Chih-Sung Chang, Tzong-Liang Tsai
  • Patent number: 6768754
    Abstract: A laser system includes a laser diode with a low dimensional nanostructure, such as quantum dots or quantum wires, for emitting light over a wide range of wavelengths. An external cavity is used to generate laser light at a wavelength selected by a wavelength-selective element. The system provides a compact and efficient laser tunable over a wide range of wavelengths.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: July 27, 2004
    Assignee: National Research Council of Canada
    Inventor: Simon Fafard
  • Patent number: 6747406
    Abstract: A light source (10) includes a light emitting component (32), such as a UV/blue light emitting diode or laser diode coated with a layer (60) of a phosphor material (64). The phosphor material converts a portion of the light emitted by the light emitting component to light of a longer wavelength, such as yellow light. The thickness d of the layer varies across the light emitting component in relation to the intensity of light emitted by the light emitting component. This maintains a uniform color of the emission from the light source while minimizing the loss in light intensity (brightness) due to the presence of the phosphor.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: June 8, 2004
    Assignee: General Electric Company
    Inventors: Jacob C. Bortscheller, Robert J. Wojnarowski
  • Patent number: 6734530
    Abstract: A GaN-based compound semiconductor epi-wafer includes: a substrate 11 made of a first nitride semiconductor belonging to a hexagonal system; and an element layer 12 for forming a semiconductor element, which is made of a second nitride semiconductor belonging to the hexagonal system and which is grown on a principal surface of the substrate 11. An orientation of the principal surface of the substrate 11 has an off-angle in a predetermined direction with respect to a (0001) plane, and the element layer 12 has a surface morphology of a stripe pattern extending substantially in parallel to the predetermined direction.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industries Co., Ltd.
    Inventor: Yuzaburo Ban
  • Patent number: 6734453
    Abstract: A photonic device includes a silicon semiconductor based superlattice. The superlattice has a plurality of layers that form a plurality of repeating units. At least one of the layers in the repeating unit is an optically active layer with at least one species of rare earth ion.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: May 11, 2004
    Assignee: Translucent Photonics, Inc.
    Inventors: Petar B. Atanackovic, Larry R. Marshall
  • Patent number: 6720585
    Abstract: A low thermal impedance optoelectronic device includes an optical cavity adjacent a low thermal impedance DBR that provides improved heat dissipation and temperature performance. The thermal impedance of the DBR may be reduced by increasing the relative or absolute thickness of a layer of high thermal conductivity material relative to a layer of low thermal conductivity material for at least a portion of the mirror periods. The thermal impedance may also be reduced by increasing the distance between phonon scattering surfaces by increasing the thickness of the high thermal conductivity layer, the low thermal conductivity layer or both.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: April 13, 2004
    Assignee: Optical Communication Products, Inc.
    Inventors: John Wasserbauer, Ryan Likeke Naone, Andrew William Jackson
  • Patent number: 6717185
    Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a first cladding layer of a Group III nitride, a second cladding layer of a Group III nitride, and an active layer of a Group III nitride that is positioned between the first and second cladding layers, and whose bandgap is smaller than the respective bandgaps of the first and second cladding layers. The semiconductor structure is characterized by the absence of gallium in one or more of these structural layers.
    Type: Grant
    Filed: March 1, 2003
    Date of Patent: April 6, 2004
    Assignee: Cree, Inc.
    Inventors: John Adam Edmond, Kathleen Marie Doverspike, Hua-shuang Kong, Michael John Bergmann
  • Patent number: 6706620
    Abstract: A lower region having a composition of Alx1Gax2Inx3N (x1+x2+x3=1, 0.5≦x1≦1.0) is formed through epitaxial growth by a CVD method, and subsequently, an upper region having a composition of Aly1Gay2Iny3N (y1+y2+y3=1, 0≦y1≦x1−0.1) is formed through epitaxial growth by a CVD method. A boundary face divides a given III nitride film into the lower region and the upper region and the lower and upper regions have an Al content difference of 10 atomic percent or more.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: March 16, 2004
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Mitsuhiro Tanaka, Keiichiro Asai, Osamu Oda
  • Patent number: 6707074
    Abstract: A semiconductor light-emitting device has first and second semiconductor layers each of a first conductivity type, a third semiconductor layer of a second conductivity type provided between the first and second semiconductor layers, and an active layer provided between the second and third semiconductor layers to emit light with charge injected therein from the second and third semiconductor layers. A graded composition layer is provided between the active layer and the third semiconductor layer to have a varying composition which is nearly equal to the composition of the active layer at the interface with the active layer and to the composition of the third semiconductor layer at the interface with the third semiconductor layer.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: March 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Kiyoshi Ohnaka