With Rough Surface, E.g., Using Hemispherical Grains (epo) Patents (Class 257/E21.013)
  • Patent number: 10607833
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing supplying a precursor gas to the substrate; and supplying a first oxygen-containing gas to the substrate. Further, the act of supplying the precursor gas includes a time period in which the precursor gas and a second oxygen-containing gas are simultaneously supplied to the substrate.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 31, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Katsuyoshi Harada, Takashi Ozaki, Masato Terasaki, Risa Yamakoshi, Satoshi Shimamoto, Jiro Yugami, Yoshiro Hirose
  • Patent number: 10573551
    Abstract: An etching method and a fabrication method of semiconductor structures are provided. The etching method includes forming trenches in a to-be-etched structure, and forming a dielectric layer in the trenches. The etching method further includes etching the dielectric layer in the trenches by an etching process, and controlling at least an etching temperature of the etching process while a polymer is formed on side surface of the to-be-etched structure. During the etching process of the dielectric layer, the polymer undergoes a deposition stage and a removal stage. The deposition stage has a deposition rate of the polymer greater than an etch rate of the polymer, and the removal stage has the deposition rate of the polymer less than the etch rate of the polymer.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 25, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Min Da Hu, Er Hu Zheng, Cheng Long Zhang, Hai Yang Zhang
  • Patent number: 10431647
    Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harunobu Kondo, Kenichi Echigoya
  • Patent number: 10355075
    Abstract: Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second contact plugs each including side and upper surfaces, the side surfaces of the first and second contact plugs being surrounded by the first insulating film, the upper surfaces of the first and second contact plugs being substantially on the same plane with an upper surface of the first insulating layer; a second insulating layer over the first insulating layer; a first conductive layer including a bottom portion on the first contact plug and a side portion surrounded by the second insulating layer; a third insulating layer over the first conductive layer; and a second conductive layer on the second contact plug, a part of a side surface of the second conductive layer being surrounded by both the second and third insulating layers.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Takashi Sasaki
  • Patent number: 10217569
    Abstract: A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends elevationally. The first electrode has elevationally-extending first conductive material and has second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material. The laterally-projecting second conductive material has a vertical thickness that is less than that of the elevationally-extending first conductive material. Support material laterally supports the capacitor and contacts a tip end of the laterally-projecting second conductive material.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kenji Komeda, Kana Suzuki
  • Patent number: 10043888
    Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure includes a substrate and a plurality of fins formed on the substrate. Then, a first polysilicon layer is formed on the substrate. The first polysilicon layer covers at least portions of the fins. An amorphous silicon layer is formed on the first polysilicon layer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Hui Lin, Keng-Jen Lin, Yu-Ren Wang
  • Patent number: 10032563
    Abstract: A capacitor element including at least an anode body composed of a sintered compact containing tungsten as a main component, a dielectric layer with a smooth surface formed by chemical conversion of the surface of the anode body, and a semiconductor layer laminated on the dielectric layer. The capacitor is obtained by a production method which includes the steps of chemically converting the surface layer of the tungsten powder sintered compact into the dielectric layer in an aqueous solution containing 0.05 to 12% by mass of an oxidant composed of an oxygen-containing compound at a solution temperature of 62° C. or less, and removing all or most of water adhering to the inner surface of pores at a temperature of less than the boiling point of water, followed by drying at a temperature of not less than the boiling point of water.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: July 24, 2018
    Assignee: SHOWA DENKO K.K.
    Inventors: Kazumi Naito, Shouji Yabe
  • Patent number: 9893068
    Abstract: To effectively prevent short circuit between capacitors adjacent to each other. A semiconductor device has a substrate, an interlayer insulating film, a plurality of capacitors, and an isolation insulating film. The interlayer insulating film is located over the substrate. The capacitors are located in a plurality of recesses, respectively. The recesses each have an opening in the surface of the interlayer insulating film. The isolation insulating film lies in the interlayer insulating film. The isolation insulating films are located between recesses adjacent to each other in plan view. Further, the isolation insulating film is made of a material different from that of the interlayer insulating film.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroyuki Hoshizaki
  • Patent number: 9837264
    Abstract: A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Reiko Shamoto, Hideto Takekida
  • Patent number: 9818472
    Abstract: A semiconductor device includes a plurality of memory cells being disposed in a matrix in a memory cell array area, each of the memory cells includes a capacitive element including a cell plate electrode, a capacitive insulating film, and a storage node electrode, and a switch transistor coupled between the storage node electrode and a bit line and being controlled based on a potential of a word line, a peripheral circuit disposed in a peripheral circuit area adjacent to the memory cell array area, and a signal line formed at a boundary between the memory cell array area and the peripheral circuit area. The capacitive element has a cylinder shape. The storage node electrode is formed on inner wall of a hole which penetrates through a first insulating film layer and a second insulating film layer.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: November 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroyuki Takahashi
  • Patent number: 9761592
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device also includes a contact plug in the dielectric layer, and a recess extending from a surface of the dielectric layer towards the contact plug. The semiconductor device further includes a capacitor element in the recess and electrically connected to the contact plug.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Geng-Shuoh Chang, Yung-Tsun Liu, Chun-Sheng Wu, Chun-Li Lin, Yi-Fang Li
  • Patent number: 9711509
    Abstract: To effectively prevent short circuit between capacitors adjacent to each other. A semiconductor device has a substrate, an interlayer insulating film, a plurality of capacitors, and an isolation insulating film. The interlayer insulating film is located over the substrate. The capacitors are located in a plurality of recesses, respectively. The recesses each have an opening in the surface of the interlayer insulating film. The isolation insulating film lies in the interlayer insulating film. The isolation insulating films are located between recesses adjacent to each other in plan view. Further, the isolation insulating film is made of a material different from that of the interlayer insulating film.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: July 18, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroyuki Hoshizaki
  • Patent number: 9680016
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 13, 2017
    Assignee: INTEL CORPORATION
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann
  • Patent number: 9673295
    Abstract: A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Annie Levesque, Viorel C. Ontalus, Matthew W. Stoker
  • Patent number: 9666575
    Abstract: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ming-Hsiang Song, Jam-Wem Lee, Yi-Feng Chang, Wun-Jie Lin
  • Patent number: 9646877
    Abstract: A semiconductor device includes an interlayer insulating layer having openings, contact plugs formed in lower parts of the openings, wherein the contact plugs include a first conductive layer, and bit lines formed in upper parts of the openings and coupled to the contact plugs, wherein the bit lines include a second conductive layer.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 9, 2017
    Assignee: SK Hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 9548316
    Abstract: A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: January 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Sung Lim, Jang-Gn Yun, Sunghoon Bae, Jaesun Yun, Kyu-Baik Chang
  • Patent number: 9543308
    Abstract: A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoon Park, Young-Seok Kim, Yeong-Cheol Lee
  • Patent number: 9520323
    Abstract: Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 13, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael B Vincent, Zhiwei Gong, Scott M Hayes, Douglas G Mitchell
  • Patent number: 9478459
    Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures, and an etch buffer layer. The etch buffer layer includes an overhang component disposed on the upper portion of the gate structures with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent gate structures.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 25, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ya Hui Chang
  • Patent number: 9391069
    Abstract: An on-chip capacitor with enhanced capacitance and a method of forming the same are provided. An epitaxial process is employed to selectively form semiconductor material nodules on portions of a semiconductor material nodule nucleation layer that is present atop a semiconductor substrate. The semiconductor material nodules have an increased surface area for forming a capacitor structure thereon. A metal-insulator-metal capacitor structure is then formed surrounding each semiconductor material nodule. The resultant semiconductor structure (i.e., on-chip capacitor) has enhanced capacitance without increasing the size of the chip or the fabrication cost.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan
  • Patent number: 9324573
    Abstract: One method includes sequentially forming an insulating film and a first material film on a semiconductor substrate, forming on the first material film a mask film having a rectangular first opening, and dry-etching the first material film using the mask film as a mask to form an ellipsoidal second opening having its shorter side aligned in a first direction of the first material film. Forming the mask film includes forming a second material film having a side surface that faces the first direction of the first opening, and a third material film having side surfaces facing a second direction of the first opening, and the thickness of the third material film is greater than the thickness of the second material film.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: April 26, 2016
    Assignee: PS5 Luxco S.a.r.l.
    Inventor: Atsushi Maekawa
  • Patent number: 8975682
    Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Rebha El Farhane, Benoit Froment
  • Patent number: 8933535
    Abstract: A method of forming an insulating spacer is disclosed that includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion. A wafer is also disclosed.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Andrew B. Graham, Gary Yama, Gary O'Brien
  • Patent number: 8927346
    Abstract: An electrically, thermally, or electrically and thermally actuated device is disclosed herein. The device includes a substrate, a first electrode established on the substrate, an active region established on the electrode, and a second electrode established on the active region. A pattern is defined in at least one of the substrate, the first electrode, the second electrode, or the active region. At least one of grain boundaries are formed within, or surface asperities are formed on, at least one of the electrodes or the active region. The pattern controls the at least one of the grain boundaries or surface asperities.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: January 6, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Theodore I Kamins
  • Patent number: 8895442
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8884350
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota
  • Patent number: 8742542
    Abstract: A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Cheng Yang, Bo Tao, Jason Luo, Jinganag Wu
  • Patent number: 8575000
    Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 5, 2013
    Assignee: SanDisk Technologies, Inc.
    Inventors: Vinod R. Purayath, James K. Kai, Jayavel Pachamuthu, Jarrett Jun Liang, George Matamis
  • Patent number: 8441077
    Abstract: A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: May 14, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Sam Yang
  • Patent number: 8426286
    Abstract: A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Cheng Yang, Bo Tao, Jason Luo, Jingang Wu
  • Patent number: 8384143
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiyuki Hirota
  • Patent number: 8268703
    Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: September 18, 2012
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
  • Patent number: 8203176
    Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakagawa, Toru Tatsumi, Nobuyuki Ikarashi, Makiko Oshida
  • Patent number: 8169015
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 1, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiyuki Hirota
  • Patent number: 8080483
    Abstract: A method of forming a nanoporous film is disclosed. The method comprises forming a coating solution including clusters, surfactant molecules, a solvent, and one of an acid catalyst and a base catalyst. The clusters comprise inorganic groups. The method further comprises aging the coating solution for a time period to select a predetermined phase that will self-assemble and applying the coating solution on a substrate. The method further comprises evaporating the solvent from the coating solution and removing the surfactant molecules to yield the nanoporous film.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 20, 2011
    Assignee: Purdue Research Foundation
    Inventors: Hugh W. Hillhouse, Vikrant N. Urade, Ta-Chen Wei, Michael P. Tate
  • Patent number: 8080474
    Abstract: The present invention provides a method for making an electrode. Firstly, a conducting substrate is provided. Secondly, a plurality of nano-sized structures is formed on the conducting substrate by a nano-imprinting method. Thirdly, a coating is formed on the nano-sized structures. The nano-sized structures are configured for increasing specific surface area of the electrode.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: December 20, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ga-Lane Chen
  • Patent number: 8071476
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be structured as one or more monolayers. The cobalt titanium oxide film may be formed by atomic layer deposition.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: December 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8039344
    Abstract: In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Jin Lim, Jae-Hong Seo, Seok-Woo Nam, Bong-Hyun Kim, Taek-Soo Jeon
  • Patent number: 8021974
    Abstract: An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: September 20, 2011
    Assignee: Internatioanl Business Machines Corporation
    Inventors: Chih-Chao Yang, David Vaclav Horak, Takeshi Nogami, Shom Ponoth
  • Patent number: 8012858
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: removing a native oxide film and adhering silicon nitrides on an area of a Si based substrate in hydrogen gas atmosphere under a condition in which a pressure is a first pressure and a temperature is a first temperature, a silicon nitride-containing member being formed on the Si based substrate, the area being a area not covered by the member; lowering the temperature to a second temperature from the first temperature while maintaining the pressure at the first pressure in hydrogen gas atmosphere; lowering the pressure to a second pressure from the first pressure while maintaining the temperature at the second temperature in hydrogen gas atmosphere; and epitaxially growing a crystal on the area of the Si based substrate in a precursor gas atmosphere after the pressure is lowered to the second pressure, the crystal including at least one of Si and Ge, the precursor gas atmosphere including at least one of hydrogen, Si and Ge.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Murano, Ichiro Mizushima, Tsutomu Sato, Shinji Mori, Shuji Katsui, Hiroshi Itokawa
  • Patent number: 7989362
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 7872291
    Abstract: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: January 18, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej Singh Sandhu
  • Patent number: 7867885
    Abstract: A nanometer-scale post structure and a method for forming the same are disclosed. More particularly, a post structure, a light emitting device using the structure, and a method for forming the same, which is capable of forming a nanometer-scale post structure having a repetitive pattern by using an etching process, are disclosed. The method includes forming unit patterns on a substrate by use of a first material, growing a wet-etchable second material on the substrate formed with the unit patterns, and wet etching the substrate having the grown second material.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: January 11, 2011
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventor: Duk Kyu Bae
  • Patent number: 7825043
    Abstract: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component mixed in predetermined mole fractions of x, y and z, respectively; and forming a top electrode on the ZrxAlyOz dielectric layer.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-Jeung Lee
  • Patent number: 7812450
    Abstract: The present invention relates to an electrode 100 with high capacitance. The electrode includes a conducting substrate 10 with a number of nano-sized structures 13 thereon and a coating 15. The nano-sized structures are concave-shaped and are of a size in the range from 2 nanometers to 50 nanometers. The nano-sized structures are configured for increasing specific surface area of the electrode. The present invention also provides a method for making the above-described electrode. The method includes steps of providing a conducting substrate, forming a number of nano-sized structures on the conducting substrate, and forming a coating on the nano-sized structures.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: October 12, 2010
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ga-Lane Chen
  • Patent number: 7807477
    Abstract: In an embodiment of the present invention is provided a method of manufacturing a varactor, comprising providing a substrate; positioning a bottom electrode on a surface of the substrate; placing a tunable dielectric material adjacent to and extending over the bottom electrode forming a step and in contact with a top electrode; placing an interconnect layer in contact with the bottom electrode, the tunable dielectric and the top electrode.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: October 5, 2010
    Assignee: Paratek Microwave, Inc.
    Inventors: Xubai Zhang, Louise C. Sengupta, Jason Sun, Nicolaas DuToit
  • Patent number: 7781820
    Abstract: The semiconductor memory device includes: an interlayer insulating film that is formed on a semiconductor substrate; an insulating film that is formed on the interlayer insulating film and has a cylinder hole; and a capacitor that has an impurity-containing silicon film, a lower metal electrode, a capacitive insulating film and an upper electrode, which are formed so as to cover a bottom and a side of the cylinder hole, wherein the cylinder hole extends through the insulating film so as to expose an end side of the contact plug, the end side facing opposite from the source electrode; and the impurity-containing silicon film has a silicide layer near an interface between the impurity-containing silicon film and the lower metal electrode, the silicide layer being produced by a reaction of impurity-containing silicon included in the impurity-containing silicon film with metal included in the lower metal electrode.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: August 24, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Shigeru Sugioka
  • Patent number: 7741176
    Abstract: A method for fabricating a semiconductor device is disclosed. The semiconductor device includes a capacitor and a support insulator. The capacitor includes a cylindrical electrode. The cylindrical electrode comprises upper and lower sections. The lower section has a roughened inner surface and an outer surface supported by the support insulator. The upper section upwardly projects from the support insulator. An initial cylindrical electrode is formed, wherein the initial cylindrical electrode comprises an initial upper section and an initial lower section which correspond to the upper section and the lower section of the cylindrical electrode, respectively. The initial upper section is supported by the support insulator. Specific impurities are implanted into the initial upper section, wherein the specific impurities serve to prevent the initial upper section from being roughened.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: June 22, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Tomohiro Uno, Yoshitaka Nakamura
  • Patent number: 7732316
    Abstract: In accordance with an embodiment of the invention the method of manufacturing a semiconductor device is capable of forming a semiconductor substrate having an embossing structure. The method includes forming a layer having a plurality of hemispherical single crystal silicon elements, and forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements, thereby, increasing a length of an effective channel of a transistor.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: June 8, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chi Hwan Jang