Abstract: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component mixed in predetermined mole fractions of x, y and z, respectively; and forming a top electrode on the ZrxAlyOz dielectric layer.

Abstract: The present invention relates to an electrode 100 with high capacitance. The electrode includes a conducting substrate 10 with a number of nano-sized structures 13 thereon and a coating 15. The nano-sized structures are concave-shaped and are of a size in the range from 2 nanometers to 50 nanometers. The nano-sized structures are configured for increasing specific surface area of the electrode. The present invention also provides a method for making the above-described electrode. The method includes steps of providing a conducting substrate, forming a number of nano-sized structures on the conducting substrate, and forming a coating on the nano-sized structures.

Abstract: In an embodiment of the present invention is provided a method of manufacturing a varactor, comprising providing a substrate; positioning a bottom electrode on a surface of the substrate; placing a tunable dielectric material adjacent to and extending over the bottom electrode forming a step and in contact with a top electrode; placing an interconnect layer in contact with the bottom electrode, the tunable dielectric and the top electrode.

Abstract: The semiconductor memory device includes: an interlayer insulating film that is formed on a semiconductor substrate; an insulating film that is formed on the interlayer insulating film and has a cylinder hole; and a capacitor that has an impurity-containing silicon film, a lower metal electrode, a capacitive insulating film and an upper electrode, which are formed so as to cover a bottom and a side of the cylinder hole, wherein the cylinder hole extends through the insulating film so as to expose an end side of the contact plug, the end side facing opposite from the source electrode; and the impurity-containing silicon film has a silicide layer near an interface between the impurity-containing silicon film and the lower metal electrode, the silicide layer being produced by a reaction of impurity-containing silicon included in the impurity-containing silicon film with metal included in the lower metal electrode.

Abstract: A method for fabricating a semiconductor device is disclosed. The semiconductor device includes a capacitor and a support insulator. The capacitor includes a cylindrical electrode. The cylindrical electrode comprises upper and lower sections. The lower section has a roughened inner surface and an outer surface supported by the support insulator. The upper section upwardly projects from the support insulator. An initial cylindrical electrode is formed, wherein the initial cylindrical electrode comprises an initial upper section and an initial lower section which correspond to the upper section and the lower section of the cylindrical electrode, respectively. The initial upper section is supported by the support insulator. Specific impurities are implanted into the initial upper section, wherein the specific impurities serve to prevent the initial upper section from being roughened.

Abstract: In accordance with an embodiment of the invention the method of manufacturing a semiconductor device is capable of forming a semiconductor substrate having an embossing structure. The method includes forming a layer having a plurality of hemispherical single crystal silicon elements, and forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements, thereby, increasing a length of an effective channel of a transistor.

Abstract: A high surface area capacitor structure includes a storage electrode with recesses. An upper surface of the storage electrode has a maze-like appearance. Low elevation regions of a hemispherical grain polysilicon layer may remain on the upper surface of the storage electrode. The storage electrode or portions thereof may be lined or coated with dielectric material. The dielectric material may space a cell electrode of the high surface area capacitor structure apart from the storage electrode. One or both of the storage electrode and the cell electrode may be formed from polysilicon. Intermediate structures, which include mask material over contiguous low elevation regions of a layer of hemispherical grain polysilicon, which may have a maze-like appearance, and apertures located laterally between the low elevation regions of the layer of hemispherical grain polysilicon, are also disclosed.

Abstract: A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.

Abstract: The capacitance of a capacitor is adjusted by forming openings in one of a pair of electrodes of the capacitor, the openings having different sizes d1, d2, d3, . . . , wherein d1>d2>d3> . . . and being arranged in numbers n1, n2, n3, . . . , respectively; and sequentially filling a necessary number of the openings with an electroconductive material in descending order of the size so as to adjust the capacitance gradually with an increasing degree of precision. The resulting capacitor is mounted to a printed wiring board.

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface.

Abstract: Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by modifying process conditions to cause metal agglomeration or by treating the substrate surface to provide a limited number of discontinuous reactive sites. The roughened metal surface may be used, for example, in the manufacture of integrated circuits.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.

Abstract: Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

Abstract: Provided is a capacitor for a semiconductor device. The capacitor comprises a bottom electrode, a dielectric pattern, and a top electrode. The bottom electrode has an uneven surface. The dielectric pattern is on the bottom electrode, and the top electrode is on the dielectric pattern. The bottom electrode has a first height in edge and center regions thereof, and a protrusion between the edge region and the center region of the bottom electrode having a second height greater than the first height.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.

Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.

Abstract: The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises inner and outer electrodes and a dielectric layer. The buried isolation collar is recessed into a sidewall of the trench and has a substantially uniform thickness. Such a buried isolation collar is preferably formed by oxygen implantation before trench etching.

Abstract: The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an upper electrode formed over the dielectric layer.

Abstract: In a semiconductor device having a concave-type capacitor, HSG silicon is formed on a side surface of a lower electrode while no HSG silicon is formed on a bottom of the lower electrode.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: A storage capacitor plate for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to formed a substantially continuous porous conductive layer.

Abstract: It is an object of the present invention to provide a porous body containing an oxide semiconductor in which more efficient photocatalytic reactions and photoelectrode reactions occur. The present invention relates to a porous body having a network structure skeleton wherein 1) the aforementioned skeleton is composed of an inner part and a surface part, 2) the aforementioned inner part is substantially made of carbon material, and 3) all or part of the aforementioned surface part is an oxide semiconductor, and to a manufacturing method therefor.

Abstract: A method of manufacturing electric double layer capacitors is disclosed. The method assumes a model in which solute is dissolved in solvent before preparing electrolyte, and estimates a withstanding voltage through a simulation. The electrolyte, of which withstanding voltage is expected to exceed a target value, is selectively prepared. The method adjusts respective surface areas of the positive electrode and the negative electrode of the capacitor for making full use of the withstanding voltage of the electrolyte. According to this method, a time for developing electrolyte can be substantially shortened, and an electric double layer capacitor having a high withstanding voltage can be efficiently developed.

Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. Photoimageable material is used to facilitate positioning of the capacitive dielectric being printed. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.

Abstract: A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.