Made By Patterning Layers, E.g., Etching Conductive Layers (epo) Patents (Class 257/E21.02)
  • Patent number: 10355072
    Abstract: A method for forming a trench capacitor without an additional mask adder and the resulting device are provided. Embodiments include forming a buried implant layer over a substrate; forming an EPI layer over the buried implant layer; forming an oxide layer over the EPI layer; forming a nitride layer over the oxide layer; forming first and second trenches in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the first trench being wider and deeper than the second trench; forming a dielectric layer in the trenches; forming a first polysilicon layer over the dielectric layer in the trenches; removing the first polysilicon layer and the dielectric layer above the EPI layer in the trenches and at a bottom of the first trench; and forming a second polysilicon layer filling the first trench and above the EPI layer in the second trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zeng Wang, Wei Si, Jeoung Mo Koo, Purakh Raj Verma
  • Patent number: 10290509
    Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 14, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Sangmin Lee, Sinhae Do, Seok-Won Cho, Taeseop Choi, Kon Ha
  • Patent number: 10153205
    Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Wen-Chih Chiou, Jui-Pin Hung, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 9985033
    Abstract: A semiconductor device including a capacitor is provided. The semiconductor device includes lower electrodes, each of which includes a first electrode and a second electrode stacked in a first direction. The second electrode has a pillar shape that has a bar-type cross section having a longitudinal axis when viewed from a cross-sectional view taken along a plane defined by second and third directions perpendicular to the first direction.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taejin Park, Kyung-Eun Kim, Bong-Soo Kim, Ki-hyung Nam, Yoosang Hwang
  • Patent number: 9893019
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien Ma, Haw-Chuan Wu, Shih-Hao Tsai, Yu-Chuan Lin
  • Patent number: 9520459
    Abstract: A surface treatment method for a semiconductor device includes providing a substrate where a plurality of projected patterns are formed, forming a hydrophobic coating layer on a surface of each of the plurality of projected patterns, rinsing the substrate with deionized water, and drying the substrate, wherein the hydrophobic coating layer is formed using a coating agent that includes phosphate having more than one hydrocarbon group, phosphonate having more than one hydrocarbon group, or a mixture thereof.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: December 13, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Hyuk Cho, Hyo-Sang Kang, Sung-Ki Park, Kwon Hong, Hyung-Soon Park, Hyung-Hwan Kim, Young-Bang Lee, Ji-Hye Han, Tae-Yeon Jung, Hyeong-Jin Nor
  • Patent number: 8980762
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Iida, Yuji Kobayashi
  • Patent number: 8940601
    Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Youichi Yamamoto, Masayuki Tachikawa, Yoshitake Kato
  • Patent number: 8815740
    Abstract: A method for forming a pattern according to an embodiment, includes forming above a first film film patterns of a second film; forming film patterns of the first film by etching the first film using the film patterns of the second film as a mask; converting the film patterns of the second film into film patterns whose width are narrower than the film patterns of the first film by performing a slimming process; forming film patterns of a third film on both sidewalls of the film patterns of the first film and the film patterns of the second film after the slimming process; and etching the first film using the film patterns of the third film as a mask after the film patterns of the second film being removed.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Horiguchi, Takashi Ohashi
  • Patent number: 8643197
    Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sheila F. Chopin, Varughese Mathew, Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8623692
    Abstract: A method for manufacturing a solar cell is presented. The method includes: forming an amorphous silicon layer on a first surface of a light absorbing layer; doping the amorphous silicon layer with a dopant; forming a dopant layer by diffusing the dopant into the amorphous silicon layer with a laser; forming a semiconductor layer by removing the dopant that remains outside the dopant layer; etching the surface of the semiconductor layer by using an etchant; forming a first electrode on the semiconductor layer; and forming a second electrode on a second surface of the light absorbing layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Myung Su Kim, Min Chul Song, Soon Young Park, Dong Seop Kim, Sung Chan Park, Yoon Mook Kang, Tae Jun Kim, Min Ki Shin, Sang Won Lee, Heung Kyoon Lim
  • Patent number: 8617950
    Abstract: A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong Jin Kuh, Jong Cheol Lee, Yong Suk Tak, Young Sub You, Kyu Ho Cho, Jong Sung Lim
  • Patent number: 8575731
    Abstract: A semiconductor integrated circuit device with a balun which is formed above a conductive semiconductor substrate and which includes a dielectric film, an unbalanced line for transmitting an unbalanced signal, and balanced lines for transmitting a balanced signal. The unbalanced line is placed opposite to the balanced lines via a nano-composite film that is a region of the dielectric film. The nano-composite film, interposed between the unbalanced line and the balanced lines, has a relative permittivity higher than that of other regions of the dielectric film. This allows suppression of electromagnetic coupling of transmission lines or passive elements other than the balun, thereby providing a semiconductor device with a wide-band and small-size balun.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Shinji Ujita, Takeshi Fukuda, Hiroyuki Sakai
  • Patent number: 8481426
    Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-In Kim, Jaehee Oh, Kiseok Suh
  • Patent number: 8383437
    Abstract: An etchant according to exemplary embodiments of the present invention includes about 0.5 wt % to about 20 wt % of persulfate, about 0.01 wt % to about 2 wt % of a fluorine compound, about 1 wt % to about 10 wt % of inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 5 wt % of a chlorine compound, about 0.05 wt % to about 3 wt % of copper salt, about 0.1 wt % to about 10 wt % of organic acid or organic acid salt, and water.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 26, 2013
    Assignees: Samsung Display Co., Ltd., Dongwoo Fine-Chem Co., Ltd.
    Inventors: Ji-Young Park, Shin-Il Choi, Jong-Hyun Choung, Sang Gab Kim, Seon-Il Kim, Sang-Tae Kim, Joon-Woo Lee, Young-Chul Park, Young-Jun Jin, Kyong-Min Kang, Suck-Jun Lee, O-Byoung Kwon, In-Ho Yu, Sang-Hoon Jang, Min-Ki Lim, Yu-Jin Lee
  • Patent number: 8354347
    Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: January 15, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Chun Hui Low, Chim Seng Seet, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8314034
    Abstract: Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: Elliot N. Tan, Michael K. Harper
  • Publication number: 20120264268
    Abstract: Methods of forming nonvolatile memory devices include forming first and second floating gate electrodes of first and second nonvolatile memory cells, respectively, at side-by-side locations on a substrate. The substrate is selectively etched to define a trench therein extending between the first and second floating gate electrodes. The trench is at least partially filled with a first electrical insulation pattern. An inorganic polysilazane-type spin-on-glass (SOG) layer is conformally deposited on the first and second floating gate electrodes and on the first electrical insulation pattern and then partially removed.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 18, 2012
    Inventor: Ji-Hwon Lee
  • Patent number: 8268708
    Abstract: Silicon wafers polished on their front sides are individually placed on a susceptor in an epitaxy reactor and firstly pretreated under a hydrogen atmosphere, and secondly with addition of an etching medium with a flow rate of 1.5-5 slm to the hydrogen atmosphere, the hydrogen flow rate being 1-100 slm in both steps, and subsequently epitaxially coated on the polished front side, and then removed from the reactor. In a second method, gas flows introduced into the reactor by injectors are distributed into outer and inner zones of the chamber, such that the inner zone gas flow acts on a wafer central region and the outer zone gas flow acts on a wafer edge region, the inner/outer distribution of the etching medium I/O=0-0.75. Silicon wafers having an epitaxial layer having global flatness value GBIR of 0.02-0.06 ?m, relative to an edge exclusion of 2 mm are produced.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: September 18, 2012
    Assignee: Siltronic AG
    Inventors: Joerg Haberecht, Christian Hager, Georg Brenninger
  • Patent number: 8193099
    Abstract: A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mukesh V. Khare, Renee T. Mo, Ravikumar Ramachandran, Richard S. Wise, Hongwen Yan
  • Patent number: 8178958
    Abstract: The present invention provides an antenna in that the adhesive intensity of a conductive body formed on a base film is increased, and a semiconductor device including the antenna. The invention further provides a semiconductor device with high reliability that is formed by attaching an element formation layer and an antenna, wherein the element formation layer is not damaged due to a structure of the antenna. The semiconductor device includes the element formation layer provided over a substrate and the antenna provided over the element formation layer. The element formation layer and the antenna are electrically connected. The antenna has a base film and a conductive body, wherein at least a part of the conductive body is embedded in the base film. As a method for embedding the conductive body in the base film, a depression is formed in the base film and the conductive body is formed therein.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: May 15, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kyosuke Ito, Junya Maruyama, Takuya Tsurume, Shunpei Yamazaki
  • Patent number: 8138089
    Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction minor arrays on the substrate, each diffraction minor array of the set of at least three diffraction minor arrays comprising a single row of minors, all mirrors in any particular diffraction minor array spaced apart a same distance, minors in different diffraction minor arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Axel A. Granados, Benjamin A. Fox, Nathaniel J. Gibbs, Andrew B. Maki, Trevor J. Timpane
  • Patent number: 8124490
    Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: February 28, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang, Robert C. Frye
  • Patent number: 8076778
    Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 13, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuo Liang Wei, Hsu Sheng Yu, Hong-Ji Lee
  • Patent number: 8012811
    Abstract: A feature is formed in an integrated circuit by providing one or more layers to be patterned, providing a first layer overlying the one or more layers to be patterned, and providing a second layer overlying the first layer. The second layer is patterned to form a raised feature with one or more sidewalls. Subsequently, the first layer is processed such that components of the first layer deposit on the one or more sidewalls of the raised feature to form a mask. The mask is used to pattern the one or more layers to be patterned.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kuan-Neng Chen, John Christopher Arnold, Niranjana Ruiz
  • Patent number: 8003544
    Abstract: A method of manufacturing a semiconductor device according to an embodiment includes processing a second film 14 formed on a semiconductor substrate to a pattern including a plurality of linear parts and end portions formed in an end of each of the linear parts, having a width wider than the linear parts, forming a first pattern 16 by slimming the pattern, forming a second pattern including a first opening 180 that traverses the end portion 141a of the first pattern 16, etching the second film 14 exposed in the first opening 180, and dividing the end portion 141a into a first end portion 142a close to the linear part 140a and a second end portion 143a apart from the linear part 140a.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Sato, Keisuke Kikutani
  • Patent number: 7943470
    Abstract: The semiconductor device according to the present invention includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a silicon film in contact with an inner surface of the isolation trench, a silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the silicon films. According to the present invention, the silicon film within the isolation trench can be substantially regarded as a part of the silicon substrate. Therefore, even when the width of the isolation trench is increased to increase the etching rate, the width of the insulation film becoming a dead space can be made sufficiently small. Consequently, the chip area can be decreased.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 17, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 7939822
    Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 10, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Hideaki Kuwabara
  • Patent number: 7927959
    Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 19, 2011
    Assignee: Intel Corporation
    Inventors: Steven J. Keating, Nick Lindert, Nadia Rahhal-Orabi, Brian Doyle, Satyarth Suri, Swaminathan Sivakumar, Lana Jong, Lin Sha
  • Patent number: 7910483
    Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: March 22, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer K Abatchev, Krupaker Murali Subramanian, Baosuo Zhou
  • Patent number: 7888725
    Abstract: An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
  • Patent number: 7858451
    Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: December 28, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Hideaki Kuwabara
  • Patent number: 7847405
    Abstract: In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: December 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayoshi Watanabe, Yumi Hayashi, Takamasa Usui
  • Patent number: 7846801
    Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-jun Kim, Seong-kyu Yun, Chang-ki Hong, Bo-un Yoon, Jong-won Lee, Ho-young Kim
  • Publication number: 20100238536
    Abstract: A magneto-optical isolator device is provided. The isolator device includes a substrate and a bottom cladding layer that is formed on the substrate. An optical resonator structure is formed on the bottom cladding layer. The resonator structure includes crystalline or amorphous diamagnetic silicon or silicon-germanium so as to provide non-reciprocal optical isolation. A top cladding layer is formed on the resonator structure. One or more magnetic layers positioned on the top cladding layer or between the top cladding or bottom cladding layers and the optical resonator structure.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 23, 2010
    Inventors: Juejun Hu, Lei Bi, Lionel C. Kimerling, Gerald F. Dionne, Caroline A. Ross
  • Publication number: 20100133665
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed.
    Type: Application
    Filed: November 29, 2008
    Publication date: June 3, 2010
    Inventors: Jong-Woo Ha, TaeWoo Kang, DongSoo Moon
  • Patent number: 7700472
    Abstract: A method of forming a gate of a semiconductor device includes providing a semiconductor substrate over which a first conductive layer, a dielectric layer and a second conductive layer are formed. The second conductive layer is patterned to expose a part of the dielectric layer. A first protection layer is formed on sidewalls of the second conductive layer. A first etch process is performed to remove the exposed dielectric layer and to expose a part of the first conductive layer. A second protection layer is formed on sidewalls of the second conductive layer. A second etch process is performed to remove the exposed first conductive layer.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: April 20, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Soo Jin Kim
  • Patent number: 7700433
    Abstract: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on a surface of the lower electrode layer to have a depth less than the first trench. Forming a capacitor dielectric layer conformal along a surface of the lower electrode layer including the second trench. Forming an upper electrode layer of a metal nitride layer substance on the capacitor dielectric layer. Sequentially patterning the upper electrode layer and the capacitor dielectric layer by photolithography.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: April 20, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Sang-Il Hwang
  • Patent number: 7684003
    Abstract: A liquid crystal display device includes first and second substrates bonded to each other, first column spacers on the first substrate, protrusions on the second substrate that contact a center portion of an upper surface of the spacers, respectively, recesses formed in the second substrate surrounding the protrusions, respectively, and a liquid crystal layer between the first and second substrates.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: March 23, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Yoon Paik, Joon Youp Lee
  • Patent number: 7674710
    Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: March 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Shigeo Ashigaki, Hideaki Yamasaki, Tomoyuki Sakoda, Mikio Suzuki, Genji Nakamura, Gert Leusink
  • Patent number: 7674682
    Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: March 9, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Edmund Burke, Satyavolu S. Papa Rao, Timothy A. Rost
  • Patent number: 7670921
    Abstract: A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Anthony K. Stamper, Richard P. Volant
  • Patent number: 7662718
    Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer K. Abatchev, Krupakar Murali Subramanian, Baosuo Zhou
  • Patent number: 7655530
    Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: February 2, 2010
    Assignee: SB Electronics, Inc.
    Inventor: Terry Hosking
  • Patent number: 7646007
    Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100?x composition.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: January 12, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, John T. Moore
  • Publication number: 20090273747
    Abstract: A liquid crystal display and a manufacturing method thereof, including: a first substrate; a thin film transistor formed on the first substrate; a pixel electrode connected to the thin film transistor; a second substrate facing the first substrate; a first spacer formed on the second substrate and overlapping the thin film transistor; a second spacer formed on the second substrate and overlapping the pixel electrode; a common electrode formed on the second substrate, the first spacer, and the second spacer; and a liquid crystal layer disposed between the first substrate and the second substrate, wherein the pixel electrode and the common electrode disposed on the second spacer form a storage capacitor.
    Type: Application
    Filed: April 16, 2009
    Publication date: November 5, 2009
    Inventors: KYOUNG-JU SHIN, Cheol-Woo Park, Chang-Hoon Kim, Chang-Soon Jang
  • Publication number: 20090215231
    Abstract: In a method of manufacturing an electronic component built-in substrate of the present invention, a mounted body including a first insulating layer, a stopper metal layer formed under the first insulating layer of a portion corresponding to a component mounting region and a second insulating layer formed on a lower surface of the first insulating layer and covering the stopper metal layer is prepared, and a concave portion is obtained by penetration-processing a portion of the first insulating layer, which corresponds to the component mounting region to form an opening portion, while using the stopper metal layer as a stopper. Also, the stopper metal layer in the concave portion is removed, then an electronic component is mounted on the concave portion, and then a third insulating layer is formed on the electronic component.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 27, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD
    Inventor: Osamu INOUE
  • Patent number: 7547638
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming a circuit element on a semiconductor substrate, forming an insulation film covering the circuit element, forming a first electrode on the insulation film, forming a ferroelectric film on the first electrode, forming a second electrode on the ferroelectric film, forming a hardmask comprised of lower, middle, and upper layer mask films on the second electrode, etching the second electrode using the upper layer mask film as an etching mask, removing the upper layer mask film remaining after the etching of the second electrode, etching the ferroelectric film and the first electrode using the middle layer mask film as an etching mask, removing the middle layer mask film remaining after the etching of the ferroelectric film and the first electrode, and removing the lower layer mask film.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: June 16, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Takahashi
  • Publication number: 20090104739
    Abstract: Processes for non-selectively forming one or more conformal silicon-containing epitaxial layers on recess corners are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of a non-selective epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source such as silane and a higher order silane, followed by heating the substrate to promote solid phase epitaxial growth.
    Type: Application
    Filed: October 18, 2007
    Publication date: April 23, 2009
    Inventors: Zhiyuan Ye, Andrew Lam, Saurabh Chopra, Yihwan Kim
  • Patent number: 7482274
    Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: January 27, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa