Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a capacitor array and a supporting structure. A plurality of conductive contact plugs which are arranged at intervals are formed on the substrate. The capacitor array includes a plurality of columnar capacitors which are arranged at intervals. Each columnar capacitor is formed on a respective one of the conductive contact plugs. A lower electrode layer of the columnar capacitor is in contact connection with the conductive contact plug. The supporting structure is formed on the substrate at an edge of the capacitor array and surrounds the capacitor array. A spacing between an inner wall and an outer wall of the supporting structure on any cross section parallel to the substrate is greater than an aperture of a capacitor hole of any one of the columnar capacitors on the cross section.

Abstract: Some embodiments include an apparatus having a structure with a surface which comprises tungsten. The apparatus has titanium-nitride-containing protective material along and directly against the surface. The structure may be a digit line of a memory array. Some embodiments include a method in which an assembly is formed to have a tungsten-containing layer with an exposed tungsten-containing upper surface. Titanium-nitride-containing protective material is formed over and directly against the tungsten-containing upper surface. Additional material is formed over the protective material, and is spaced from the tungsten-containing upper surface by the protective material. The additional material may comprise silicon nitride and/or silicon dioxide.

Abstract: A method of forming ferroelectric hafnium oxide (HfO2) in a substrate processing system includes depositing an HfO2 layer on a substrate, depositing a capping layer on the HfO2 layer, annealing the HfO2 layer and the capping layer to form ferroelectric hafnium HfO2, and selectively etching the capping layer to remove the capping layer without removing the HfO2 layer.

Abstract: Disclosed herein is a method comprising: attaching a plurality of chips to a substrate, wherein each of the chips comprises only one pixel configured to detect radiation. Disclosed herein is a method comprising: attaching a wafer to a substrate, wherein the substrate comprises discrete electrodes, wherein the wafer comprises a radiation absorption layer and a plurality of electrical contacts, wherein each of the electrical contacts is connected to at least one of the discrete electrodes; identifying a defective area of the wafer; replacing a portion of the wafer with a chip configured to absorb radiation, the portion comprising the defective area.

Abstract: Embodiments relate to a method for manufacturing a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate in which a plurality of contact pads arranged in an array are provided, wherein the contact pad protrudes from the upper surface of the substrate; forming a first barrier layer on the substrate and the surface of the contact pad; forming a first conductive layer on the surface of the first barrier layer; etching the upper surface of the first conductive layer to form a first recessed structure and a second recessed structure, wherein the first recessed structure extends downward to the substrate, the projection of the first recessed structure on the substrate surrounds the contact pad, and the second recessed structure is formed in the first conductive layer and arranged above each of the corresponding contact pads.

Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

Abstract: A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

Abstract: Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.

Abstract: A method for forming a capacitor array includes depositing a first nitride layer, a first oxide layer, and a second nitride layer in sequence over first and second contacts on a substrate; etching the first nitride layer, the first oxide layer, and the second nitride layer to form first and second openings exposing the first and second contacts; conformally depositing a bottom electrode layer over the first and second nitride layers and the first oxide layer and on the first and second contacts; etching the second nitride layer and the first oxide layer to form a third opening having a bottom position higher than a top surface of the first nitride layer; removing the first oxide layer through the third opening; forming a capacitor dielectric layer over the bottom electrode layer; forming a top electrode layer over the capacitor dielectric layer.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode.

Abstract: A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

Abstract: Semiconductor memory devices and methods of forming the same are provided. The semiconductor devices may include a vertical insulating structure extending in a first direction on a substrate, a semiconductor pattern extending along a sidewall of the vertical insulating structure, a bitline on a first side of the semiconductor pattern, an information storage element on a second side of the semiconductor pattern and including first and second electrodes, and a gate electrode on the semiconductor pattern and extending in a second direction that is different from the first direction. The bitline may extend in the first direction and may be electrically connected to the semiconductor pattern. The first electrode may have a cylindrical shape that extends in the first direction, and the second electrode may extend along a sidewall of the first electrode.

Abstract: A semiconductor device includes a first substrate, a first insulating film provided on the first substrate, and a first plug provided in the first insulating film. The device further includes a first layer provided on the first insulating film and a first metal layer provided on the first plug in the first layer and electrically connected to the first plug. The device further includes a second metal layer including a first portion provided in the first layer and a second portion provided on the first layer and electrically connected to the first metal layer.

Abstract: A device is disclosed. The device includes a plurality of capacitors, a transistor connected to each of the plurality of capacitors, and a first dielectric layer and a second dielectric layer on respective adjacent sides of adjacent capacitors of the plurality of capacitors. The first dielectric layer and the second dielectric layer include a top portion and a bottom portion, the top portion of the first dielectric layer and the top portion of the second dielectric layer extend from respective directions and meet at a top portion of a space between the adjacent capacitors, the bottom portion of the first dielectric layer and the bottom portion of the second dielectric layer extend from respective directions and meet at a bottom portion of a space between the adjacent capacitors.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

Abstract: The present disclosure provides a semiconductor device with an anti-fuse and a metal-insulator-metal (MIM) capacitor connected to a redistribution layer (RDL) and a method for forming the semiconductor device. The semiconductor device includes a first conductive portion and a second conductive portion disposed over a semiconductor substrate. The semiconductor device also includes a passivation layer covering the first conductive portion and the second conductive portion. The first conductive portion, the second conductive portion and a portion of the passivation layer therebetween form an anti-fuse. The semiconductor device further includes a first metal-insulator-metal (MIM) capacitor and a first redistribution layer (RDL) disposed over the passivation layer. The first MIM capacitor and the first RDL are electrically connected to the first conductive portion, and a first metal layer of the first MIM capacitor is integrally formed with the first RDL.

Abstract: A semiconductor device includes a landing pad, a first insulating pattern in contact with a lower portion of a side surface of the landing pad, a pad oxide layer having a lateral portion disposed on a portion of an upper surface of the landing pad and a vertical portion in contact with an upper portion of the side surface of the landing pad, a second insulating pattern in contact with an upper surface of the first insulating pattern and covering the first insulating pattern and the pad oxide layer, and a lower electrode that vertically passes through the second insulating pattern and is in contact with a portion of the upper surface and an upper portion of a side surface of the landing pad.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

Abstract: Embodiments are disclosed for a method to process microelectronic workpieces including forming a metal hard mask layer including ruthenium (Ru MHM layer) over one or more underlying layers on a substrate for a microelectronic workpiece, etching the Ru MHM layer to provide a patterned Ru MHM layer, and etching the one or more underlying layers using the patterned Ru MHM layer as a mask to protect portion of the one or more underlying layers. For one embodiment, the Ru MHM layer is a material including 95 percent or more of ruthenium (Ru). For another embodiment, the Ru MHM layer is a material including 70 percent or more of ruthenium (Ru). Further, the Ru MHM layer preferably has a selectivity of 10 or greater with respect to a next underlying layer adjacent to the Ru MHM layer, such as a SiN hard mask layer.

Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.

Abstract: This application relates to capacitors that resist deformation because of the configuration of their conductive and dielectric layers. The capacitors are multilayer capacitors that include multiple dielectric and conductive layers. The dielectric layers can be arranged in a way that creates a rigid barrier or dead zone, which can resist mechanical deformation when the multilayer capacitor is charged. In some embodiments, two or more multilayer capacitors are stacked together in an arrangement that causes each of the multilayer capacitors to cancel any deformations of the other when the multilayer capacitors are charged. In this way, noise exhibited by the multilayer capacitors can be reduced.

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.

Abstract: A capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: A vertical metal-insulator-metal (MIM) capacitor is formed within multiple layers of a multi-level metal interconnect system of a chip. The vertical MIM capacitor has a first electrode, a second electrode, and a high-k capacitor dielectric material disposed therebetween. The dielectric constant of the capacitor dielectric material is greater than the dielectric constant of interlayer dielectric (ILD) material. After ILD is removed from between the vertically-oriented, interdigitated portions of the first and second electrodes, a capacitor dielectric material having a dielectric constant greater than the ILD dielectric material is disposed therebetween.

Abstract: Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.

Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A first capacitor plate is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. An insulator layer and a second capacitor plate are disposed on the first capacitor plate forming a MIM capacitor. A pair of capacitor plate contacts are electrically connected to the first capacitor plate and the second capacitor plate.

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

Abstract: Described are methods of making silicon nitride (SiN) materials on substrates. Improved SiN films made by the methods are also included. One aspect relates to depositing chlorine (Cl)-free conformal SiN films. In some embodiments, the SiN films are Cl-free and carbon (C)-free. Another aspect relates to methods of tuning the stress and/or wet etch rate of conformal SiN films. Another aspect relates to low-temperature methods of depositing high quality conformal SiN films. In some embodiments, the methods involve using trisilylamine (TSA) as a silicon-containing precursor.

Abstract: A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.

Abstract: The light output surface structure layer has a concavo-convex structure on a surface opposite to the organic EL element. The concavo-convex structure includes flat surface portions parallel to one surface of the organic EL element and an inclined surface portion tilted relative to the flat surface portions. The projected area which is formed by projecting the inclined surface portion in a direction perpendicular to the flat surface portions onto a plane parallel to the flat surface portions is equal to or less than 0.1 times the total area of the flat surface portions. On a cross section of a flat surface portion cut along a plane parallel to the width and thickness directions thereof, the ratio H/W is 1 or greater and 2.5 or less, where H and W are the height and the width thereof, respectively.

Abstract: A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form a double-sided capacitor. The support structure further supports the bottom plates during formation of a cell dielectric layer, a capacitor top plate, and final supporting dielectric. An inventive structure is also described.

Abstract: An integrated circuit having a place-efficient capacitor includes a lower capacitor electrode having a surface area comprised of an inner surface area of a partial opening and a via opening formed in a patterned dielectric layer on a semiconductor substrate, a capacitor insulating layer overlying the lower capacitor electrode, and an upper capacitor electrode including a metal fill material filling the partial opening and the via opening and having a surface area that includes the inner surface area of the partial opening and via opening.

Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

Abstract: A thin film deposition apparatus to remove static electricity generated between a substrate and a mask, and a method of manufacturing an organic light-emitting display device using the thin film deposition apparatus.

Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.

Abstract: Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

Abstract: A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the side to form the capacitor plate. The side from which the metal layer is removed is alternated with every metal layer that is deposited. When all the capacitor plates have been formed, the remaining opening in the layer of insulator material is filled with dielectric material then planarized, followed by the formation of contacts with the capacitor plates. There is also an MIM capacitor structure having interdigitated capacitor plates.

Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

Abstract: A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device.

Abstract: Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of: (1) coating a solution containing an organic semiconductor material on a water-repellent surface of a water-repellent stamp substrate; (2) drying the thus coated organic semiconductor material-containing solution on the water-repellent surface to crystallize the organic semiconductor material in contact with the water-repellent surface, thereby forming a semiconductor layer; (3) thermally treating the semiconductor layer formed on the stamp substrate; and (4) pressing the stamp substrate at a side, in which the thermally treated organic semiconductor layer is formed, against a surface of a substrate to be transferred so that the organic semiconductor layer is transferred to the surface of the substrate to be transferred.

Abstract: Method for encapsulating an electronic arrangement against permeates wherein a pressure-sensitive adhesive mass based on butylene block copolymers is applied to and around the areas of the electronic arrangement to be encapsulated.

Abstract: After forming a first capacitor hole, first mask material is filled in an upper portion of the first capacitor hole. A second capacitor hole is formed so that it is aligned with the first capacitor hole. After removing the first mask material, a lower electrode is formed in the first and second capacitor holes by one film formation step. After that, a capacitor dielectric film and an upper electrode are sequentially formed on the lower electrode.

Abstract: A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body includes a plurality of layer portions stacked. In a method of manufacturing the layered chip package, a plurality of structures are initially formed. Each structure includes at least one main-body-forming portion that is to be the main body and that has a pre-wiring surface. Next, the plurality of structures are surrounded with a jig and thereby aligned so that their pre-wiring surfaces face upward. The jig has a top surface that is lower in level than the pre-wiring surfaces. Next, a resin layer covering the jig and the structures is formed using a resin film. Next, the resin layer is polished until the pre-wiring surfaces are exposed. Next, the wiring is formed on the pre-wiring surfaces simultaneously. Next, the main-body-forming portions are separated from each other.

Abstract: An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of materials between the top and bottom surfaces are non-uniform and arranged to induce a variation in energy gap between the top and bottom surfaces. The variation in energy gap establishes an electric field between the top and bottom surfaces tending to oppose charge motion toward at least one of the top and bottom surfaces and prevent resultant charge leakage.

Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.