Abstract: A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper wiring, wherein the copper wiring includes an additive for improving adhesion between the copper wiring and the insulating layer, and a profile of the additive has a gradient in which a concentration is gradually reduced as it goes from the top surface of the copper wiring toward the inside thereof, and has the highest concentration on the top surface of the copper wiring.

Abstract: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory metal (300) is deposited over the capacitor region (200). Other aspects of the present invention include a metal-insulator-metal capacitor (900) and a method of manufacturing an integrated circuit (1000).

Abstract: In a method of forming a titanium aluminum nitride layer, a first reactant is formed on a substrate by reacting a first source including titanium and a second source including nitrogen. A second reactant is formed by providing a third source including aluminum onto the substrate having the first reactant thereon and reacting the third source with the first reactant. A third reactant is formed by providing a fourth source including nitrogen onto the substrate having the second reactant thereon and reacting the fourth source with the second reactant. The titanium aluminum nitride layer having a good step coverage is formed on the substrate. Processes of forming the titanium aluminum nitride layer are simplified and deposition rate is improved. Therefore, a phase-change memory device using the titanium aluminum nitride layer as a lower electrode may have an improved throughput.

Abstract: The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard mask material layer using a photosensitive mask; forming a capacitor electrode by etching the capacitor electrode material layer using the hard mask as an etching mask; and forming a top insulation layer on an entire surface of the semiconductor.

Abstract: A PLZT film (30) is formed as the material film of a capacitor dielectric film and a top electrode film (31) is formed on the PLZT film (30). The top electrode film (31) comprises two IrOx films having different composition. Subsequently, back face of a semiconductor substrate (11) is cleaned and an Ir adhesion film (32) is formed on the top electrode film (31). Substrate temperature is set at 400° C. or above at that time. Thereafter, a TiN film and a TEOS film are formed sequentially as a hard mask. In such a method, carbon remaining on the top electrode film (31) after cleaning the back face is discharged into the chamber while the temperature of the semiconductor substrate (11) is kept at 400° C. or above in order to form the Ir adhesion film (32). Consequently, adhesion is enhanced between a TiN film being formed subsequently and the Ir adhesion film (32) thus preventing the TiN film from being stripped.

Abstract: Electrostatic capacitors with high capacitance density and high-energy storage are implemented over conventional electrolytic capacitor anode substrates using highly conformal contact layers deposited by atomic layer deposition. Capacitor films that are suitable for energy storage, electrical and electronics circuits, and for integration onto PC boards endure long lifetime and high-temperature operation range.

Abstract: A method of manufacturing a semiconductor device includes: preparing a semiconductor element having a first metal layer made of first metal on a surface thereof, and a metal substrate made of second metal, the metal substrate having a fourth metal layer made of fourth metal on a surface thereof, and mounting the semiconductor element on the surface thereof; providing metal nanopaste between the first metal layer and the fourth metal layer, the metal nanopaste being formed by dispersing fine particles made of third metal with a mean diameter of 100 nm or less into an organic solvent; and heating, or heating and pressurizing the semiconductor element and the metal substrate between which the metal nanopaste is provided, thereby removing the solvent. Further, each of the first, third and fourth metals is made of any metal of gold, silver, platinum, copper, nickel, chromium, iron, lead, and cobalt, an alloy containing at least one of the metals, or a mixture of the metals or the alloys.

Abstract: A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process.

Abstract: A method of forming an electronic structure may include providing a substrate having a metal pad thereon. A conductive barrier layer may be formed on a first portion of the metal pad, and a second exposed portion of the metal pad may be free of the conductive barrier layer. In addition, an interconnection structure may be provided on the conductive barrier layer with the conductive barrier layer being between the interconnection structure and the metal pad. Moreover, the interconnection structure and the conductive barrier layer may include different materials. Related structures are also discussed.

Abstract: Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.

Abstract: A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls, depositing a metal barrier layer comprising the barrier metal on the first barrier layer, depositing a main conductor species seed layer on the metal barrier layer and depositing a main conductor layer. The method further includes annealing the main conductor layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light.

Abstract: Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques may be used to define the gate stack.

Abstract: A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a metal-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.

Abstract: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

Abstract: A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (22) over a gate dielectric layer (11), forming a transition layer (32) over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer (44) over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (52). By forming the transition layer (32) with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer (32) is constructed having a lower region (e.g., 31, 33) with a polycrystalline structure and an upper region (e.g., 37, 39) with an amorphous structure that blocks silicon diffusion.

Abstract: A method for fabricating an MIM capacitor is disclosed. First, a substrate is provided having a first dielectric layer thereon. Next at least one first damascene conductor is formed within the first dielectric layer, and a second dielectric layer with a capacitor opening is formed on the first dielectric layer, in which the capacitor opening is situated directly above the first damascene conductor. Next, an MIM capacitor having a top plate and a bottom plate is created within the capacitor opening, in which the bottom plate of the MIM capacitor is electrically connected to the first damascene conductor. Next, a third dielectric layer is deposited on the second dielectric layer and the MIM capacitor, and at least one second damascene conductor is formed within part of the third dielectric layer, in which the second damascene conductor is electrically connected to the top plate of the MIM capacitor.

Abstract: There is provided a semiconductor device that comprises a first impurity diffusion region formed on a silicon substrate (semiconductor substrate), a first interlayer insulating film (first insulating film) formed over the silicon substrate, a first hole formed in the first interlayer insulating film, a first conductive plug formed in the first hole and connected electrically to the first impurity diffusion region and having an end portion protruded from an upper surface of the first interlayer insulating film, a conductive oxygen barrier film formed to wrap the end portion of the first conductive plug, and a capacitor formed by laminating a capacitor lower electrode, a capacitor dielectric film, and a capacitor upper electrode sequentially on the conductive oxygen barrier film.

Abstract: A method and a deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors using CO gas and a dilution gas. The method includes providing a substrate in a process chamber of a processing system, forming a process gas containing a metal-carbonyl precursor vapor and a CO gas, diluting the process gas in the process chamber, and exposing the substrate to the diluted process gas to deposit a metal layer on the substrate by a thermal chemical vapor deposition process.

Abstract: A method of fabricating a Metal-Insulator-Metal (MIM) capacitor is presented. The method includes depositing a bottom plate of the MIM capacitor on a passivating dielectric layer which may be a pre-metal or post metal dielectric layer. A capacitor dielectric of the MIM capacitor is subsequently deposited on top of the bottom plate. The capacitor dielectric and the bottom plate both conform to the profile of the passivating dielectric layer. In addition, because the bottom plate is located on a dielectric, which is thermally stable and does not morph or change significantly with successive thermal processing, the capacitor dielectric does not have to be designed to compensate for topography changes due to such thermal processing.

Abstract: An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The method also includes forming the substrate structure over the patterned protective layer. An opening within the substrate structure overlies an exposed portion of the substrate structure. The method further includes removing the exposed portion of the patterned protective layer, thereby exposing a portion of the first electrode and forming an undercut region of the substrate structure. The method still further includes depositing a liquid over the first electrode after removing the exposed portion of the patterned protective layer, and solidifying the liquid to form a solid layer.

Abstract: A semiconductor bear chip having a bump subjected to high temperatures is pressed, from the upper side, onto a wiring board including a wiring pattern, a thermosetting resin film covering an electrode area on the wiring pattern and having insulating particles dispersed and included and a thermoplastic resin film covering the thermosetting resin film, while applying a ultrasonic wave, thereby inserting the bumps of the semiconductor bear chip through the thermoplastic resin film and the thermosetting resin film to bond the top end portion of the bump with the electrode area.

Abstract: Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching speed and current gain of bipolar transistors. Current fabrication techniques involve high temperature procedures that melt desirable low-resistance substitutes, such as aluminum, during fabrication. Accordingly, one embodiment of the invention provides an emitter contact structure that includes a polysilicon-carbide layer and a low-resistance aluminum, gold, or silver member to reduce emitter resistance. Moreover, to overcome manufacturing difficulties, the inventors employ a metal-substitution technique, which entails formation of a polysilicon emitter, and then substitution or cross-diffusion of metal for the polysilicon.

Abstract: The present invention provides a low dielectric constant copper diffusion barrier film composed, at least in part, of boron-doped silicon carbide suitable for use in a semiconductor device and methods for fabricating such a film. The copper diffusion barrier maintains a stable dielectric constant of less than 4.5 in the presence of atmospheric moisture.

Abstract: A metal-insulator-insulator (MIM) capacitor structure is provided. The MIM capacitor includes a top electrode, a bottom electrode and a dielectric layer. The dielectric layer is disposed between the top electrode and the bottom electrode. The main feature for this kind of MIM capacitor is that the bottom electrode includes a conductive layer and a metal nitride with multi-layered structure. The metal nitride with multi-layered structure is disposed between the conductive layer and the dielectric layer. The nitrogen content in the metal nitride with multi-layered structure gradually increases toward the dielectric layer and the metal nitride belongs to the amorphous type. Due to the presence of the metal nitride, the dielectric layer is prevented from crystallization, thereby reducing the current leakage of the MIM capacitor.

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.

Abstract: Semiconductor devices with copper interconnections and MIM capacitors and methods of fabricating the same are provided. The device includes a lower electrode composed of a first copper layer. A first insulation layer covers a lower electrode. A window is formed in the first insulation layer to expose a portion of the lower electrode. A capacitor includes a lower barrier electrode, a dielectric layer, and an upper barrier electrode, which are sequentially formed to cover a sidewall and a bottom of the window. An intermediate electrode composed of a second copper layer fills a remaining space of an inside of the capacitor. A second insulation layer is formed on the intermediate electrode. A connection hole is formed in the second insulation layer to expose a portion of the intermediate electrode. A connection contact plug composed of a third copper layer fills the connection hole.

Abstract: In accordance with the objectives of the invention a new method and structure is provided for the creation of a capacitor. A contact pad and a lower capacitor plate have been provided over a substrate. Under the first embodiment of the invention, a layer of etch stop material, serving as the capacitor dielectric is deposited after which a triple layer of passivation is created over a substrate. The compound passivation layer is first etched, using a fuse mask, to define and expose the capacitor dielectric and a fuse area after which the passivation layer is second etched to define and expose the contact pad. A layer of AlCu is then deposited, patterned and etched to create a capacitor upper plate and a contact interconnect over the contact pad. Under a second embodiment of the invention, a triple layer of passivation is created over a layer of etch stop material deposited over a substrate, a contact pad and a lower capacitor plate have been provided over the substrate.

Abstract: A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.