Abstract: A substrate processing apparatus includes a source gas supply system including a source gas supply pipe connected to a source gas source and a source gas supply controller; a reactive gas supply system including a reactive gas supply pipe connected to a reactive gas source, a reactive gas supply controller, a plasma generation unit and an ion trap unit and an inert gas supply pipe whereat an inert gas supply controller is disposed; a processing chamber supplied with a source gas by the source gas supply system and a reactive gas by the reactive gas supply system; and a control unit configured to control the gas supply controllers. The inert gas supply pipe has a downstream side connected between the reactive gas supply controller and the plasma generation unit and an upstream side connected to an inert gas supply source.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of second core films, the second core film having a first array portion, and a second array portion which is arranged so as to be spaced at a larger second space than the first space in the first direction from the first array portion, the second space being positioned above the loop portion. The method includes processing the second film to be processed below the first array portion into a second line and space pattern which includes a second line pattern extending in the second direction, and removing the second film to be processed below the second space and the loop portion of the first film to be processed, by an etching using the second spacer film as a mask.

Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

Abstract: An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer.

Abstract: A method for particle beam lithography, such as electron beam (EB) lithography, includes forming a plurality of cell patterns on a stencil mask and shaping one or more of the cell patterns with a polygonal-shaped contour. A first polygonal-shaped cell pattern is exposed to a particle beam so as to project the first polygonal-shaped cell pattern on a substrate. A second polygonal-shaped cell pattern, having a contour that mates with the contour of the first polygonal-shaped cell pattern, is exposed to the particle beam, such as an electron beam, so as to project the second polygonal-shaped cell pattern adjacent to the first polygonal-shaped cell pattern to thereby form a combined cell with the contour of the first polygonal-shaped cell pattern mated to the contour of the second polygonal-shaped cell pattern. The polygonal-shaped contour of the first and second cell patterns may comprise a rectilinear-shaped contour.

Abstract: An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

Abstract: A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring.

Abstract: An amorphous silicon (Si) film is taken to form a metal silicide of Si—Al(aluminum) under a high temperature. Al atoms is diffused into the amorphous Si film for forming the metal silicide of Si—Al as nucleus site. Then through heating and annealing, a microcrystalline or nano-crystalline silicon thin film is obtained. The whole process is only one process and is done in only one reacting chamber.

Abstract: Combined e-beam and optical exposure lithography for semiconductor fabrication is disclosed. E-beam direct writing to is employed to create critical dimension (CD) areas of a semiconductor design on a semiconductor wafer. Optical exposure lithography is employed to create non-CD areas of the semiconductor design on the semiconductor CD's of the semiconductor design can also be separated from non-CD's of the semiconductor design prior to employing e-beam direct writing and optical exposure lithography.

Abstract: A measurement substrate 100 in which a silicon oxide film 102, a polysilicon layer 103 and a titanium silicide layer 104 are formed over a silicon substrate 101 in this order is prepared. The measurement substrate 100 is irradiated with X-rays so that the proportions of three types of silicides with different compositions in the titanium silicide layer 104 are measured based on the intensity of hard X-rays emitted from oxygen in the silicon oxide film 102 and the intensity of hard X-rays emitted from titanium in the titanium silicide layer 104.