Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.

Abstract: A method for lithography patterning includes forming an opening in a first layer over a substrate and coating a grafting solution over the first layer and filling in the opening. The grafting solution comprises a grafting compound and a solvent. The grafting compound comprises a grafting unit chemically bonded to a linking unit chemically bonded to a polymer backbone. The grafting unit is attachable to the first layer. The method further includes curing the grafting solution so that a first portion of the grafting compound is attached to a surface of the first layer, thereby forming a second layer over the surface of the first layer. The method further includes transferring a pattern including the first layer and the second layer to the substrate.

Abstract: Methods for forming imprinted patterns using an imprint template. The imprint template may include at least an imprint portion and a photomask portion. The imprint portion may include imprinting patterns. The imprinting patterns may be transferred into a first imprint shot region of a resist layer. The photomask portion may include light blocking patterns. The light blocking patterns may provide a light permeation area corresponding to a boundary region defining a second imprint shot region of the resist layer.

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

Abstract: The present invention provides a planarization apparatus which planarizes a composition on a substrate by using a mold, the apparatus including a processing unit configured to, for each of a plurality of substrates, perform planarization processing for, by bringing a planar portion of the mold into contact with the composition on the substrate and making the planar portion conform to a surface shape of the substrate, planarizing the composition, and a driving unit configured to, whenever the planarization processing is performed a predetermined number of times, relatively drive the mold and a processing target substrate among the plurality of substrate so that a relative positional relationship between the processing target substrate and the planar portion changes.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes a step of forming an opening portion in a resist coated on a substrate, a step of coating a thermally-shrinking shrink agent on the resist to fill the opening portion with the shrink agent, a shrinking step of heating and thermally shrinking the shrink agent to reduce a width of the opening portion, a removing step of removing the shrink agent after the shrinking step, a step of forming a metal layer on the resist and in the opening portion after the removing step and a step of removing a portion of the metal layer above the resist and the resist, wherein in the shrinking step, a side surface of the resist forming the opening portion forms a curved surface protruding toward a center portion of the opening portion.

Abstract: Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

Abstract: Defluorination processes for removing fluorine residuals from a workpiece such as a semiconductor wafer are provided. In one example implementation, a method for processing a workpiece can include supporting a workpiece on a workpiece support. The workpiece can have a photoresist layer. The workpiece can have one or more fluorine residuals on a surface of the workpiece. The method can include performing a defluorination process on the workpiece at least in part using a plasma generated from a first process gas. The first process gas can include a hydrogen gas. Subsequent to performing the defluorination process, the method can include performing a plasma strip process on the workpiece to at least partially remove a photoresist layer from the workpiece.

Abstract: Methods for forming imprinted patterns using an imprint template. The imprint template may include at least an imprint portion and a photomask portion. The imprint portion may Include imprinting patterns. The imprinting patterns may be transferred into a first imprint shot region of a resist layer. The photomask portion may include light blocking patterns. The light blocking patterns may provide a light permeation area corresponding to a boundary region defining a second imprint shot region of the resist layer.

Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.

Abstract: A micro-LED (3r) transfer method and a manufacturing method are disclosed. The micro-LED (3r) transfer method comprises: forming a sacrificial post (4) on a micro-LED (3r) to be picked-up on a carrier substrate (1); bonding the micro-LED (3r) to be picked-up with a pickup substrate (5) via the sacrificial post (4); lifting-off the micro-LED (3r) to be picked-up from the carrier substrate (1); bonding the micro-LED (3r) on the pickup substrate (5) with a receiving substrate (12); and lifting-off the micro-LED (3r) from the pickup substrate (5). A complicated pickup head is not necessary, and the technical solution is relatively simple.

Abstract: A method for masking a surface, in particular a surface having silicon oxide, aluminum or silicon, includes providing a substrate having a surface to be masked, in particular having a surface having silicon oxide, aluminum or silicon; and producing a defined masking pattern by locally selective forming of colloidal silicon oxide on the surface. The method allows for the creating of an extremely stable masking in a simple and cost-effective manner, in contrast to a plurality of etching media, in particular in contrast to hydrofluoric acid, in order to thus create extremely accurate and defined structures such as by an etching process.

Abstract: A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles.

Abstract: In a method of forming a pattern, a lower coating layer and a photoresist layer are sequentially formed on an object layer. An exposure process may be performed such that the photoresist layer is divided into an exposed portion and a non-exposed portion. A portion of the lower coating layer overlapping or contacting the exposed portion is at least partially transformed into a polarity conversion portion that has a polarity substantially identical to that of the exposed portion. The non-exposed portion of the photoresist layer is selectively removed.

Abstract: A method of monitoring critical dimensions of gate electrode structures is provided including providing a substrate, forming a gate electrode pattern on the substrate comprising forming gate electrode lines parallel to each other, forming a mask layer on the gate electrode pattern and forming openings in the mask layer in a crosswise direction with respect to the direction of the parallel gate electrode lines, thereby exposing portions of the gate electrode pattern, etching exposed portions of the gate electrode pattern through the mask layer openings, thereby obtaining a negative image of the mask layer openings, removing remaining portions of the mask layer, and monitoring dimensions of the mask layer openings.

Abstract: Provided is a configuration capable of suppressing a variation in characteristics of transistor. The configuration includes: a process chamber; a gas supply unit configured to supply a hard mask forming gas into the process chamber; a substrate support table configured to support a substrate Wn of an nth lot having a film to be etched formed thereon; a heater embedded in the substrate support table; and a controller configured to control a temperature distribution of the heater based on an etching information of a substrate Wm of an mth lot processed prior to the nth lot.

Abstract: A pattern formation method according to the present embodiment includes forming a resist film on a treatment target material. The resist film is processed into resist patterns. A cross-link film or a coating agent protecting the resist film is coated onto the resist film. A self-organizing material is applied onto the resist film having the cross-link film or the coating agent coated thereon. The self-organizing material is thermally treated to achieve phase separation. A part of the self-organizing material which has been phase-separated is removed.

Abstract: A fine pattern structure includes a layer having or including alternating protrusion portions and recess portions, polymer patterns disposed in recess regions formed by the recess portions, brush patterns disposed on top surfaces of the protrusion portions, and a block co-polymer layer including first polymer block patterns formed on the brush patterns and second polymer block patterns formed on the polymer patterns.

Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A positive-tone development process is performed to remove the first exposure region from the positive photoresist layer to form first opening(s). The second exposure region in the negative photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A negative-tone development process is performed to remove portions of the negative photoresist layer outside of remaining second exposure region to form a double patterned negative photoresist layer.

Abstract: An array substrate for an IPS mode LCD device comprises a substrate; a gate line along a first direction; a data line along a second direction; a TFT connected to the gate and data lines; a common electrode having a plate shape on the substrate and formed of a first transparent conductive material; and a pixel electrode formed of a second transparent conductive material on the common electrode and including first and second portions and a plurality of third portions combining the first portion with the second portion. The first and second portions are parallel to the second direction and separated from each other and the plurality of third portions are oblique to the first and second portions and separated from one another.

Abstract: An apparatus includes a substrate; and a photoactive layer disposed on the substrate. The photoactive layer includes an electron acceptor material; an electron donor material; and a material having dipoles.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.

Abstract: A method of manufacturing a thin film transistor array substrate includes forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming first, second, and third passivation films successively on the substrate. Over the above multi-layered passivation film forming a first photoresist pattern including a first portion formed on part of the drain electrode and on the pixel region, and a second portion. The second portion is thicker than the first portion. Then, patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern, and forming a transparent electrode pattern on the second passivation layer.

Abstract: It is disclosed an over-coating agent for forming fine patterns which is applied to cover a substrate having photoresist patterns thereon and allowed to shrink under heat so that the spacing between adjacent photoresist patterns is lessened, with the applied film of the over-coating agent being removed to form fine patterns, further characterized by comprising a water-soluble polymer which contains a monomeric component and a dimeric component, wherein the total content of the monomeric component and the dimeric component in the water-soluble polymer is reduced to 10 mass % or less, and a method of forming fine patterns using the same. By the present invention, even in reducing the pattern size on a substrate having thereon patterns having different pitches, the heat shrinkage of the over-coating agent can be controlled, irrespective whether the pitch is dense or isolate, thus achieving the pattern size reduction.

Abstract: The present invention provides a pattern formation method capable of preventing formation of surface defects. In the method, a resist surface after subjected to exposure is coated with an acidic film and then subjected to heating treatment. This method is suitably adopted in a process employing liquid immersion lithography and/or light of short wavelength, such as ArF excimer laser beams, for producing a very fine pattern.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: An organic light emitting diode (OLED) device includes a substrate, an anode, a cathode, an active region including an organic material, wherein the active region is electrically coupled to the anode and the cathode, at least one coupler configured to electrically couple at least one of the anode or the cathode to a power supply, and an encapsulation that isolates the active region from an ambient environment. A lighting system can be made including a plurality of OLED devices. A lighting system can be assembled using the OLED devices from a kit. The OLED devices may be polymer light emitting diode (PLED) devices or small molecule light emitting diode (SMOLED) devices. The OLED devices can use regio-regular poly-thiophene.

Abstract: A method for manufacturing a solid-state imaging device, in which a photoelectric conversion portion to receive light with a light-receiving surface and generate a signal charge is disposed in a substrate, includes the steps of forming a metal light-shield layer above the substrate and in a region other than a region corresponding to the light-receiving surface, forming a light-reflection layer above the metal light-shield layer, and forming a photoresist pattern layer from a negative type photoresist film formed above the light-reflection layer, by conducting an exposing treatment and a developing treatment, wherein in the forming of the light-reflection layer, the light-reflection layer includes a shape corresponding to a pattern shape of the photoresist pattern layer, and the light-reflection layer is formed in such a way as to reflect exposure light to the photoresist film in conduction of the exposing treatment in the forming of the photoresist pattern layer.

Abstract: A method of fabricating a semiconductor device includes forming core material patterns comprising first films separated from another above a substrate; modifying surfaces of core material patterns so a second film is formed, selectively etchable, with first films internally remaining, the second film not covering a base layer of core material patterns between core material patterns; covering an upper surface and sides of the second film and forming a third film on the substrate; etching back the third film to expose an upper surface of the second film and the base layer of core material patterns between the patterns, causing the third film to selectively remain; removing the second film more rapidly than the first and third films; and patterning the base layer with the first and third films remaining on the base layer serving as a mask after the second film has been removed, forming a base layer pattern.

Abstract: A method for etching features in an etch layer. A conditioning for a patterned pseudo-hardmask of amorphous carbon or polysilicon disposed over the etch layer is provided, where the conditioning comprises providing a fluorine free deposition gas comprising a hydrocarbon gas, forming a plasma from the fluorine free deposition gas, providing a bias less than 500 volts, and forming a deposition on top of the patterned pseudo-hardmask. The etch layer is etched through the patterned pseudo-hardmask.

Abstract: A method for fabricating a fine pattern includes forming a first photomask including first light transmission regions set in a line shape over a first phase shift mask (PSM) region and a first binary mask (BM) region adjacent to the first phase shift mask region. A second photomask may be formed to include second light transmission regions set in a line shape over a second phase shift mask region and a second binary mask region adjacent to the second phase shift mask region, wherein the second light transmission regions intersect the first light transmission regions. A resist layer may first be exposed using the first photomask and secondly exposed using the second photomask. The first and secondly exposed resist layer may be developed to form resist patterns with open regions corresponding to portions where the first light transmission regions intersect the second light transmission regions.

Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device capable of simplifying a silicide manufacturing process using a photo resist overhang structure. According to embodiments, a surface is subjected to a monochlorobenzene coating processing to cure the surface of the exposed photo resist so as not to react with developing solution and such a processed photo resist is developed to make the lower of the photo resist in the overhang structure so as to form an accurate pattern according to the clear removal of the oxide film, making it possible to simply manufacture the silicide and the non-silicide without performing an etching process by a subsequent cobalt deposition process.

Abstract: An image sensor and a method of fabricating an image sensor. A method of fabricating an image sensor may include forming a plurality of photodiodes on and/or over a semiconductor substrate, a filter array including color filters arranged corresponding to upper parts of photodiodes, a plurality of hydrophilic lenses arranged over a filter array spaced apart from one another, and/or a plurality of hydrophobic lenses arranged over a filter array between hydrophilic lenses. A curvature of a lens may be substantially equal in a horizontal, vertical and/or diagonal direction.

Abstract: A pattern forming method includes (a) forming pairs of deposits on sidewalls of mask portions in first mask patterns by forming a thin film thereon, etching it to leave deposits, and exposing a top surface of a second-layer film between the deposits; (b) forming second mask patterns formed of mask portions corresponding to the deposits by removing the mask portion, plasma etching the second-layer film, and removing the deposits; (c) forming a thin film thereon, and etching it to leave deposits on sidewalls of mask portions facing each other and to expose a third-layer film between the deposits while leaving deposits between adjacent mask portions; and (d) forming grooves thereon by removing the second mask portion, and etching off the third-layer film.

Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

Abstract: An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.

Abstract: A substrate treatment apparatus which uniformly forms a fine resist pattern with a desired dimension within a plane of a substrate is disclosed. In a solvent vapor supply unit, a solvent vapor discharge nozzle is provided which can discharge a solvent vapor for swelling a resist pattern while moving above the front surface of a wafer. The wafer for which developing treatment has been finished and on which a resist pattern has been formed is carried into the solvent vapor supply unit, and the solvent vapor discharge nozzle is moved above the front surface of the wafer, so that the solvent vapor discharge nozzle supplies the solvent vapor onto the front surface of the wafer. This uniformly supplies a predetermined amount of solvent vapor to the resist pattern on the front surface of the wafer. As a result, the solvent vapor causes the resist pattern to evenly swell by a predetermined dimension, so that a resist pattern with a desired dimension is finally uniformly formed within the plane of the wafer.

Abstract: A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer made of a photosensitive organic material are deposited thereon after forming data lines and drain electrodes. The upper insulating layer is patterned to form an unevenness pattern on its surface and contact holes on the drain electrodes. The lower insulating layer is patterned together with the gate insulating layer using a photoresist pattern having apertures located in the contact holes to form other contact holes respectively exposing the drain electrodes, portions of the gate lines, and portions of the data lines.

Abstract: In a stripping composition for easily removing a photoresist without an adverse effect and a method of manufacturing a TFT substrate for an LCD device using the same, the stripping composition includes acetic acid and ozone gas contained in the acetic acid as a bubble form to remove the photoresist including novolak. A photoresist pattern including novolak is formed on a predetermined layer (24) formed on a substrate (10). The layer is etched using the photoresist pattern as a mask to form a pattern of the layer. The photoresist pattern is removed using the stripping composition. The stripping composition is cheap and more effectively protects the environment in comparison with the conventional stripping compositions. Additionally, an O2 ashing process performed before or after a stripping process may be omitted to thereby simplify a stripping process.

Abstract: A method for forming a transistor gate includes performing a first exposure of a photo-resist material on a semiconductor device. The first exposure defines a line pattern in the photo-resist material. The method also includes performing a second exposure of the photo-resist material, where the second exposure trims a resist profile of the line pattern. The method further includes etching a conductive material on the semiconductor device to form a transistor gate based on the line pattern. The first exposure could represent a best focus exposure of the photo-resist material, and the second exposure could represent a positive focus exposure of the photo-resist material. The trimming of the line pattern's resist profile may cause the transistor gate to have at least one of a rounded edge and a rounded corner. This may allow a thicker insulating material, such as tetraethylorthosilicate, to be deposited around portions of the transistor gate.

Abstract: A method for forming a fine-pitch pattern on a semiconductor substrate is provided. The method includes patterning the semiconductor substrate to form a plurality of fine lines, forming a thermal oxide layer on the fine lines, polishing the thermal oxide layer to expose a top surface of the fine lines; etching the fine lines using the thermal oxide layer as a mask to expose first portions of the semiconductor substrate, etching a central bottom portion of the thermal oxide layer to expose second portions of the semiconductor substrate, and etching the semiconductor substrate using the etched thermal oxide layer as a mask.

Abstract: A method for fabricating a nonvolatile memory device includes repeatedly stacking a stacked structure over a substrate to form a multi-stacked structure, wherein the stacked structure includes a conductive layer and an insulation layer, forming a photoresist pattern over the multi-stacked structure, first-etching an uppermost stacked structure of the multi-stacked structure using the photoresist pattern as an etch barrier, second-etching a resultant structure formed by the first-etching through the use of a breakthrough etching, slimming the photoresist pattern to form a slimmed photoresist pattern, and third-etching the uppermost stacked structure using the slimmed photoresist pattern as an etch barrier and, at the same time, etching a stacked structure disposed under the uppermost stacked structure and exposed by the first-etching.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: Disclosed is a substrate processing method that dissolves and deforms a photoresist film having a first pattern formed on a substrate to reshape the resist film into a second pattern During the reflow process, an atmosphere of a thinner vapor-containing gas is established in a processing chamber. A substrate is placed on a temperature adjusting plate. The target temperature of the temperature adjusting plate is set and controlled by a control unit, and the temperature of the temperature adjusting plate is controlled by a temperature regulator based on the target temperature set by the control unit The control unit set and controls the target temperature so that it meets the following requirement: the atmospheric temperature?the target temperature?(the atmospheric temperature+2° C.). Due to the above, the reflowing of the resist can be performed stably, while achieving a satisfactory reflow rate although it is somewhat low.

Abstract: The present invention provides a method of forming interconnects in a photovoltaic module. According to one aspect, a method according to the invention includes processing steps that are similar to those performed in conventional integrated circuit fabrication. For example, the method can include masks and etches to form isolation grooves between cells, and additional etches to form a conductive step adjacent to the grooves that can be used to form interconnects between cells. According to another aspect the method for forming the conductive step can be self-aligned, such as by positioning a mirror above the module and exposing photoresist from underneath the substrate at an angle one or more times, and etching to expose the conductive step. According to another aspect, the process can include steps to form grid lines in the module to improve current transport in the structure.

Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.