Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.

Abstract: A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Abstract: The method of manufacturing a semiconductor device comprising: forming a first hard mask layer and a second hard mask layer on the layer to be etched (S11); a first groove-forming mask pattern forming process for forming a groove-forming mask pattern which has a first pitch, is formed of the second hard mask layer, and is used as an etching mask when forming groove patterns(S12-S14); and a first concave portion-forming mask pattern forming process for etching the first hard mask layer using the second resist pattern as an etching mask, wherein the second resist pattern is formed of the second resist layer having an opening portion that has a fourth pitch and the first organic layer having an opening portion that is connected to an opening portion of the second resist layer and has a smaller size than the opening portion of the second resist layer (S15-S18).

Abstract: A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surfaces extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Abstract: An inventive leadframe includes an outer frame, a die pad, and a plurality of leads each having land portions and connections. The land portions each have an upper surface serving as a bonding pad to be connected with a metal wiring, and a lowermost part serving as an external terminal. The connections are each devoid of its lower part so as to be thinner than the land portion, and are provided between the outer frame and the land portions, between the land portions associated with each other in each lead, and between the land portions and the die pad. Furthermore, the inventive leadframe is provided with no member that functions as a suspension lead for connecting the outer frame and the die pad to each other during plastic encapsulation.