Characterized By Their Composition, E.g., Multilayer Masks, Materials (epo) Patents (Class 257/E21.035)
  • Patent number: 7381654
    Abstract: A method is disclosed for forming right-angle contact/via holes for semiconductor devices. A device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided over the first layer. A first photoresist pattern is provided over the second layer to define an X or Y dimension of the contact/via hole. A second photoresist pattern is provided over the second layer to define an opposite dimension of the contact/via hole. First and second pattern dimensions are measured prior to etching to ensure appropriate dimensioning of the etched cavity. A second dry etch is then performed to form the contact/via hole. If the photoresist pattern is not within a desired tolerance, the etching process may be adjusted to ensure the cavity will have the desired dimensions.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: June 3, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventor: Cheng-Yao Lo
  • Patent number: 7378738
    Abstract: A method for forming a self-aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferential develop in a fashion that is replicates the existing pattern of the substrate. The existing pattern may be comprised of a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. Structures made in accordance with the method.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: May 27, 2008
    Assignee: International Business Machines Corporation
    Inventors: Timothy A. Brunner, Matthew E. Colburn, Elbert Huang, Muthumanickam Sankarapandian
  • Patent number: 7368390
    Abstract: A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: May 6, 2008
    Assignee: Infineon Technologies AG
    Inventors: Guenther Czech, Carsten Fuelber, Markus Kirchhoff, Maik Stegemann, Mirko Vogt, Stephan Wege
  • Patent number: 7364925
    Abstract: A method of forming a protective barrier in an organic light emitting device is disclosed, wherein the organic light emitting device is formed on a substrate and includes a plurality of layers of materials, the plurality of layers of materials including an organic light emitting layer. The method includes forming an inorganic layer and a semi-crystalline parylene-based polymer layer over an underlying layer, wherein the semi-crystalline parylene-based polymer layer is formed via transport polymerization of a reactive intermediate species. Organic light emitting devices having barriers are also disclosed.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: April 29, 2008
    Assignee: International Display Systems, Inc.
    Inventors: Chung J. Lee, Chieh Chen, Atul Kumar
  • Patent number: 7309659
    Abstract: The disclosure provides methods to mitigate and/or eliminate problems associated with removal of carbon-based resists from organic low k dielectrics. The methods include forming an organic low k dielectric layer over a semiconductor substrate, forming a capping layer over the organic low k dielectric layer, forming a silicon-containing resist over the capping layer, patterning the silicon-containing resist layer to expose portions of the capping layer and to form a patterned silicon oxide layer, removing the organic low k dielectric layer to form one or more openings, and removing the patterned silicon oxide layer. The silicon-containing resist facilitates efficient patterning of the organic low k-dielectric layers, and thereby increases the performance and cost-effectiveness of semiconductor devices fabricated using organic low k dielectrics.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: December 18, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Calvin T. Gabriel, Bhanwar Singh
  • Publication number: 20070141848
    Abstract: A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as for example a high-ohmic poly resistor. The method transfers a pattern defined by a mask onto the screening layer by selectively removing portions of the screening layer in accordance with the pattern. Portions of the auxiliary layer that are not protected by the screening layer are removed using a plasma gas selective to the auxiliary layer material, without removing the area of the auxiliary layer that overlays the portion of the circuit component, thereby protecting the circuit component from the plasma gas via the screening layer and auxiliary layer.
    Type: Application
    Filed: December 21, 2005
    Publication date: June 21, 2007
    Applicant: STMicroelectronics, Inc.
    Inventors: Olivier Le Neel, Olivier Girard, Fabio Ferrari
  • Publication number: 20070138526
    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.
    Type: Application
    Filed: January 31, 2007
    Publication date: June 21, 2007
    Applicant: Micron Technology, Inc.
    Inventors: Luan Tran, William Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer Abatchev, Gurtej Sandhu, D. Durcan
  • Patent number: 7138338
    Abstract: A method and structure for forming deep trenches in a semiconductor substrate is provided. The method comprises: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a pad nitride layer on the pad oxide layer; forming a borophosphosilicate glass layer on the pad nitride layer; forming a borosilicate glass layer on the borophosphosilicate glass layer; and forming deep trenches through the borosilicate glass layer, through the borophosphosilicate glass layer, through the pad nitride, through the pad oxide, and into the semiconductor substrate. The borosilicate glass layer and the borophosphosilicate glass layer function as a composite hard mask in forming the deep trenches. With the borophosphosilicate glass layer, the composite hard mask can be easily removed by dry etch process using hydrogen fluoride vapor after the deep trenches have been formed.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: November 21, 2006
    Assignee: NANYA Technology Corporation
    Inventors: Chang-Rong Wu, Yinan Chen, Tuz-Ching Tsai
  • Patent number: 7138341
    Abstract: An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a first lateral width, and a second lateral width different than the first lateral width, forming a second hard mask layer having substantially the first and second lateral widths in the opening, and etching the first hard mask layer using at least one of the lateral widths of the second hard mask layer.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: November 21, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Manish Sharma