Diode (epo) Patents (Class 257/E21.053)
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Patent number: 10910443Abstract: An organic electroluminescence display device includes a first electrode, a first light emitter on the first electrode, the first light emitter including a first light emitting layer, a first charge generation layer disposed on the first light emitter, a second light emitter on the first charge generation layer, the second light emitter including a second light emitting layer, and a second electrode on the second light emitter. The first light emitter includes a first electron injection enhancing layer on the first light emitting layer. The second light emitter includes an electron injection suppressing layer on the second light emitting layer, the electron injection suppressing layer having electron mobility less than that of the first electron injection enhancing layer.Type: GrantFiled: July 6, 2017Date of Patent: February 2, 2021Assignee: Samsung Display Co., Ltd.Inventors: Ilsoo Oh, Pyungeun Jeon, Myungsuk Han
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Patent number: 10186568Abstract: An organic light emitting display device includes a thin film transistor (TFT) including a gate electrode and a source electrode. An anode electrode is disposed on the TFT, and a cathode electrode disposed on an organic emission layer is connected to an auxiliary electrode which is disposed on a same layer on which the anode electrode is disposed. A signal pad disposed in a pad area of a substrate is disposed on a same layer on which the gate electrode is disposed in an active area of the substrate. A pad electrode disposed on the signal pad is connected to the signal pad through a contact hole.Type: GrantFiled: December 30, 2015Date of Patent: January 22, 2019Assignee: LG DISPLAY CO., LTD.Inventors: SeJune Kim, Joonsuk Lee, SoJung Lee, Jin-Hee Jang, Jonghyeok Im, JaeSung Lee
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Patent number: 9035311Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.Type: GrantFiled: March 15, 2013Date of Patent: May 19, 2015Assignee: Samsung Display Co., Ltd.Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
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Patent number: 9029921Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.Type: GrantFiled: January 17, 2014Date of Patent: May 12, 2015Assignee: STMicroelectronics International N.V.Inventors: Alexei Ankoudinov, Vladimir Rodov
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Patent number: 8999770Abstract: A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board.Type: GrantFiled: July 24, 2013Date of Patent: April 7, 2015Assignee: TSMC Solid State Lighting Ltd.Inventors: Tien-Ming Lin, Chih-Hsuan Sun, Wei-Yu Yeh
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Patent number: 8993361Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions.Type: GrantFiled: August 28, 2013Date of Patent: March 31, 2015Assignee: Hamamatsu Photonics K.K.Inventors: Hiroshi Oguri, Yoshitaka Ishikawa, Akira Sakamoto, Tomoya Taguchi, Yoshimaro Fujii
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Patent number: 8987753Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.Type: GrantFiled: July 1, 2013Date of Patent: March 24, 2015Assignee: LG Innotek Co., Ltd.Inventor: Hyo Kun Son
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Patent number: 8969134Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.Type: GrantFiled: May 10, 2013Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: Xavier F. Brun, Takashi Kumamoto, Sufi Ahmed
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Patent number: 8969143Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.Type: GrantFiled: August 7, 2013Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Daniel Kim, Jae-sung You, Jong-kil Park
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Patent number: 8969892Abstract: Disclosed is a light emitting structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer disposed on between the first and second semiconductor layers, a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer. The first semiconductor layer is formed, at an edge portion thereof, with a hole, in which a portion of the first electrode is arranged.Type: GrantFiled: October 11, 2011Date of Patent: March 3, 2015Assignee: LG Innotek Co., Ltd.Inventors: WooSik Lim, SungKyoon Kim, MinGyu Na, SungHo Choo, MyeongSoo Kim, HeeYoung Beom
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Patent number: 8963197Abstract: An LED package includes a package body having a well formed in its upper surface, where the well is configured to receive a light emitting chip. An optical lens is disposed above the package body and includes a hollow dome structure located above and encompassing the lateral extent of the light emitting chip within the well of the package body. In one implementation, the package body and the optical lens collectively include at least one protrusion and concave, where the protrusion is aligned with the concave so that the optical lens mates with the package body, thereby causing the optical lens to self align with the package body. In another implementation, a protruding inner portion of the upper surface of the package body mates with the hollow dome structure, achieving a similar purpose. Consequently, generation of an eccentric fault between the optical lens and the package body is prevented.Type: GrantFiled: December 16, 2013Date of Patent: February 24, 2015Assignee: LG Display Co., Ltd.Inventors: Myung Soo Han, Seung Ho Jang, Won Seok Choi
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Patent number: 8952512Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.Type: GrantFiled: April 19, 2013Date of Patent: February 10, 2015Assignee: China Wafer Level CSP Ltd.Inventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
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Patent number: 8945979Abstract: An organic layer deposition apparatus, a method of manufacturing an organic light-emitting display apparatus by using the same, and an organic light-emitting display apparatus manufactured by the method, and more particularly, an organic layer deposition apparatus that is suitable for use in the mass production of a large substrate, that enables high-definition patterning, and that is capable of controlling a distance between a patterning slit sheet and a substrate that moves, a method of manufacturing an organic light-emitting display apparatus by using the organic layer deposition apparatus, and an organic light-emitting display apparatus manufactured by the method.Type: GrantFiled: March 12, 2013Date of Patent: February 3, 2015Assignee: Samsung Display Co., Ltd.Inventor: Yun-Ho Chang
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Patent number: 8946784Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.Type: GrantFiled: February 18, 2013Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung, Pao-Tung Chen, Jen-Cheng Liu
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Patent number: 8927348Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.Type: GrantFiled: May 12, 2009Date of Patent: January 6, 2015Assignee: Toyoda Gosei Co., Ltd.Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
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Patent number: 8928052Abstract: An optoelectronic semiconductor chip has a semiconductor layer sequence having an active layer that generates radiation between a layer of a first conductivity type and a layer of a second conductivity type. The layer of the first conductivity type is adjacent to a front side of the semiconductor layer sequence. The semiconductor layer sequence contains at least one cutout extending from a rear side, lying opposite the front side, of the semiconductor layer sequence through the active layer to the layer of the first conductivity type. The layer of the first conductivity type is electrically connected through the cutout by means of a first electrical connection layer which covers the rear side of the semiconductor layer sequence at least in places.Type: GrantFiled: March 13, 2009Date of Patent: January 6, 2015Assignee: OSRAM Opto Semiconductors GmbHInventors: Karl Engl, Lutz Hoeppel, Patrick Rode, Matthias Sabathil
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Patent number: 8907375Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.Type: GrantFiled: March 29, 2013Date of Patent: December 9, 2014Assignee: Sony CorporationInventor: Masashi Yanagita
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Patent number: 8906752Abstract: Ink compositions comprising polythiophenes and methicone that are formulated for inkjet printing the hole injecting layer (HIL) of an organic light emitting diode (OLED) are provided. Also provided are methods of inkjet printing the HILs using the ink compositions.Type: GrantFiled: December 4, 2013Date of Patent: December 9, 2014Assignee: Kateeva, Inc.Inventors: Inna Tregub, Rajsapan Jain, Michelle Chan
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Patent number: 8900912Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.Type: GrantFiled: June 26, 2013Date of Patent: December 2, 2014Assignee: OmniVision Technologies, Inc.Inventors: Gang Chen, Ashish Shah, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
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Patent number: 8896338Abstract: A method for characterizing the electronic properties of a semiconductor sample by exploiting transients in measured photoconductance, the transients being induced by illuminating the semiconductor sample with a small probing illumination that is superimposed over a larger background illumination. In one embodiment, a pulse-type probing illumination is utilized, with either the intensity of the probing illumination being gradually reduced or the intensity of the background illumination being gradually increased until the measured photoconductance rise and decay in the sample are substantially exponential. In another embodiment, a continuous probing illumination with a sinusoidally-modulated intensity is utilized, the modulated intensity of the probing illumination being gradually adjusted until the measured photoconductance is linearly dependent thereupon.Type: GrantFiled: June 14, 2012Date of Patent: November 25, 2014Inventor: Emil Kamieniecki
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Patent number: 8896037Abstract: A solid-state imaging device including: a semiconductor layer; a charge accumulation region configured to be formed inside the semiconductor layer and serve as part of a photodiode; and a reflective surface configured to be disposed inside or under the charge accumulation region and be so formed as to reflect light that has passed through the charge accumulation region and direct the light toward a center part of the charge accumulation region.Type: GrantFiled: October 14, 2011Date of Patent: November 25, 2014Assignee: Sony CorporationInventors: Harumi Ikeda, Masashi Nakazawa
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Patent number: 8890186Abstract: A molded resin product or the like that is provided with a phosphor layer made of gel-like or rubber-like resin that can maintain its shape for a long period and that can be implemented easily. The molded resin product (phosphor layer 7) includes a resin member 17 made of a gel-like or rubber-like translucent resin including a phosphor material. The resin member 17 includes a shape maintaining member 19 that is formed in a lattice shape by line-like members 20 that are made of a material having a higher elasticity modulus than the resin member 17. The molded resin product (phosphor layer 7) is in the shape of a dome. The translucent resin is made of, for example, silicon resin, and the resin member 17 is gel-like.Type: GrantFiled: March 17, 2009Date of Patent: November 18, 2014Assignee: Panasonic CorporationInventors: Toshifumi Ogata, Nobuyuki Matsui, Masumi Abe
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Patent number: 8872194Abstract: An illumination device is disclosed. The illumination device includes a light source a pre-dip material that at least partially encapsulates the light source. The pre-dip material may include one or both of thermally-conductive particles and a cyclo-aliphatic composition. The pre-dip material may further include a resin and a hardener for the resin. Methods of manufacturing an illumination device are also disclosed.Type: GrantFiled: March 8, 2013Date of Patent: October 28, 2014Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Kum Soon Wong, Yean Chon Yaw, Kit Lai Wong
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Patent number: 8871574Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.Type: GrantFiled: August 5, 2013Date of Patent: October 28, 2014Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8871556Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.Type: GrantFiled: December 17, 2013Date of Patent: October 28, 2014Assignee: Kyma Technologies, Inc.Inventors: Edward Preble, Lianghong Liu, Andrew D. Hanser, N. Mark Williams, Xueping Xu
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Patent number: 8871548Abstract: A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate.Type: GrantFiled: February 19, 2013Date of Patent: October 28, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Jengping Lu, Raj B. Apte
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Patent number: 8872180Abstract: A production method for a liquid crystal display device having a plurality of thin film transistors (TFTs) including reflection sections disposed to correspond to a plurality of pixels includes: a step of forming on a substrate a metal layer having apertures; a step of forming a semiconductor layer on the metal layer; a step of forming a protection layer on the semiconductor layer; a step of forming a resist layer on the protection layer; a photolithography step of irradiating the resist layer with light through the metal layer to pattern the protection layer by photolithography technique; and a step of stacking a reflective layer on the patterned protection layer. A plurality of bumps are formed from the protection layer in the photolithography step, and a plurality of bumps corresponding to the plurality of bumps of the protection layer are formed on the reflective layer.Type: GrantFiled: March 24, 2009Date of Patent: October 28, 2014Assignee: Sharp Kabushiki KaishaInventor: Katsunori Misaki
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Patent number: 8847367Abstract: Provided are a hole-injecting material for an organic electroluminescent device (organic EL device) exhibiting high luminous efficiency at a low voltage and having greatly improved driving stability, and an organic EL device using the material. The hole-injecting material for an organic EL device is selected from benzenehexacarboxylic acid anhydrides, benzenehexacarboxylic acid imides, or N-substituted benzenehexacarboxylic acid imides. Further, the organic EL device has at least one light-emitting layer and at least one hole-injecting layer between an anode and a cathode arranged opposite to each other, and includes the above-mentioned hole-injecting material for an organic EL device in the hole-injecting layer. The organic EL device may contain a hole-transporting material having an ionization potential (IP) of 6.0 eV or less in the hole-injecting layer or a layer adjacent to the hole-injecting layer.Type: GrantFiled: February 27, 2009Date of Patent: September 30, 2014Assignee: Nippon Steel & Sumikin Chemical Co., Ltd.Inventors: Takayuki Fukumatsu, Ikumi Ichihashi, Hiroshi Miyazaki, Atsushi Oda
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Patent number: 8816404Abstract: A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.Type: GrantFiled: September 16, 2011Date of Patent: August 26, 2014Assignee: STATS ChipPAC, Ltd.Inventors: YoungJoon Kim, SangMi Park, YongHyuk Jeong
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Patent number: 8809981Abstract: A method for manufacturing a semiconductor device includes: irradiating a growth substrate with laser light to focus the laser light into a prescribed position inside a crystal for a semiconductor device or inside the growth substrate, the crystal for the semiconductor device being formed on a first major surface of the growth substrate; moving the laser light in a direction parallel to the first major surface; and peeling off a thin layer including the crystal for the semiconductor device from the growth substrate, a wavelength of the laser light being longer than an absorption end wavelength of the crystal for the semiconductor device or the growth substrate, the laser light being irradiated inside a crystal for the semiconductor device or inside the growth substrate.Type: GrantFiled: December 20, 2011Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masanobu Ando, Toru Gotoda, Toru Kita
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Patent number: 8810765Abstract: An electroluminescence element includes an electroluminescence substrate including a thin film transistor substrate, and a light-emitting layer provided over the thin film transistor substrate and divided by picture-element separating portions so as to correspond to unit picture elements; and a sealing substrate arranged to hermetically seal the light-emitting layer of the electroluminescence substrate. At least one of the electroluminescence substrate and the sealing substrate is a flexible substrate. Spacers are provided between the electroluminescence substrate and the sealing substrate.Type: GrantFiled: January 11, 2008Date of Patent: August 19, 2014Assignee: Sharp Kabushiki KaishaInventors: Tohru Okabe, Hirohiko Nishiki
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Patent number: 8785326Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.Type: GrantFiled: May 29, 2012Date of Patent: July 22, 2014Assignee: Micron Technology, Inc.Inventors: Martin F. Schubert, Ming Zhang, Lifang Xu
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Patent number: 8772074Abstract: Provided are an organic light emitting display device and a method for manufacturing the same. The organic light emitting display device comprises a transistor on a substrate, a cathode on the transistor and connected to a source or a drain of the transistor, a bank layer on the cathode and having an opening, a metal buffer layer on the cathode, an organic light emitting layer on the metal buffer layer, and an anode on the organic light emitting layer.Type: GrantFiled: August 12, 2009Date of Patent: July 8, 2014Assignee: LG Display Co., Ltd.Inventors: Jaehee Park, Heeseok Yang, Howon Choi
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Patent number: 8772826Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer is comprised of a plurality of stacked semiconductor layers containing a chalcopyrite-based compound semiconductor. The semiconductor layers contain oxygen. A molar concentration of the oxygen in surfaces and their vicinities of the semiconductor layers where the semiconductor layers are stacked on each other is higher than average molar concentrations of the oxygen in the semiconductor layers.Type: GrantFiled: May 30, 2011Date of Patent: July 8, 2014Assignee: KYOCERA CorporationInventors: Hideaki Asao, Rui Kamada, Shuichi Kasai, Seiji Oguri, Isamu Tanaka, Nobuyuki Horiuchi, Kazumasa Umesato
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Patent number: 8765584Abstract: A semiconductor device and a manufacturing method therefor, wherein, during lift-off, no cracks due to internal stresses occur in the compound semiconductor layer. A method for manufacturing a semiconductor device having a structure in which a semiconductor layer is bonded on a supporting substrate, including: a device region formation step of forming a device region including the semiconductor layer on a growth substrate through a lift-off layer; a columnar member formation step of forming a columnar member on the growth substrate; a bonding step of bonding the tops of the semiconductor layer and the columnar member to a supporting substrate; a lift-off step of separating the bottom face of the semiconductor layer from the growth substrate by removing the lift-off layer, and not separating the columnar member from the growth substrate; and a step of separating the columnar member from the supporting substrate.Type: GrantFiled: July 26, 2011Date of Patent: July 1, 2014Assignee: Dowa Electronics Materials Co., Ltd.Inventors: Yoshitaka Kadowaki, Tatsunori Toyota
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Patent number: 8759164Abstract: In a method for manufacturing an integral imaging device, a layer of curable adhesive is first applied on a flexible substrate and half cured such that the curable adhesive is solidified but is capable of deforming under external forces. Then the curable adhesive is printed into a lenticular lens having a predetermined shape and size using a roll-to-roll processing device and fully cured such that the curable adhesive is capable of withstanding external forces to hold the predetermined shape and size. Last, a light emitting diode display is applied on the flexible substrate opposite to the lenticular lens such that an image plane of the light emitting diode display coincides with a focal plane of the lenticular lens.Type: GrantFiled: June 20, 2012Date of Patent: June 24, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Chia-Ling Hsu
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Patent number: 8753946Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.Type: GrantFiled: February 4, 2012Date of Patent: June 17, 2014Assignees: NthDegree Technologies Worldwide Inc, NASA, an agency of the United StatesInventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8753947Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.Type: GrantFiled: February 4, 2012Date of Patent: June 17, 2014Assignees: NthDegree Technologies Worldwide Inc, NASAInventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 8748205Abstract: A MEMS structure incorporating multiple joined substrates and a method for forming the MEMS structure are disclosed. An exemplary MEMS structure includes a first substrate having a bottom surface and a second substrate having a top surface substantially parallel to the bottom surface of the first substrate. The bottom surface of the first substrate is connected to the top surface of the second substrate by an anchor, such that the anchor does not extend through either the bottom surface of the first substrate or the top surface of the second substrate. The MEMS structure may include a bonding layer in contact with the bottom surface of the first substrate, and shaped to at least partially envelop the anchor.Type: GrantFiled: November 30, 2012Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chih Liang, Jiou-Kang Lee, Chung-Hsien Lin, Te-Hao Lee, Chia-Hua Chu
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Patent number: 8748938Abstract: There is provided a solid-state imaging device in which a plurality of pixels is two-dimensionally arranged in a pixel region. Each of the pixels is formed in an island-shaped semiconductor. In this island-shaped semiconductor, a signal line N+ region and a P region are formed from the bottom. On an upper side surface of this P region, an N region and a P+ region are formed from an inner side of the island-shaped semiconductor. Above the P region, a P+ region is formed. By setting the P+ region and the P+ region to have a low-level voltage and setting the signal line N+ region to have a high-level voltage that is higher than the low-level voltage, signal charges accumulated in the N region are discharged to the signal line N+ region via the P region.Type: GrantFiled: February 18, 2013Date of Patent: June 10, 2014Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 8741702Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.Type: GrantFiled: October 20, 2009Date of Patent: June 3, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunichi Ito, Miyuki Hosoba, Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
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Patent number: 8716766Abstract: Graphene semiconductor device, a method of manufacturing a graphene semiconductor device, an organic light emitting display and a memory, include forming a multilayered member including a sacrificial substrate, a sacrificial layer, and a semiconductor layer deposited in sequence, forming a transfer substrate on the semiconductor layer, forming a first laminate including the transfer substrate and the semiconductor layer by removing the sacrificial layer to separate the sacrificial substrate from the semiconductor layer, forming a second laminate by forming a graphene layer on a base substrate, combining the first laminate and the second laminate such that the semiconductor layer contacts the graphene layer, and removing the transfer substrate.Type: GrantFiled: June 14, 2012Date of Patent: May 6, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-seung Lee, Young Bae Kim, Young Jun Yun, Yong Sung Kim, David Seo, Joo-ho Lee
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Patent number: 8686515Abstract: A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.Type: GrantFiled: December 21, 2011Date of Patent: April 1, 2014Assignee: STMicroelectronics (Tours) SASInventors: Yannick Hague, Samuel Menard
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Patent number: 8679884Abstract: A method for manufacturing a semiconductor apparatus includes the first step of forming a silicon oxide film including a main portion on a second portion and a sub portion between a first portion and a silicon nitride film, the second step of forming a first conductivity type impurity region under the silicon oxide film, and the third step of forming a semiconductor element including a second conductivity type impurity region having an opposite conductivity to the first conductivity type impurity region in the first portion. In the second step, angled ion implantation is performed into a region under the sub portion at an implantation angle using the silicon nitride film as a mask.Type: GrantFiled: April 25, 2012Date of Patent: March 25, 2014Assignee: Canon Kabushiki KaishaInventor: Yasuhiro Kawabata
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Patent number: 8669130Abstract: A fringe field switching (FFS) liquid crystal display (LCD) device which uses an organic insulating layer and consumes less power, in which film quality of an upper layer of a low temperature protective film is changed to improve undercut within a pad portion contact hole, and a method for fabricating the same is provided.Type: GrantFiled: November 2, 2012Date of Patent: March 11, 2014Assignee: LG Display Co., Ltd.Inventors: KyoungJin Nam, SeungRyull Park, KyungMo Son, JiHye Lee
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Patent number: 8664691Abstract: A silicon photomultiplier maintains the photon detection efficiency high while increasing a dynamic range, by reducing the degradation of an effective fill factor that follows the increase of cell number density intended for a dynamic range enhancement.Type: GrantFiled: December 19, 2011Date of Patent: March 4, 2014Assignee: Electronics and Telecommunications Research InstituteInventor: Joon Sung Lee
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Patent number: 8633521Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.Type: GrantFiled: January 6, 2010Date of Patent: January 21, 2014Assignee: STMicroelectronics N.V.Inventors: Alexei Ankoudinov, Vladimir Rodov
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Patent number: 8629467Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.Type: GrantFiled: June 26, 2012Date of Patent: January 14, 2014Assignee: Renesas Electronics CorporationInventors: Takamitsu Kanazawa, Toshiyuki Hata
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Patent number: 8604482Abstract: A microelectronic device includes a plurality of disconnected similar semiconducting portions, electrically isolated from each other and forming a semiconductor layer, at a spacing by a constant distance and with a shape parallel to the other portions. The microelectronic device also includes two electrodes arranged in contact with the semiconductor layer such that a maximum distance separating the two electrodes is less than the largest dimension of one of the semiconductor portions. The shape and dimensions of the semiconductor portions, the spacing between the semiconductor portions, the shape and dimensions of the electrodes and the layout of the electrodes relative to the semiconductor portions are such that at least one of the semiconductor portions electrically connects the two electrodes to each other. The largest dimensions of the semiconductor portions are perpendicular to the largest dimension of the electrodes, the electrodes being similar.Type: GrantFiled: May 3, 2011Date of Patent: December 10, 2013Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Romain Gwoziecki, Romain Coppard
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Patent number: 8587041Abstract: According to one embodiment, a solid-state imaging device includes an imaging region including unit pixels which are two-dimensionally arranged on a semiconductor layer and each of which includes a photoelectric conversion unit and a signal scanning circuit unit. The unit pixel includes a transfer gate provided on the semiconductor layer, a photogate provided on the semiconductor layer, a first semiconductor layer of a first conductivity type, which is provided in the semiconductor layer below the photogate, and a second semiconductor layer of the first conductivity type, which is adjacent to the first semiconductor layer and provided in the semiconductor layer between the transfer gate and the photogate.Type: GrantFiled: September 18, 2011Date of Patent: November 19, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ai Mochizuki, Takeshi Yoshida