Abstract: A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum mold. By depositing the patterned and full-surface layers in a single process, a photosensitive array with an integrated transistor backplane may be fabricated, resulting in improved sensitivity and performance.

Abstract: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.

Abstract: A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.

Abstract: Provided is a phase-change memory device including a phase-change material pattern of which strips are shared by neighboring cells. The phase-change memory device includes a plurality of bottom electrodes arranged in a matrix array. The phase-change material pattern is formed on the bottom electrodes, and the strips of the phase-change material pattern are electrically connected to the bottom electrodes. Each strip of the phase-change material pattern is connected to at least two diagonally neighboring bottom electrodes of the bottom electrodes.

Abstract: Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers.

Abstract: A method for fabrication of a semiconductor device, the semiconductor device having a plurality of epitaxial layers on a substrate. The plurality of epitaxial layers include an active region in which light is able to be generated. The method comprises applying at least one first ohmic contact layer to a front surface of the epitaxial layer, the first ohmic contact layer also acting as a reflector. The substrate is then remove from a rear surface of the epitaxial layers. The rear surface is then textured.

Abstract: An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding and light-transparent material. The light-transparent material, such as a dielectric, is selected to have a stress, such as a tensile stress, that offsets the stress, such as a compressive stress, of the light shielding material. Without the stress offset, the high compressive stress of the refractory metal could damage the integrity of the nearby silicon. The refractory metal is capable of withstanding the high temperatures associated with front end CMOS processing. The laminate structure allows the light shield to be placed close to the pixel surface. The light-transparent material has a thickness equal to about one-quarter wavelength of the light to be blocked, to act as an anti-reflective coating. An aperture in the light shield exposes the active region of the pixel's photoconversion device.

Abstract: A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped AlXGa1-XN (0?X<1); a second nitride-based semiconductor layer made of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor layer; a first electrode formed on the second nitride-based semiconductor layer; a second electrode formed on the second nitride-based semiconductor layer; and an insulating film that covers the second nitride-based semiconductor layer below a peripheral portion of the first electrode. In the diode, a recess structure portion is formed at a position near the peripheral portion of the first electrode on the second nitride-based semiconductor layer, and the first electrode covers the second nitride-based semiconductor layer and at least a part of the insulating film.

Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.

Abstract: A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.

Abstract: The present invention is to provide a semiconductor laser with a feedback grating comprised of InP and AlGaInAs without InAsP put therebetween, and to provide a method for manufacturing the DFB-LD having such grating. The LD includes an n-type InP substrate, an AlInAsP intermediate layer, an AlGaInAs lower SCH layer, an active layer, and a p-type layer for upper cladding in this order from the InP substrate. The InP substrate, the AlInAsP intermediate layer, and the AlGaInAs lower SCH layer constitute the feedback grating. The AlInAsP intermediate layer lowers a series resistance along these semiconductor stacks.

Abstract: A method for manufacturing a semiconductor optical device includes: forming a p-type cladding layer; forming a capping layer on the p-type cladding layer, the capping layer being selectively etchable relative to the p-type cladding layer; forming a through film on the capping layer; forming a window structure by ion implantation; removing the through film after the ion implantation; and selectively removing the capping layer using a chemical solution.

Abstract: An efficient long-wavelength light-emitting diode has a resonant-cavity design. The light-emitting diode preferably has self-organized (In,Ga)As or (In,Ga)(As,N) quantum dots in the light-emitting active region, deposited on a GaAs substrate. The light-emitting diode is capable of emitting in a long-wavelength spectral range of preferably 1.15-1.35 ?m. The light-emitting diode also has a high efficiency of preferably at least 6 mW and more preferably at least 8 mW at an operating current of less than 100 mA and a low operating voltage of preferably less than 3V. In addition, the light-emitting diode preferably has an intensity of maxima, other than the main maximum of the emission spectrum, of less than 1% of an intensity of the main maximum. This combination of parameters makes such a device useful as an inexpensive optical source for various applications.

Abstract: An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whether an ion implantation process has been performed on the polysilicon layers, a different module is selected. A correlation process is performed according to the selected module to generate a theoretical curve that correlates with the real curve to obtain a plurality of parameters corresponding to the theoretical curve.

Abstract: An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached face down to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires is attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.

Abstract: A method of manufacturing semiconductor wafers is provided that comprises processing a semiconductor wafer to form at least one temperature-sensing RF device on the wafer and further processing the wafer to form a plurality of semiconductor products on the wafer while sensing temperature on the wafer with the formed RF device and wirelessly transmitting data from the RF device. Semiconductor wafers made according to the method are provided having at least one active RFID temperature-sensing device and semiconductor device products formed thereon. The RFID devices are located on portions of the wafer that are disposable when the semiconductor device products are cut from the wafers. A semiconductor wafer processing apparatus is provided having an RF antenna and transmitter and receiver circuits that communicate with RF devices on a wafer during processing.

Abstract: A method of growing nitride semiconductor material and particularly a method of growing Indium nitride is disclosed can increase surface flatness of a nitride semiconductor material and decrease density of V-defects therein. Further, the method can increase light emission efficiency of a quantum well or quantum dots of the produced LED as well as greatly increase yield. The method is also applicable to the fabrications of electronic devices made of nitride semiconductor material and diodes of high breakdown voltage for rectification. The method can greatly increase surface flatness of semiconductor material for HBT, thereby increasing quality of the produced semiconductor devices.

Abstract: A semiconductor chip (1), to which a layer sequence (2) intended for the production of a soldered connection has been applied. The layer sequence (2) comprises a solder layer (15) and an oxidation prevention layer (17), which follows the solder layer (15) as seen from the semiconductor chip (1). A barrier layer (16) is included between the solder layer (15) and the oxidation prevention layer (17). This prevents a constituent of the solder layer (15) from diffusing through the oxidation prevention layer (17) prior to the soldering operation, where it would effect oxidation that is disadvantageous for producing a soldered connection.

Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.

Abstract: A method of manufacturing an LED of high reflectivity includes forming a substrate; depositing an n-type GaN layer on the substrate; depositing an active layer on a first portion of the n-type GaN layer; attaching an n-type metal electrode to a second portion of the n-type GaN layer; depositing a p-type GaN layer on the active layer; forming a metal reflector on the p-type GaN layer; attaching a p-type metal electrode to the metal reflector; and attaching the p-type metal electrode and the n-type metal electrode to an epitaxial layer respectively. The metal reflector includes a transparent layer, an Ag layer, and an Au layer. The transparent layer and the Ag layer are formed by annealing in a furnace, and the Au layer is subsequently coated on the Ag layer.

Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.

Abstract: The invention provides an organic electroluminescent device and a method of manufacturing the same which conveniently reduce or suppress the transfer of ionic impurities into a light-emitting layer, and reduce or prevent the light-emitting property in the light-emitting layer from degrading, which promotes life extension. An organic electroluminescent device includes a functional layer having at least a light-emitting layer between a first electrode and a second electrode. At least a part of the functional layer is formed of the inorganic ion exchange material added to the functional material to form the functional layer.

Abstract: A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to form the gate structure of the FET, is utilized to form an isolation structure between the Schottky barrier and backside structure of the Schottky diode. Silicide (e.g., cobalt silicide (CoSi2)) structures, which are utilized to form source and drain metal-to-silicon contacts in the FET, are used to form the Schottky barrier and backside Ohmic contact of the Schottky diode. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.

Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides an alternative to expensive SiC wafers for growing semiconductor crystals.

Abstract: A gallium nitride-based compound semiconductor light-emitting device which includes an n-type semiconductor layer of a gallium nitride-based compound semiconductor, a light-emitting layer of a gallium nitride-based compound semiconductor and a p-type semiconductor layer of a gallium nitride-based compound semiconductor formed on a substrate in this order, and has a negative electrode and a positive electrode provided on the n-type semiconductor layer and the p-type semiconductor layer, respectively; wherein the negative electrode includes a bonding pad layer and a contact metal layer which is in contact with the n-type semiconductor layer, and the contact metal layer is composed of Cr or a Cr alloy and formed through sputtering.

Abstract: A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped AlXGa1-XN (0?X<1); a second nitride-based semiconductor layer made of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor layer; a first electrode formed on the second nitride-based semiconductor layer; a second electrode formed on the second nitride-based semiconductor layer; and an insulating film that covers the second nitride-based semiconductor layer below a peripheral portion of the first electrode. In the diode, a recess structure portion is formed at a position near the peripheral portion of the first electrode on the second nitride-based semiconductor layer, and the first electrode covers the second nitride-based semiconductor layer and at least a part of the insulating film.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Abstract: Regio-regular polythiophenes used in diodes which are not light emitting or photovoltaic. High quality, processable thin film polymer films can be made. The thin film can have a thickness of about 50 nm to about one micron, and the conductive thin film can be applied by spin casting, drop casting, screening, ink-jetting, transfer or roll coating. The polythiophenes can be homopolymers or copolymers. The regio-regular poly(3-substitutedthiophene) can be derivatized so that the 3-substituent is an alkyl, aryl, or alkyl/aryl moiety with a heteroatom substitution in either the ?- or beta-position of the 3-substituent.

Abstract: The present invention related to a method of manufacturing an LED, including the steps of: first, forming a tape coppery metal strip; then, continuously pressing circuits on the tape coppery metal strip so as to form a carrier having circuit patterns of electric contacts on which the diode dies can be placed; next, electroplating a plurality of metal layers on the surface of the carrier; then, performing continuous injection molding on the carrier so as to form a protector having a designated shape; and curing and fixing the diode die on the carrier to connect to the terminal contact of the carrier via metal wire. A conductive or non-conductive adhesive is dropped onto the bonding position between the metal wire and the terminal of the carrier, and a soft paste is Anther applied to cover the diode die, the metal wire and the terminal.

Abstract: Disclosed is a method of manufacturing a photoreceiver, including sequentially laminating a buffer layer, a channel layer, a barrier layer, and a cap layer on a substrate; forming a mesa for HEMT and MSM PD by removing the buffer layer, the channel layer, the barrier layer, and the cap layer with the exception of a region corresponding to HEMT and MSM PD; forming a source electrode and a drain electrode of HEMT; removing the cap layer from a region corresponding to a gate electrode of HEMT and a Schottky electrode of MSM PD; forming the gate electrode of HEMT and the Schottky electrode of HEMT on the cap layer-removed region; and removing the cap layer, the barrier layer and the channel layer from a region corresponding to an optical waveguide, to expose the optical waveguide.

Abstract: A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method includes the following steps: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas, and top electrode areas; etching to remove the exposed silicon (Si) surfaces; selectively forming metal sidewalls adjacent the hard mask; filling the memory areas with memory resistor material; removing the hard mask, exposing the underlying Si active device areas; forming an overlying layer of oxide; etching the oxide to form contact holes to the active device areas; forming diodes in the contact holes; and, forming bottom electrode lines overlying the diodes.

Abstract: A method of implanting, for example, a phosphorous plug over a charge collection region and a method of forming a contact over the phosphorous plug implant and charge collection region. The method allows implantation of phosphorous or other materials without contamination of other contact regions. The method further allows implantation of a material with only one step and without an extra masking step.

Abstract: A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.