Ohmic Electrode (epo) Patents (Class 257/E21.062)
  • Patent number: 10012859
    Abstract: A display device including: a substrate including first, second, and third pixel areas; a plurality of pixel electrodes positioned on the substrate within each of the first, second, and third pixel areas; and a plurality of roof layers each facing a respective one of the pixel electrodes, ones of the roof layers positioned to be spaced apart from respective ones of the pixel electrodes with a plurality of microcavities therebetween, the microcavities positioned to correspond to each of the first, second, and third pixel areas. The roof layer includes first and second color filter layers positioned corresponding to the first pixel area and the second pixel area and a third color filter layer positioned below the liquid crystal layer, and a cell gap of the microcavity corresponding to the third pixel area is smaller than cell gaps of the microcavities corresponding to the first and second pixel areas.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: July 3, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang Il Park, Won Tae Kim, Ji Yeon Choi, Seok-Joon Hong
  • Patent number: 9892919
    Abstract: A first nickel film is deposited inside a contact hole of an interlayer dielectric formed on an n+-type SiC substrate. Irradiation with a first laser is carried out, forming an Ohmic contact with a silicon carbide semiconductor. A second nickel film and a front surface electrode film are deposited on the first nickel film, forming a source electrode. The back surface of the n+-type SiC substrate is ground, and a third nickel film is formed on the ground back surface of the n+-type SiC substrate. Irradiation with a second laser is carried out, forming an Ohmic contact with the silicon carbide semiconductor. A fourth nickel film and a back surface electrode film are deposited on the third nickel film, forming a drain electrode. By so doing, it is possible to prevent electrical characteristic deterioration of a semiconductor device, and to prevent warping and cracking of a wafer.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Tachioka, Naoto Fujishima, Masaaki Ogino, Tsunehiro Nakajima, Kenichi Iguchi
  • Patent number: 9040402
    Abstract: A first metal layer (3) is formed on a back face of a silicon carbide substrate (1) to a degree such that the first metal layer (3) does not fully cover the back face of the silicon carbide substrate. Many holes (4) are formed on the back face of the silicon carbide substrate (1) by dry-etching the back face of the silicon carbide substrate (1) using the first metal layer (3) as a mask therefor. A second metal layer constituting an ohmic contact is formed on the first metal layer (3) and the back face of the silicon carbide substrate (1) including inner surfaces of the many holes (4).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 26, 2015
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masahide Goto, Kenji Fukuda, Noriyuki Iwamuro
  • Patent number: 9012284
    Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine
  • Patent number: 8963167
    Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 24, 2015
    Assignee: Neokismet, LLC
    Inventors: Jawahar M. Gidwani, Anthony C. Zuppero
  • Patent number: 8912659
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyeong Seok Choi
  • Patent number: 8853068
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
  • Patent number: 8841217
    Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive element on a sidewall of the opening and extending over an upper surface of the dielectric material.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 23, 2014
    Assignee: Life Technologies Corporation
    Inventors: Keith Fife, James Bustillo, Jordan Owens
  • Patent number: 8765555
    Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Damon E. Van Gerpen
  • Patent number: 8728923
    Abstract: A manufacturing method of a semiconductor device having an ohmic electrode is disclosed. The manufacturing method includes: forming a metal thin film on a rear surface of a semiconductor substrate; forming an ohmic electrode by laser annealing by irradiating the metal thin film with laser beam; and dicing the semiconductor substrate into chips by cutting at a dicing region of the semiconductor substrate. In forming the ohmic electrode, laser irradiation of the metal thin film is performed on a chip-by-chip basis while the dicing region is not being irradiated with the laser beam.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 20, 2014
    Assignee: DENSO CORPORATION
    Inventors: Jun Kawai, Tetsuji Kondou, Kazuhiko Sugiura, Nobuyuki Kato
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8637339
    Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 28, 2014
    Assignee: Neokismet L.L.C.
    Inventors: Anthony C. Zuppero, Jawahar M. Gidwani
  • Patent number: 8623752
    Abstract: An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: January 7, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Hideto Tamaso
  • Patent number: 8518729
    Abstract: A method includes forming a black photoresist layer on a substrate to form a black matrix; forming an isolation layer on the black matrix; forming first and second metal layers sequentially on the isolation layer to form source terminal/drain terminal and storage capacitor Com electrode; forming an ohmic contact layer on the second metal layer; forming a channel layer on the ohmic contact layer to form an island; forming a gate insulation layer on the channel layer and forming a third metal layer on the gate insulation layer to form a gate terminal and a storage capacitor counter electrode; forming a protection layer on the third metal layer; forming pixels on the protection layer; forming vias in the pixels; forming a transparent conductive layer on the pixels to form pixel electrode, thereby forming a COA substrate; and bonding the COA substrate to an upper substrate and filling liquid crystal therebetween.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 27, 2013
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Chao Dai
  • Patent number: 8329556
    Abstract: A process for the fabrication of semiconductor devices on a substrate, the semiconductor devices including at least one metal layer. The process includes, removing the substrate and applying a second substrate; and annealing the at least one metal layer by application of a beam of electromagnetic radiation on the at least one metal layer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: December 11, 2012
    Assignee: Tinggi Technologies Private Limited
    Inventors: Shu Yuan, Jing Lin
  • Patent number: 8324704
    Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: December 4, 2012
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Hirokazu Fujiwara, Masaki Konishi, Takashi Katsuno, Yukihiko Watanabe
  • Patent number: 8288279
    Abstract: A method for fabricating a conductive contact is provided, including: providing a semiconductor substrate with a gate structure and a pair of first conductive regions in a first region, and a pair of second conductive regions and an isolation element in the second region, and a first dielectric layer and a second dielectric layer thereon; forming a third dielectric layer and a fourth dielectric layer over the semiconductor substrate in the first region; forming a pattern mask layer with a first opening over the second dielectric layer in the second region; performing an etching process to the third and fourth dielectric layers in the first region and a portion of the first and second dielectric layers in the second region exposed by the first opening; removing the patterned mask layer; forming a first conductive semiconductor layer over the first conductive regions and a second conductive semiconductor layer over the isolation element and portions of the top surface of the second conductive regions; forming a
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 16, 2012
    Assignee: Nanya Technology Corporation
    Inventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8216929
    Abstract: In a method of manufacturing a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and having first and second opposing surfaces is prepared. The second surface of the semiconductor substrate is processed so that a surface roughness of the second surface is less than or equal to 10 nm and a value of (100%-reflectance-transmittance) at a wavelength of a laser light is greater than or equal to 80%. A metal layer is formed on the second surface of the semiconductor substrate after the processing the second surface. The metal layer is irradiated with the laser light and thereby an ohmic electrode is formed on the second surface.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: July 10, 2012
    Assignee: DENSO CORPORATION
    Inventors: Jun Kawai, Kazuhiro Tsuruta
  • Publication number: 20110284876
    Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
    Type: Application
    Filed: August 8, 2011
    Publication date: November 24, 2011
    Applicant: ROHM CO. LTD.
    Inventors: Yuji Okamura, Masashi Matsushita
  • Patent number: 7935628
    Abstract: A low on-resistance silicon carbide semiconductor device is provided to include an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide. Specifically, the silicon carbide semiconductor device includes at least an insulating film, formed on an upper surface of a silicon carbide substrate, and includes at least an ohmic electrode, formed of an alloy comprising nickel and titanium, or formed of a silicide comprising nickel and titanium, and which is formed on the lower surface of the silicon carbide substrate.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: May 3, 2011
    Assignee: National Institute for Advanced Industrial Science and Technology
    Inventors: Shinsuke Harada, Makoto Katou, Kenji Fukuda, Tsutomu Yatsuo
  • Publication number: 20110092063
    Abstract: In a method of manufacturing a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and having first and second opposing surfaces is prepared. The second surface of the semiconductor substrate is processed so that a surface roughness of the second surface is less than or equal to 10 nm and a value of (100%-reflectance-transmittance) at a wavelength of a laser light is greater than or equal to 80%. A metal layer is formed on the second surface of the semiconductor substrate after the processing the second surface. The metal layer is irradiated with the laser light and thereby an ohmic electrode is formed on the second surface.
    Type: Application
    Filed: September 9, 2010
    Publication date: April 21, 2011
    Applicant: DENSO CORPORATION
    Inventors: Jun Kawai, Kazuhiro Tsuruta
  • Patent number: 7875545
    Abstract: A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: January 25, 2011
    Assignee: Cree, Inc.
    Inventors: Allan Ward, III, Jason Patrick Henning, Helmut Hagleitner, Keith Dennis Wieber
  • Patent number: 7858507
    Abstract: A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum mold. By depositing the patterned and full-surface layers in a single process, a photosensitive array with an integrated transistor backplane may be fabricated, resulting in improved sensitivity and performance.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: December 28, 2010
    Assignee: The Regents of the University of Michigan
    Inventor: Stephen R. Forrest
  • Patent number: 7829374
    Abstract: A semiconductor device according to the present invention includes a silicon carbide semiconductor substrate having a silicon carbide semiconductor layer; a p-type impurity region provided in the silicon carbide semiconductor layer and including a p-type impurity; a p-type ohmic electrode electrically connected to the p-type impurity region; an n-type impurity region provided in the silicon carbide semiconductor layer adjacent to the p-type impurity region, and including an n-type impurity; and an n-type ohmic electrode electrically connected to the n-type impurity region. The p-type ohmic electrode contains an alloy of nickel, aluminum, silicon and carbon, and the n-type ohmic electrode contains an alloy of titanium, silicon and carbon.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Masashi Hayashi, Kazuya Utsunomiya, Osamu Kusumoto
  • Patent number: 7811874
    Abstract: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: October 12, 2010
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Shinsuke Harada, Makoto Katou, Kenji Fukuda, Tsutomu Yatsuo
  • Publication number: 20100244049
    Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 30, 2010
    Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Hirokazu Fujiwara, Masaki Konishi, Takashi Katsuno, Yukihiko Watanabe
  • Publication number: 20100244048
    Abstract: A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (1) including a silicon carbide layer (2); a high-concentration impurity region (4) provided in the silicon carbide layer (2); an ohmic electrode (9) electrically connected with the high-concentration impurity region (4); a channel region electrically connected with the high-concentration impurity region; a gate insulating layer (14) provided on the channel region; and a gate electrode (7) provided on the gate insulating layer (14). The ohmic electrode (9) contains an alloy of titanium, silicon and carbon, and the gate electrode (7) contains titanium silicide.
    Type: Application
    Filed: February 12, 2008
    Publication date: September 30, 2010
    Inventors: Masashi Hayashi, Shin Hasimoto
  • Patent number: 7723798
    Abstract: FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Eduard Albert Cartier, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri
  • Patent number: 7659628
    Abstract: Contact structures and methods for forming such contact structures are disclosed. An example contact structure includes a layer of semiconductor material having an interface and an electrical contact at the interface of the layer of semiconductor material, where the electrical contact includes a granular metal. An example method for forming a contact structure includes providing a substrate and producing a granular metal on at least part of the substrate, where the granular metal includes a cluster of metal islands extending essentially in a two-dimensional plane. The method further includes depositing a layer of a semiconductor material on top of the substrate and the cluster of metal islands.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: February 9, 2010
    Assignee: IMEC
    Inventors: Vladimir Arkhipov, Paul Heremans
  • Publication number: 20090230405
    Abstract: A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic contact; forming a mask having an opening on the first metallic film; etching a part of the first metallic film and a part of the P type semiconductor film via the opening so that a part of the N type semiconductor layer is exposed; and forming a second metallic film on the part of the N type semiconductor layer so that the second metallic film contacts the N type semiconductor layer with a Schottky contact.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 17, 2009
    Applicant: DENSO CORPORATION
    Inventors: Takeo Yamamoto, Takeshi Endo, Masaki Konishi, Hirokazu Fujiwara, Yukihiko Watanabe, Takashi Katsuno, Masayasu Ishiko
  • Patent number: 7586131
    Abstract: A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of which is electrically conductive, an insulating layer that covers the core, and a semiconductor layer that covers the insulating layer. Each of the function lines contacts with, and crosses, the conductor lines. Each of the transistors includes a first ohmic contact region, which is defined by a region where one of the conductor lines crosses one of the function lines and which makes an ohmic contact with the semiconductor layer, a second ohmic contact region, which also makes an ohmic contact with the semiconductor layer, and a channel region, which is defined in the semiconductor layer between the first and second ohmic contact regions.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: September 8, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hirohiko Nishiki, Kazuki Kobayashi
  • Patent number: 7569469
    Abstract: The present invention relates to dielectric nanostructures useful in semiconductor devices and other electronic devices and methods for manufacturing the dielectric nanostructures. The nanostructures generally comprises an array of isolated pillars positioned on a substrate. The methods of the present invention involve using semiconductor technology to manufacture the nanostructures from a mixture of a crosslinkable dielectric material and an amphiphilic block copolymer.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: August 4, 2009
    Assignee: International Business Machines Corporation
    Inventors: Ho-Cheol Kim, Robert D. Miller
  • Patent number: 7550374
    Abstract: Disclosed herein is a technique for forming a high quality ohmic contact utilizable in the fabrication of short-wavelength light emitting diodes (LEDs) emitting blue and green visible light and ultraviolet light, and laser diodes (LDs) using a gallium nitride (GaN) semiconductor. The ohmic contact is formed by depositing a nickel (Ni)-based solid solution on top of a p-type gallium nitride semiconductor. The ohmic contact thus formed has an excellent current-voltage characteristic and a low specific contact resistance due to an increased effective carrier concentration around the surface of the gallium nitride layer, as well as a high transmittance in the short-wavelength region.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: June 23, 2009
    Assignees: Samsung Electronics Co., Ltd., Kwangju Institute of Science and Technology
    Inventors: June-o Song, Dong-suk Leem, Tae-yeon Seong
  • Publication number: 20090134405
    Abstract: A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher than either the first impurity concentration or the third impurity concentration.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 28, 2009
    Inventors: Chiharu OTA, Johji Nishio, Takashi Shinohe
  • Patent number: 7501673
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer may be formed from an amorphous semiconductor material. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: March 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwa Park, Hee-Sook Park, Dae-Yong Kim, Jang-Hee Lee
  • Patent number: 7411219
    Abstract: A semiconductor device can comprise a contact material in substantially continuous contact with a contact region. In an embodiment the contact region may comprise an alloy comprising a wide band-gap material and a low melting point contact material. A wide band-gap material may comprise silicon carbide and a low melting point contact material may comprise aluminum. In another embodiment a substantially uniform ohmic contact may be formed between a contact material and a semiconductor material by annealing the contact at a temperature less than the melting point of the contact material. In an embodiment, the contact may be annealed for more than five hours.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: August 12, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Richard L. Woodin, William F. Seng
  • Patent number: 7368822
    Abstract: The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resistance of the ohmic contact is adjusted by the thicknesses of the three layers.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: May 6, 2008
    Assignee: National Chiao Tung University
    Inventors: Cheng-Shih Lee, Edward Yi Chang, Ke-Shian Chen
  • Patent number: 7312529
    Abstract: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: December 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Clevenger, Mukta G. Farooq, Louis L. Hsu, William F. Landers, Donna S. Zupanski-Nielsen, Carl J. Radens, Chih-Chao Yang
  • Patent number: 7205220
    Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: April 17, 2007
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 7141498
    Abstract: A method of forming an ohmic contact on a substrate composed of a wide-band gap semiconductor material includes: depositing a transition metal group metal on the substrate; annealing the substrate at a high temperature to cause a solid state chemical reaction between the substrate and the deposited metal that forms a modified layer in the substrate having modified properties different than the substrate, and by-products composed of a silicide and a nanocrystalline graphite layer; selectively etching the substrate to remove one or more of the by-products of the solid state chemical reaction from a surface of the substrate; and depositing a metal film composed of a transition group metal over the modified layer on the substrate to form the ohmic contact. The modified layer permits formation of the ohmic contact without high temperature annealing after depositing the metal film.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: November 28, 2006
    Assignees: Denso Corporation, The University of Newcastle upon Tyne
    Inventors: Rajesh Kumar Malhan, Yuichi Takeuchi, Irina Nikitina, Konstantin Vassilevski, Nicholas Wright, Alton Horsfall
  • Patent number: 7135420
    Abstract: Single crystal silicon is grown in a [100] direction to make a bulk. Next, a silicon substrate with a normal of a surface extending in an inclined direction from a [100] direction is cut from the bulk. At this time, when an angle (off-angle) of inclination of the normal is decomposed into a component in a [001] direction and a component in a [010] direction, the component in the [001] direction is made within ±0.2 degrees (excluding 0 degree). An MOS transistor with a moving direction of carriers being the [001] direction is formed on the surface of the silicon substrate. At this time, after steps existing on the surface of the silicon substrate are reconstituted by thermal treatment in a hydrogen atmosphere, a gate insulation film, a gate electrode and the like are formed.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: November 14, 2006
    Assignee: Fujitsu Limited
    Inventor: Hiroe Kawamura
  • Publication number: 20060183272
    Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr3N4) and zirconium oxide (ZrO2) and a method of fabricating such a dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing zirconium oxide using atomic layer deposition using precursor chemicals, followed by depositing zirconium nitride using precursor chemicals, and repeating. Alternatively, the zirconium nitride may be deposited first followed by the zirconium nitride, thus providing a different work function. Such a dielectric may be used as the gate insulator of a MOSFET, a capacitor dielectric, or a tunnel gate insulator in memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because of the reduced leakage current of the physically thicker dielectric layer when compared to an electrically equivalent thickness of silicon dioxide.
    Type: Application
    Filed: February 15, 2005
    Publication date: August 17, 2006
    Inventors: Kie Ahn, Leonard Forbes