Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.

Abstract: Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented.

Abstract: An interlayer structure that, in one implementation, includes a combination of an amorphous or nano-crystalline seed-layer, and one or more metallic layers, deposited on the seed layer, with the fcc, hcp or bcc crystal structure is used to epitaxially orient a semiconductor layer on top of non-single-crystal substrates. In some implementations, this interlayer structure is used to establish epitaxial growth of multiple semiconductor layers, combinations of semiconductor and oxide layers, combinations of semiconductor and metal layers and combination of semiconductor, oxide and metal layers. This interlayer structure can also be used for epitaxial growth of p-type and n-type semiconductors in photovoltaic cells.

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.

Abstract: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component. For this purpose the trench structure has a base (7) and a wall area (8) and is filled with a material (9) with a relatively high dielectric constant (?r). The base area (7) of the trench structure (5) is provided with a heavily doped semiconductor material (11) of the same conductivity type as the lightly doped semiconductor body areas (17), and/or having a metallically conductive material (12).

Abstract: A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief.

Abstract: A smooth electrode is provided. The smooth electrode includes at least one metal layer having thickness greater than about 1 micron; wherein an average surface roughness of the smooth electrode is less than about 10 nm.

Abstract: There is provided a method of manufacturing a silicon carbide semiconductor device including the steps of: in a semiconductor stacked substrate including a first conductivity type silicon carbide crystal substrate, a first conductivity type silicon carbide crystal layer, a second conductivity type silicon carbide crystal layer, and a first conductivity type semiconductor region, forming a trench extending through the first conductivity type semiconductor region and the second conductivity type silicon carbide crystal layer into the first conductivity type silicon carbide crystal layer defined as a bottom surface; forming a silicon film on at least a part of the trench; heating the semiconductor stacked substrate having the silicon film formed to a temperature that is not less than the melting temperature of the silicon film; removing the heated silicon film; forming a gate insulating film on a surface exposed after the silicon film is removed; and forming a gate electrode layer on a surface of the gate insula

Abstract: A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing a portion of the photo resist to expose the protective layer overlying a first region while maintaining the photo resist overlying a second region. The method includes implanting impurities for threshold voltage adjustment into the first region while the second region is substantially free of the impurities for threshold voltage adjustment. The method also includes forming a source region and a drain region. The method further includes providing a conductive structure over the source region. A junction between the conductive structure and the source region is substantially within the second region. The method then provides a storage capacitor in electrical contact with the source region via the conductive structure.

Abstract: A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implanting phosphorous into the silicon layer, diffusing at least the phosphorous by heat-treating the silicon layer, and patterning the silicon layer by using a dry etching technique.

Abstract: A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum mold. By depositing the patterned and full-surface layers in a single process, a photosensitive array with an integrated transistor backplane may be fabricated, resulting in improved sensitivity and performance.

Abstract: A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.

Abstract: A semiconductor device according to the present invention includes: a silicon carbide substrate (11) that has a principal surface and a back surface; a semiconductor layer (12), which has been formed on the principal surface of the silicon carbide substrate; and a back surface ohmic electrode layer (1d), which has been formed on the back surface of the silicon carbide substrate. The back surface ohmic electrode layer (1d) includes: a reaction layer (1da), which is located closer to the back surface of the silicon carbide substrate and which includes titanium, silicon and carbon; and a titanium nitride layer (1db), which is located more distant from the back surface of the silicon carbide substrate.

Abstract: There is provided a method of manufacturing a silicon carbide semiconductor device including the steps of: in a semiconductor stacked substrate including a first conductivity type silicon carbide crystal substrate, a first conductivity type silicon carbide crystal layer, a second conductivity type silicon carbide crystal layer, and a first conductivity type semiconductor region, forming a trench extending through the first conductivity type semiconductor region and the second conductivity type silicon carbide crystal layer into the first conductivity type silicon carbide crystal layer defined as a bottom surface; forming a silicon film on at least a part of the trench; heating the semiconductor stacked substrate having the silicon film formed to a temperature that is not less than the melting temperature of the silicon film; removing the heated silicon film; forming a gate insulating film on a surface exposed after the silicon film is removed; and forming a gate electrode layer on a surface of the gate insula

Abstract: A silicon carbide semiconductor device provided as a semiconductor chip includes a substrate, a drift layer on the substrate, an insulation film on the drift layer, a semiconductor element formed in a cell region of the drift layer, a surface electrode formed on the drift layer and electrically coupled to the semiconductor element through an opening of the insulation film, and a passivation film formed above the drift layer around the periphery of the cell region to cover an outer edge of the surface electrode. The passivation film has an opening through which the surface electrode is exposed outside. A surface of the passivation film is made uneven to increase a length from an inner edge of the opening of the passivation film to a chip edge measured along the surface of the passivation film.

Abstract: A method for fabricating a semiconductor device includes the steps of forming an oxide film on a silicon carbide substrate; forming a gate electrode layer on the oxide film thereafter to pattern the gate electrode layer so as to form a gate electrode, comprising: and performing a thermal treatment to the gate electrode layer or the gate electrode in a mixed gas atmosphere of an oxidized gas and an inert gas.

Abstract: A method of creating a sensor that may include applying a first conductive material on a first portion of a substrate to form a reference electrode and depositing a first mask over the substrate, the first mask having an opening that exposes the reference electrode and a second portion of the substrate. The method may also include depositing a second conductive material into the opening in the first mask, the second conductive material being in direct contact with the reference electrode and depositing a second mask over the second conductive material, the second mask having an opening over the second portion of the substrate, the opening exposing a portion of the second conductive material, which forms a working surface to receive a fluid of interest.

Abstract: A method of fabricating a capacitor in a semiconductor device is provided. The method includes steps of depositing a metal layer for forming a lower electrode on a semiconductor substrate; forming, using an oxidation rate differential, an uneven structure in correspondence with a grain boundary of the metal layer; forming a dielectric layer on the lower electrode having the uneven structure; and forming an upper electrode on the dielectric layer.

Abstract: A method for forming a through electrode is disclosed. The through electrode integrally comprises a columnar electrode filling a through hole, a lower end electrode pad formed on a lower end side of a columnar electrode and having an area wider than the cross section of the through hole, and an upper end electrode pad formed on an upper end side of the columnar electrode and having an area wider than the cross section of the through hole. The lower end electrode pad is arranged is arranged to occlude a lower end opening of the through hole. The columnar electrode fills the through hole by laminating copper on the lower end electrode pad.

Abstract: Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: A method of manufacturing a semiconductor device having electrodes penetrating a semiconductor substrate, the method includes the steps of forming a concave portion extending from an active surface of a semiconductor substrate on which an integrated circuit is formed to an interior of the semiconductor substrate, forming a first insulating layer on an inner surface of the concave portion, filling an inner side of the first insulating layer with an electroconductive material so as to form an electrode, exposing a distal end portion of the first insulating layer by etching a rear surface of the semiconductor substrate, forming a second insulating layer on a rear surface of the substrate, and exposing the distal end portion of the electrode by removing the first insulating layer and the second insulating layer from a distal end portion of the electrode.

Abstract: Structures including a capacitor dielectric material disposed on the surface of an electrode suitable for use in forming capacitors are disclosed. Methods of forming such structures are also disclosed.

Abstract: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.