Multistep Processes For Manufacture Of Device Whose Active Layer, E.g., Base, Channel, Comprises Silicon Carbide (epo) Patents (Class 257/E21.065)
  • Patent number: 9029945
    Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Doyle Craig Capell, Lin Cheng, Sarit Dhar, Charlotte Jonas, Anant Agarwal, John Palmour
  • Patent number: 9012922
    Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Patent number: 9000448
    Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: April 7, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
  • Patent number: 8981384
    Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8955357
    Abstract: A method for embedding a dopant into a glass substrate is provided. The method may include the steps of applying the dopant to a surface of the glass substrate, positioning the glass substrate adjacent to a catalyst such that the dopant is intermediate the catalyst and the glass substrate, heating the glass substrate to a first temperature, operating a directed thermal energy source so as to generate thermal energy incident upon the dopant, reducing the temperature of the glass substrate to a second temperature below the first temperature, and holding the glass substrate at the second temperature for at least a period of time.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: February 17, 2015
    Assignee: Lighting Science Group Corporation
    Inventors: Fredric S. Maxik, David E. Bartine, Theodore Scone, Sepehr Sadeh
  • Patent number: 8895422
    Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Roland Rupp, Thomas Gutt, Michael Treu
  • Patent number: 8889533
    Abstract: A method of manufacturing a semiconductor device by using a substrate processing apparatus comprises a reaction chamber configured to process a plurality of substrates stacked at predetermined intervals, wherein a first gas flow from a first gas supply inlet and a second gas flow from a second gas supply inlet are crossed with each other before these gas flows reach the substrates. The method of manufacturing a semiconductor device comprises: loading the plurality of substrates into the reaction chamber; supplying a silicon-containing gas and a chlorine-containing gas from the first gas supply inlet into the reaction chamber, supplying a carbon-containing gas and a reducing gas from the second gas supply inlet into the reaction chamber and supplying a dopant-containing gas into the reaction chamber from the first gas supply inlet or the second gas supply inlet; and unloading the substrates from the reaction chamber.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takafumi Sasaki, Yoshinori Imai, Koei Kuribayashi, Sadao Nakashima
  • Patent number: 8872193
    Abstract: The present invention provides a technique capable of realizing a silicon carbide semiconductor device having high performance and high reliability. By constituting a channel region by an n?-type, intrinsic, or p?-type channel region and a p+-type channel region, a high channel mobility and a high threshold voltage are realized. Further, by constituting a source region by an n+-type source region and an n++-type source region, and forming the n+-type source region between the p+-type channel region and the n++-type source region, an electric field in the p+-type channel region is relaxed to suppress deterioration of a gate insulating film, and also by electrically connecting a source wiring electrode to the n++-type source region, a contact resistance is decreased.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Tega, Digh Hisamoto, Takashi Takahama
  • Patent number: 8866155
    Abstract: A collector layer is made of silicon carbide having a first conductivity type. A switching element is provided on the collector layer. The switching element includes a junction gate for controlling a channel having a second conductivity type different from the first conductivity type.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideki Hayashi
  • Patent number: 8829532
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: September 9, 2014
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Maik Häberlen, Jörg Lindner, Bernd Stritzker
  • Patent number: 8802546
    Abstract: Gas containing Si, gas containing C and gas containing Cl are introduced into a reacting furnace. SiC epitaxial film is grown on the surface of a 4H—SiC substrate by CVD in a gas atmosphere including raw material gas, additive gas, doping gas and carrier gas. The amount of the gas containing Cl relative to the gas containing Si in the gas atmosphere is reduced gradually. At the start of growth, the number of Cl atoms in the gas containing Cl is three times as large as the number of Si atoms in the gas containing Si. The number of Cl atoms in the gas containing Cl relative to the number of Si atoms in the gas containing Si in the gas atmosphere is reduced at a rate of 0.5%/min to 1.0%/min. The method grows silicon carbide semiconductor film at a high rate.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: August 12, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuyuki Kawada, Yoshiyuki Yonezawa
  • Patent number: 8735905
    Abstract: Provided is a method for producing inexpensive and high-quality aluminum nitride crystals. Gas containing N atoms is introduced into a melt of a Ga—Al alloy, whereby aluminum nitride crystals are made to epitaxially grow on a seed crystal substrate in the melt of the Ga—Al alloy. A growth temperature of aluminum nitride crystals is set at not less than 1000 degrees C. and not more than 1500 degrees C., thereby allowing GaN to be decomposed into Ga metal and nitrogen gas.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: May 27, 2014
    Assignees: Sumitomo Metal Mining Co., Ltd., Tohoku University
    Inventors: Hiroyuki Fukuyama, Masayoshi Adachi, Akikazu Tanaka, Kazuo Maeda
  • Patent number: 8703566
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8563442
    Abstract: In order to provide a method for manufacturing a single crystal SiC substrate that can obtain an SiC layer with good crystallinity, an Si substrate 1 having a surface Si layer 3 of a predetermined thickness and an embedded insulating layer 4 is prepared, and when the Si substrate 1 is heated in a carbon-series gas atmosphere to convert the surface Si layer 3 into a single crystal SiC layer 6, the Si layer in the vicinity of an interface 8 with the embedded insulating layer 4 is left as a residual Si layer 5.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: October 22, 2013
    Assignee: Air Water Inc.
    Inventors: Keisuke Kawamura, Katsutoshi Izumi, Hidetoshi Asamura, Takashi Yokoyama
  • Patent number: 8536582
    Abstract: A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a <0001> direction of less than 8°.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: September 17, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal, Doyle Craig Capell, Albert Burk, Joseph Sumakeris, Michael O'Loughlin
  • Patent number: 8519452
    Abstract: A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: August 27, 2013
    Assignee: DENSO CORPORATION
    Inventor: Rajesh Kumar Malhan
  • Patent number: 8470698
    Abstract: In a method for growing a p-type SiC semiconductor single crystal on a SiC single crystal substrate, using a first solution in which C is dissolved in a melt of Si, a second solution is prepared by adding Al and N to the first solution such that an amount of Al added is larger than that of N added, and the p-type SiC semiconductor single crystal is grown on the SiC single crystal substrate from the second solution. A p-type SiC semiconductor single crystal is provided which is grown by the method as described above, and which contains 1×1020 cm?3 of Al and 2×1018 to 7×1018 cm?3 of N as impurities.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: June 25, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akinori Seki, Yasuyuki Fujiwara
  • Patent number: 8450750
    Abstract: A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×1021 cm?3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the <?2110> direction in the sidewall of the trench. A method of manufacturing the silicon carbide semiconductor device is also provided.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: May 28, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Misako Honaga, Shin Harada
  • Patent number: 8415241
    Abstract: A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 9, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shunsuke Yamada
  • Patent number: 8404536
    Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8394711
    Abstract: Various embodiments of the present disclosure provide a method of simultaneously co-doping a wide band gap material with p-type and n-type impurities to create a p-n junction within the resulting wide band gap composite material. The method includes disposing a sample comprising a dopant including both p-type and n-type impurities between a pair of wide band gap material films and disposing the sample between a pair of opposing electrodes; and subjecting the sample to a preselected vacuum; and heating the sample to a preselected temperature; and applying a preselected voltage across the sample; and subjecting the sample to at least one laser beam having a preselected intensity and a preselected wavelength, such that the p-type and n-type impurities of the dopant substantially simultaneously diffuse into the wide band gap material films resulting in a wide band gap compound material comprising a p-n junction.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 12, 2013
    Assignee: The Curators of the University of Missouri
    Inventors: Mark A. Prelas, Tushar K. Ghos, Robert V. Tompson, Jr., Dabir S. Viswanath, Sudarshan Loyalka
  • Patent number: 8367536
    Abstract: The present invention includes steps below: (a) forming, on a drift layer, a first ion implantation mask and a second ion implantation mask individually by photolithography to form a third ion implantation mask, the first ion implantation mask having a mask region corresponding to a channel region and having a first opening corresponding to a source region, the second ion implantation mask being positioned in contact with an outer edge of the first ion implantation mask and configured to form a base region; (b) implanting impurities of a first conductivity type from the first opening with an ion beam using the third ion implantation mask to form a source region in an upper layer part of the silicon carbide drift layer; (c) removing the first ion implantation mask after the formation of the source region; and (d) implanting impurities of a second conductivity type with an ion beam from a second opening formed in the second ion implantation mask after the removal of the first ion implantation mask to form a bas
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 5, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Watanabe, Naruhisa Miura
  • Patent number: 8278666
    Abstract: The disclosure relates to a high purity 2H-SiC composition and methods for making same. The embodiments represented herein apply to both thin film and bulk growth of 2H-SiC. According to one embodiment, the disclosure relates to doping an underlying substrate or support layer with one or more surfactants to nucleate and grow high purity 2H-SiC. In another embodiment, the disclosure relates to a method for preparing 2H-SiC compositions by nucleating 2H-SiC on another SiC polytype using one or more surfactants. The surfactants can include AlN, Te, Sb and similar compositions. These nucleate SiC into disc form which changes to hexagonal 2H-SiC material.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 2, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, Sean R. McLaughlin, Thomas J. Knight, Robert M. Young, Brian P. Wagner, David A. Kahler, Andre E. Berghmans, David J. Knuteson, Ty R. McNutt, Jerry W. Hedrick, Jr., George M. Bates, Kenneth Petrosky
  • Patent number: 8212261
    Abstract: A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: July 3, 2012
    Assignee: DENSO CORPORATION
    Inventors: Hiroyuki Ichikawa, Hideki Kawahara, Hiroki Nakamura
  • Patent number: 8203151
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 19, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8183573
    Abstract: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: May 22, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Abagnale, Dario Salinas, Sebastiano Ravesi
  • Patent number: 8143616
    Abstract: A structure includes a surface and a non-equilibrium two-dimensional semiconductor micro structure on the surface.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: March 27, 2012
    Assignees: Oregon State University, Hewlett Packard Development Company, L.P.
    Inventors: Gregory S. Herman, Peter Mardilovich, Chinmay Betrabet, Chih-hung Chang, Yu-jen Chang, Doo-Hyoung Lee, Mark W. Hoskins
  • Patent number: 8124510
    Abstract: A method of manufacturing a silicon carbide semiconductor device is disclosed in which a trench and a hole are controlled to have a predetermined configuration even if the silicon carbide semiconductor device is subjected to a heat treatment at a temperature of not lower than 1,500° C. A heat treatment step(s) of a method of the invention includes a step of heat treatment in an argon atmosphere at a temperature in a range of 1,600° C. to 1,800° C. under a pressure of at most 10 Torr for a time duration in a range of 0.1 min to 10 min to evaporate silicon atoms from a surface of the silicon carbide semiconductor substrate or the silicon carbide epitaxial layer and to obtain a silicon carbide surface with a carbon atom concentration of at least 95%.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 28, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuyuki Kawada, Takeshi Tawara
  • Patent number: 8067776
    Abstract: Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: November 29, 2011
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Shigeharu Yamagami, Masakatsu Hoshi, Tetsuya Hayashi, Hideaki Tanaka
  • Patent number: 8053784
    Abstract: A channel layer (40) for forming a portion of a carrier path between a source electrode (100) and a drain electrode (110) is formed on a drift layer (30). The channel layer (40) includes Ge granular crystals formed on the drift layer (30), and a cap layer covering the Ge granular crystals.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: November 8, 2011
    Assignees: Toyota Jidosha Kabushiki Kaisha, Japan Fine Ceramics Center
    Inventors: Akinori Seki, Yukari Tani, Noriyoshi Shibata
  • Publication number: 20110266557
    Abstract: Wide bandgap semiconductor devices are fabricated by providing a wide bandgap semiconductor layer, providing a plurality of recesses in the wide bandgap semiconductor layer, and providing a metal gate contact in the plurality of recesses. A protective layer may be provided on the wide bandgap semiconductor layer, the protective layer having a first opening extending therethrough, a dielectric layer may be provided on the protective layer, the dielectric layer having a second opening extending therethrough that is narrower than the first opening, and a gate contact may be provided in the first and second openings. The metal gate contact may be provided to include a barrier metal layer in the plurality of recesses, and a current spreading layer on the barrier metal layer remote from the wide bandgap semiconductor layer. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: April 28, 2010
    Publication date: November 3, 2011
    Inventors: Van Mieczkowski, Helmut Hagleitner
  • Patent number: 7985610
    Abstract: A method for forming emitter layer of a solar cell includes preparing a substrate including a first impurity of a first conductive type, diffusing a second impurity of a second conductive type opposite to the first conductive type in the substrate to form a first emitter portion of the emitter layer in the substrate, and selectively heating a portion of the first emitter portion, which corresponds to a position for forming at least one electrode, to form a second emitter portion.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: July 26, 2011
    Assignee: LG Electronics Inc.
    Inventor: JaeSung You
  • Patent number: 7981709
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: July 19, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Publication number: 20110169013
    Abstract: A method of growing polygonal carbon from photoresist and resulting structures are disclosed. Embodiments of the invention provide a way to produce polygonal carbon, such as graphene, by energizing semiconductor photoresist. The polygonal carbon can then be used for conductive paths in a finished semiconductor device, to replace the channel layers in MOSFET devices on a silicon carbide base, or any other purpose for which graphene or graphene-like carbon material formed on a substrate is suited. In some embodiments, the photoresist layer forms both the polygonal carbon layer and an amorphous carbon layer over the polygonal carbon layer, and the amorphous carbon layer is removed to leave the polygonal carbon on the substrate.
    Type: Application
    Filed: January 12, 2010
    Publication date: July 14, 2011
    Applicant: Cree, Inc.
    Inventor: Alexander V. Suvorov
  • Patent number: 7951632
    Abstract: An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: May 31, 2011
    Assignee: University of Central Florida
    Inventors: Nathaniel R. Quick, Aravinda Kar, Islam A. Salama
  • Patent number: 7928421
    Abstract: A memory device. The device includes first and second electrode members, in spaced relation on a substrate. A phase change element lies in electrical contact with the first and second electrode elements and spans the space separating them. The phase change element includes two segments, each in contact with one of the electrode elements. The segments are fused together at a location between the two electrodes such that the fused area has a smaller cross-sectional area than does the remainder of the phase change element. The electrodes, the substrate and the phase change element define a chamber containing a vacuum.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: April 19, 2011
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang Lan Lung
  • Patent number: 7923320
    Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 12, 2011
    Assignee: Cree, Inc.
    Inventor: Sei-Hyung Ryu
  • Patent number: 7915705
    Abstract: A SiC semiconductor device includes: a SiC substrate; a SiC drift layer on the substrate having an impurity concentration lower than the substrate; a semiconductor element in a cell region of the drift layer; an outer periphery structure including a RESURF layer in a surface portion of the drift layer and surrounding the cell region; and an electric field relaxation layer in another surface portion of the drift layer so that the electric field relaxation layer is separated from the RESURF layer. The electric field relaxation layer is disposed on an inside of the RESURF layer so that the electric field relaxation layer is disposed in the cell region. The electric field relaxation layer has a ring shape.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: March 29, 2011
    Assignee: Denso Corporation
    Inventors: Takeo Yamamoto, Eiichi Okuno
  • Publication number: 20110070723
    Abstract: A method of manufacturing a silicon carbide semiconductor device is disclosed in which a trench and a hole are controlled to have a predetermined configuration even if the silicon carbide semiconductor device is subjected to a heat treatment at a temperature of not lower than 1,500° C. A heat treatment step(s) of a method of the invention includes a step of heat treatment in an argon atmosphere at a temperature in a range of 1,600° C. to 1,800° C. under a pressure of at most 10 Torr for a time duration in a range of 0.1 min to 10 min to evaporate silicon atoms from a surface of the silicon carbide semiconductor substrate or the silicon carbide epitaxial layer and to obtain a silicon carbide surface with a carbon atom concentration of at least 95%.
    Type: Application
    Filed: April 27, 2010
    Publication date: March 24, 2011
    Applicant: FUJI ELECTRIC SYSTEMS CO.,LTD.
    Inventors: Yasuyuki KAWADA, Takeshi TAWARA
  • Patent number: 7888256
    Abstract: An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO2) layer of a structure designed to conduct current is disclosed. A first epitaxial layer having a first doping level is homo-epitaxially grown on a substrate. The homo-epitaxial growth is preceded by growing, on the first epitaxial layer, a second epitaxial layer having a second doping level higher than the first doping level. Finally, the second epitaxial layer is oxidized so as to be totally removed. Thereby, a silicon oxide layer of high quality is formed, and the interface between the second epitaxial layer and silicon oxide has a low trap density.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: February 15, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Giovanni Abagnale, Dario Salinas, Sebastiano Ravesi
  • Patent number: 7879705
    Abstract: A method is set forth of forming an ohmic electrode having good characteristics on a SiC semiconductor layer. In the method, a Ti-layer and an Al-layer are formed on a surface of the SiC substrate. The SiC substrate having the Ti-layer and the Al-layer is maintained at a temperature that is higher than or equal to a first temperature and lower than a second temperature until all Ti in the Ti-layer has reacted with Al. The first temperature is the minimum temperature of a temperature zone at which the Ti reacts with the Al to form Al3Ti, and the second temperature is the minimum temperature of a temperature zone at which the Al3Ti reacts with SiC to form Ti3SiC2. As a result of this maintaining of temperature step, an Al3Ti-layer is formed on the surface of the SiC substrate. The method also comprises further heating the SiC substrate having the Al3Ti-layer to a temperature that is higher than the second temperature.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: February 1, 2011
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akira Kawahashi, Masahiro Sugimoto, Akinori Seki, Masakatsu Maeda, Yasuo Takahashi
  • Publication number: 20110018005
    Abstract: A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 27, 2011
    Applicant: ROHM CO., LTD.
    Inventor: Yuki NAKANO
  • Publication number: 20100308344
    Abstract: In a method for growing a p-type SiC semiconductor single crystal on a SiC single crystal substrate, using a first solution in which C is dissolved in a melt of Si, a second solution is prepared by adding Al and N to the first solution such that an amount of Al added is larger than that of N added, and the p-type SiC semiconductor single crystal is grown on the SiC single crystal substrate from the second solution. A p-type SiC semiconductor single crystal is provided which is grown by the method as described above, and which contains 1×1020 cm?3 of Al and 2×1018 to 7×1018 cm?3 of N as impurities.
    Type: Application
    Filed: January 28, 2009
    Publication date: December 9, 2010
    Inventors: Akinori Seki, Yasuyuki Fujiwara
  • Patent number: 7825417
    Abstract: A technique for suppressing the bowing of an epitaxial wafer is provided. The epitaxial wafer is prepared by successively epitaxially growing a target group III-nitride layer, an interlayer and another group III-nitride layer on a substrate with a buffer layer. The interlayer is mainly composed of a mixed crystal of GaN and InN expressed in a general formula (GaxIny)N (0?x?1, 0?y?1, x+y=1) (or a crystal of GaN), and does not contain Al. The interlayer is epitaxially formed at a lower growth temperature than those of the group III-nitride layers, more specifically at a temperature in a range of at least 350° C. to not more than 1000° C.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: November 2, 2010
    Assignee: NGK Insulators, Ltd.
    Inventors: Masahiro Sakai, Mitsuhiro Tanaka, Takashi Egawa
  • Patent number: 7820534
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes ion-implanting an impurity in a surface of a silicon carbide wafer, and forming a carbon protection film of a predetermined thickness over all surfaces of the silicon carbide wafer, which has been ion-implanted with the impurity, by a chemical vapor deposition method that deposits a film by pyrolyzing a hydrocarbon gas. The method also includes annealing the silicon carbide wafer after the forming the carbon protection film.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: October 26, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takao Sawada, Tomokatsu Watanabe
  • Publication number: 20100244048
    Abstract: A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (1) including a silicon carbide layer (2); a high-concentration impurity region (4) provided in the silicon carbide layer (2); an ohmic electrode (9) electrically connected with the high-concentration impurity region (4); a channel region electrically connected with the high-concentration impurity region; a gate insulating layer (14) provided on the channel region; and a gate electrode (7) provided on the gate insulating layer (14). The ohmic electrode (9) contains an alloy of titanium, silicon and carbon, and the gate electrode (7) contains titanium silicide.
    Type: Application
    Filed: February 12, 2008
    Publication date: September 30, 2010
    Inventors: Masashi Hayashi, Shin Hasimoto
  • Publication number: 20100237356
    Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region.
    Type: Application
    Filed: March 20, 2009
    Publication date: September 23, 2010
    Inventors: Sarah Kay Haney, Sei-Hyung Ryu
  • Publication number: 20100224886
    Abstract: A second trench in each source electrode portion (Schottky diode portion) is formed to have a depth equal to or larger than the depth of a first trench in each gate electrode portion. The distance between the first and second trenches is set to be not longer than 10 ?m. A source electrode is formed in the second trench and a Schottky junction is formed in the bottom portion of the second trench. In this manner, it is possible to provide a wide band gap semiconductor device which is small-sized, which has low on-resistance and low loss characteristic, in which electric field concentration into a gate insulating film is relaxed to suppress reduction of a withstand voltage, and which has high avalanche breakdown tolerance at turn-off time.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 9, 2010
    Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.
    Inventor: Noriyuki IWAMURO
  • Patent number: 7781312
    Abstract: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: August 24, 2010
    Assignee: General Electric Company
    Inventors: Kevin Sean Matocha, Vinayak Tilak, Stephen Daley Arthur, Zachary Matthew Stum
  • Patent number: 7781242
    Abstract: A method of forming a vertical structure light emitting diode with a heat exhaustion structure, comprising the steps of: providing a sapphire substrate; producing a number of recesses on the sapphire substrate, each of which has a depth of p; forming a buffer layer having a number of protrusions, each of which has a height of q smaller than p so that when the protrusions of the buffer layer are accommodated within the recesses of the sapphire substrate, a number of gaps are formed therebetween for heat exhaustion; growing a number of luminescent layers on the buffer layer, having a medium layer formed between the luminescent layers and the buffer layer; etching through the luminescent layers and the buffer layer to form a duct for heat exhaustion; removing the sapphire substrate by excimer laser lift-off (LLO); roughening the medium layer; and depositing electrodes on the roughened medium layer.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: August 24, 2010
    Assignee: Walsin Lihwa Corporation
    Inventors: Shiue-Lung Chen, Jeng-Kuo Feng, Ching-Hwa Chang Jean, Jang-Ho Chen