Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

Abstract: In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.

Abstract: A semiconductor substrate having a main surface and made of a wide band gap semiconductor is provided, the semiconductor substrate including a device region formed in the semiconductor substrate, and a peripheral region formed to surround the device region. In the peripheral region, the semiconductor substrate includes a first semiconductor region having a first conductivity type, and a second semiconductor region formed on the first semiconductor region and having the main surface, the second semiconductor region having a second conductivity type different from the first conductivity type. At an outermost periphery of the peripheral region, the semiconductor substrate has a plurality of stepped portions annularly surrounding the device region, and the second semiconductor region is formed along the stepped portion.

Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.

Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n?-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p?-type body layer, and the n?-type drift layer between the p?-type body layer and the n?-type drift layer.

Abstract: A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

Abstract: A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.

Abstract: A first dielectric layer is formed over a semiconductor layer in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer in the NVM and logic regions. The charge storage layer is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed over the semiconductor layer in the NVM and logic regions which surrounds the charge storage structure and the dummy gate. The dummy gate is replaced with a logic gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. A third dielectric layer is formed over the charge storage structure, and a control gate layer is formed over the third dielectric layer.

Abstract: A semiconductor device with a JFET is disclosed. The semiconductor device includes a trench and a contact embedded layer formed in the trench. A gate wire is connected to the contact embedded layer, so that the gate wire is connected to an embedded gate layer via the contact embedded layer. In this configuration, it is possible to downsize a contact structure between the embedded gate layer and the gate wire.

Abstract: An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.

Abstract: A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.

Abstract: A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.

Abstract: According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.

Abstract: A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.

Abstract: A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. An extended terrace surface is formed at a surface of an initial growth layer on a 4H—SiC substrate by annealing with the initial growth layer covered with an Si film, and then a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion having a polytype stable at a low temperature is grown on the extended terrace surface, and a 4H—SiC portion is grown on the other region. A trench is formed by selectively removing the 3C—SiC portion with the 4H—SiC portion remaining, and a gate electrode of a UMOSFET is formed in the trench. A channel region of the UMOSFET can be controlled to have a low-order surface, and a silicon carbide semiconductor device having high channel mobility and excellent performance characteristics is obtained.

Abstract: A MEMS transducer includes a substrate, a membrane layer and a back-plate layer. The membrane layer is supported by the substrate. The back-plate layer is supported by the membrane layer and includes a respective sidewall portion and a respective raised portion. One or more columns, separate from the sidewall portion of the back-plate layer, connect the back-plate layer, the membrane layer and the substrate.

Abstract: A semiconductor light emitter (A) includes an n-type semiconductor layer (2), a p-type semiconductor layer (4), and an active layer (3) between these two layers (2, 4). The light emitter (A) further includes an n-side electrode (5) on the n-type layer (2) and a p-side electrode (6) on the p-type layer (4). An insulating layer (7) covers the n-type and p-type layers (2),(4), while also partially covering the n-side and p-side electrodes (5),(6), leaving part of the electrodes (5, 6) exposed. The n-side electrode (5) has a first Al layer (51) formed on the n-type layer (2) and a second Ni, W, Zr or Pt layer (52) formed on the first layer (51). The p-side electrode (6) has a first Au layer (61) formed on the p-type layer (4), and a second Ni, W, Zr or Pt layer (62) formed on the first layer (61).

Abstract: A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.

Abstract: The present disclosure relates to a silicon carbide (SiC) bipolar junction transistor (BJT), where the surface region between the emitter and base contacts (1, 2) on the transistor is given a negative electric surface potential with respect to the potential in the bulk SiC. The present disclosure also relates to a method for increasing the current gain in a silicon carbide (SiC) bipolar junction transistor (BJT) by the reduction of the surface recombination at the SiC surface between the emitter and base contacts (1, 2) of the transistor.

Abstract: Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.

Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.

Abstract: Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.

Abstract: A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.

Abstract: A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types sui

Abstract: An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth.

Abstract: A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer.

Abstract: A structure and method for a silicon carbide (SiC) gate turn-off (GTO) thyristor device operable to provide an increased turn-off gain comprises a cathode region, a drift region having an upper portion and a lower portion, wherein the drift region overlies the cathode region, a gate region overlying the drift region, an anode region overlying the gate, and at least one ohmic contact positioned on each of the gate region, anode region, and cathode region, wherein the upper portion of the drift region, the gate region, and the anode region have a free carrier lifetime and mobility lower than a comparable SiC GTO thyristor for providing the device with an increased turn-off gain, wherein the free carrier lifetime is approximately 10 nanoseconds. The reduced free carrier lifetime and mobility are affected by altering the growth conditions, such as temperature under which epitaxy occurs.

Abstract: A semiconductor device includes: a semiconductor layer including silicon carbide, which has been formed on a substrate; a semiconductor region 15 of a first conductivity type defined on the surface of the semiconductor layer 10; a semiconductor region 14 of a second conductivity type, which is defined on the surface 10s of the semiconductor layer so as to surround the semiconductor region 15 of the first conductivity type; and a conductor 19 with a conductive surface 19s that contacts with the semiconductor regions 15 and 14 of the first and second conductivity types. On the surface 10s of the semiconductor layer, the semiconductor region 15 of the first conductivity type has at least one first strip portion 60 that runs along a first axis i. The width C1 of the semiconductor region 15 of the first conductivity type as measured along the first axis i is greater than the width A1 of the conductive surface 19s as measured along the first axis i.

Abstract: A method of forming a semiconductor device may include forming a terminal region of a first conductivity type within a semiconductor layer of the first conductivity type. A well region of a second conductivity type may be formed within the semiconductor layer wherein the well region is adjacent at least portions of the terminal region within the semiconductor layer, a depth of the well region into the semiconductor layer may be greater than a depth of the terminal region into the semiconductor layer, and the first and second conductivity types may be different. An epitaxial semiconductor layer may be formed on the semiconductor layer, and a terminal contact region of the first conductivity type may be formed in the epitaxial semiconductor layer with the terminal contact region providing electrical contact with the terminal region. In addition, an ohmic contact may be formed on the terminal contact region. Related structures are also discussed.

Abstract: A method of manufacturing a silicon carbide semiconductor device having low interface state density in an interface region between a gate insulating film and a silicon carbide layer is provided. An epitaxially grown layer is grown on a 4H-SiC substrate, and thereafter ion implantation is performed to form a p well region, a source region and a p+ contact region that are ion implantation layers. Thereafter, using thermal oxidation or CVD, the gate insulating film formed by a silicon oxide film is formed on the p well region, the source region and the p+ contact region. Then, plasma is generated using a gas containing N2O, which is the gas containing at least any one of oxygen and nitrogen, so as to expose the gate insulating film to plasma.

Abstract: A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed.

Abstract: A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film and an edge portion of the gate electrode is rounded and oxidized.

Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.

Abstract: A SiC semiconductor device includes: a substrate; a drift layer on a first side of the substrate; a trench in the drift layer; a base region contacting a sidewall of the trench; a source region in an upper portion of the base region; a gate electrode in the trench via a gate insulation film; a source electrode on the source region; and a drain electrode on a second side of the substrate. The source region has multi-layered structure including a first layer and a second layer. The first layer as an upper layer contacts the source electrode with ohmic contact. The second layer as a lower layer has an impurity concentration, which is lower than an impurity concentration of the first layer.

Abstract: An SiC semiconductor device includes a substrate, a drift layer disposed on a first surface of the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a trench penetrating the source region and the base region to the drift layer, a gate insulating layer disposed on a surface of the trench, a gate electrode disposed on a surface of the gate insulating layer, a first electrode electrically coupled with the source region and the base region, a second electrode disposed on the second surface of the substrate, and a second conductivity-type layer disposed at a portion of the base region located under the source region. The second conductivity-type layer has the second conductivity type and has an impurity concentration higher than the base region.

Abstract: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.

Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.

Abstract: In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P? type impurity in a polycrystalline silicon layer formed on an N? type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.

Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A first conductive type impurity is diffused in the silicon carbide substrate. A method of producing a semiconductor device includes preparing the silicon carbide substrate forming a first conductive type impurity diffused region on the first main surface therein; preparing a silicon substrate having a third main surface and a fourth main surface opposite to the third main surface, said silicon substrate including a thermal oxidation film formed on the third main surface; and attaching the third main surface to the first main surface via the thermal oxidation film.

Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: A method of fabricating a storage capacitor includes depositing a first titanium nitride layer on a dielectric layer using a chemical vapor deposition technique or an atomic layer deposition technique performed at a first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas at a predetermined flow ratio and depositing a second titanium nitride layer on the first titanium nitride layer using a chemical vapor deposition process performed at a second temperature that is greater than the first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas.

Abstract: A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate.

Abstract: A transistor formed on a semiconductor substrate of a first conductivity type in a well formed in the substrate and doped with the first conductivity type to an impurity level higher than that of the substrate. A drain doped to a second conductivity type opposite to said first conductivity type is disposed in the well. A pair of opposed source regions doped to the second conductivity type are disposed in the well and are electrically coupled together. They are separated from opposing outer edges of the drain region by channels. A pair of gates are electrically coupled together and disposed above and insulated from the channels. A region of the well disposed below the drain is doped so as to reduce capacitive coupling between the drain and the well.

Abstract: An exemplary method for forming an insulator layer over a silicon carbide substrate includes providing a silicon carbide substrate and anodizing the silicon carbide substrate in a liquid ambient at a temperature of not more than 200° C. to form a silicon dioxide layer thereon. Also provided are silicon carbide transistors and methods for fabricating the same.

Abstract: A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body.