Diffusion Source (epo) Patents (Class 257/E21.14)
  • Patent number: 10170375
    Abstract: A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 1, 2019
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9034670
    Abstract: A method (100; 100a; 100b; 100c) for manufacturing a solar cell from a semiconductor substrate (1) of a first conductivity type, the semiconductor substrate having a front surface (2) and a back surface (3). The method includes in a sequence: texturing (102) the front surface to create a textured front surface (2a); creating (103) by diffusion of a dopant of the first conductivity type a first conductivity-type doped layer (2c) in the textured front surface and a back surface field layer (4) of the first conductivity type in the back surface; removing (105; 104a) the first conductivity-type doped layer from the textured front surface by an etching process adapted for retaining texture of the textured front surface; creating (106) a layer of a second conductivity type (6) on the textured front surface by diffusion of a dopant of the second conductivity type into the textured front surface.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: May 19, 2015
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventors: Paul Cornelis Barton, Ronald Cornelis Gerard Naber, Arno Ferdinand Stassen
  • Patent number: 8865513
    Abstract: Provided is a manufacturing method of a semiconductor quantum dot-sensitized solar cell. More particularly, the manufacturing method according to the present invention includes: a quantum dot forming step of forming a semiconductor layer containing a group 4 element and InP on a substrate and then performing heat-treatment on the substrate including the semiconductor layer formed thereon to remove indium (In) therefrom, thereby forming an n-type semiconductor quantum dot, which is a group 4 element quantum dot doped with phosphorus (P).
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: October 21, 2014
    Assignee: Korea Research Institute of Standards and Science
    Inventors: Kyung Joong Kim, Seung Hui Hong, Jae Hee Park, Woo Lee
  • Patent number: 8802535
    Abstract: Techniques for fabricating a field effect transistor (FET) device having a doped core and an undoped or counter-doped epitaxial shell are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A wafer is provided having a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon. At least one fin core is formed in the wafer. Ion implantation is used to dope the fin core. Corners of the fin core are reshaped to make the corners rounded or faceted. An epitaxial shell is grown surrounding the fin core, wherein the epitaxial shell includes a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Siyuranga O. Koswatta, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8735297
    Abstract: A method for fabricating an anti-fuse memory cell having a semiconductor structure with a minimized area. The method includes providing a reference pattern for the semiconductor structure, and applying a reverse OPC technique that includes inverting selected corners of the reference pattern. The reverse OPC technique uses photolithographic distortions to provide a resulting fabricated pattern that is intentionally distorted relative to the reference pattern. By inverting corners of a geometric reference pattern, the resulting distorted pattern will have an area that is reduced relative to the original reference pattern. This technique is advantageous for reducing the area of a selected region of a semiconductor structure which may otherwise not be possible through normal design parameters.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: May 27, 2014
    Assignee: Sidense Corporation
    Inventor: Wlodek Kurjanowicz
  • Publication number: 20120318350
    Abstract: A dopant material is disclosed. The dopant material comprises a polycrystalline silicon and a dopant element in the polycrystalline silicon. A concentration of the dopant element is at least 1×1018 atoms/cm3 and no greater than 1×1020 atoms/cm3. A method for producing a dopant material is also disclosed. A fused mixture is generated by mixing and fusing a silicon material with an element that serves as the dopant source. A coagulate of the dopant material is generated by cooling and coagulating the fused mixture. A semiconductor substrate is disclosed. The semiconductor substrate comprises a semiconductor material to which the dopant material is added. A solar cell element comprising the semiconductor substrate, a first electrode, and a second electrode is disclosed. The semiconductor substrate comprises a first surface and a second surface corresponding to a rear surface of the first surface.
    Type: Application
    Filed: February 23, 2011
    Publication date: December 20, 2012
    Inventors: Youhei Sakai, Satoshi Kawamura, Mayu Takimoto
  • Publication number: 20120058632
    Abstract: A method of forming a metal contact on a silicon substrate is disclosed. The method includes depositing a nanoparticle ink on a substrate surface in a pattern, the nanoparticle ink comprising set of nanoparticles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified nanoparticle layer with a nanoparticle layer thickness of greater than about 50 nm. The method further includes depositing an SiNx layer on the substrate surface, SiNx layer having a SiNx layer thickness of between about 50 nm and about 110 nm; exposing the substrate to an etchant that is selective to the densified nanoparticle layer for a second time period and at a second temperature in order to create a via; and forming a metal contact in the via, wherein an ohmic contact is formed with the silicon substrate.
    Type: Application
    Filed: June 29, 2011
    Publication date: March 8, 2012
    Inventors: Malcolm Abbott, Daniel Kray
  • Patent number: 8101486
    Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: January 24, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Witold Maszara, Hemant Adhikari
  • Patent number: 8058159
    Abstract: A method for fabricating a component is disclosed. The method includes: providing a member having an effective work function of an initial value, disposing a sacrificial layer on a surface of the member, disposing a first agent within the member to obtain a predetermined concentration of the agent at said surface of the member, annealing the member, and removing the sacrificial layer to expose said surface of the member, wherein said surface has a post-process effective work function that is different from the initial value.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: November 15, 2011
    Assignee: General Electric Company
    Inventors: Vance Robinson, Stanton Earl Weaver, Joseph Darryl Michael
  • Publication number: 20110169049
    Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.
    Type: Application
    Filed: July 6, 2009
    Publication date: July 14, 2011
    Applicant: IMEC
    Inventors: Roger Loo, Frederik Leys, Matty Caymax
  • Patent number: 7662720
    Abstract: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: February 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Eun-Jung Yun, Dong-Won Kim, Jae-Man Yoon
  • Patent number: 7611977
    Abstract: This invention discloses a process of phosphorus diffusion for manufacturing solar cell, comprising annealing a mono-crystalline silicon wafer in a nitrogen atmosphere at 900-950° C. for twenty to thirty minutes, carrying oxidation treatment in a hydrogen chloride atmosphere at 850-1050° C. to form a 10 to 30 nm thick oxide layer on the surface of said silicon wafer, diffusing from a phosphorus source at 850-900° C., until a block resistance of a material surface is controlled at 40 to 50 ohms, and the junction depth is at 0.2 to 1.0 microns, and annealing in a nitrogen atmosphere at 700-750° C. for thirty to sixty minutes to complete the phosphorus diffusion of said mono-crystalline silicon wafer. This invention allows the use of 4 N˜5 N mono-crystalline silicon as the material for manufacturing solar cells, so, the low purity material such as metallurgical silicon can be used, which greatly reduces the cost of materials.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: November 3, 2009
    Assignee: CSI Cells Co. Ltd.
    Inventors: Lingjun Zhang, Yunxiang Zuo
  • Publication number: 20080124905
    Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.
    Type: Application
    Filed: December 21, 2007
    Publication date: May 29, 2008
    Inventors: Gabriela Brase, Martin Ostermayr, Erwin Ruderer
  • Patent number: 7326631
    Abstract: Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and field-isolation regions insulating these regions from each other are formed in a silicon body. Then, a layer of a first metal is deposited in which locally, in a part of the active regions, nitrogen is introduced. On the layer of the first metal, a layer of a second metal is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal permeable to nitrogen is deposited an the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: February 5, 2008
    Assignee: NXP B.V.
    Inventors: Robert Lander, Jacob Christopher Hooker, Robertus Adrianus Maria Wolters
  • Patent number: 7303967
    Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: December 4, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hoon Sa