Using Diffusion Into Or Out Of A Solid From Or Into A Liquid Phase, E.g., Alloy Diffusion Process (epo) Patents (Class 257/E21.153)
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Patent number: 10475945Abstract: A bipolar solar cell includes a backside junction formed by a silicon substrate and a first doped layer of a first dopant type on the backside of the solar cell. A second doped layer of a second dopant type makes an electrical connection to the substrate from the front side of the solar cell. A first metal contact of a first electrical polarity electrically connects to the first doped layer on the backside of the solar cell, and a second metal contact of a second electrical polarity electrically connects to the second doped layer on the front side of the solar cell. An external electrical circuit may be electrically connected to the first and second metal contacts to be powered by the solar cell.Type: GrantFiled: August 5, 2016Date of Patent: November 12, 2019Assignee: SunPower CorporationInventor: Peter John Cousins
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Patent number: 9887312Abstract: A solar cell wherein: an emitter layer is formed on a light-receiving-surface side of a crystalline silicon substrate, with a dopant of the opposite conductivity type from the silicon substrate added to said emitter layer; a passivation film is formed on the surface of the silicon substrate; and an extraction electrode and a collector electrode are formed. Said extraction electrode extracts photogenerated charge from the silicon substrate, and said collector electrode contacts the extraction electrode at least partially and collects the charge collected at the extraction electrode. The extraction electrode contains a first electrode that consists of a sintered conductive paste containing a dopant that makes silicon conductive. Said first electrode, at least, is formed so as to pass through the abovementioned passivation layer. The collection electrode contains a second electrode that has a higher conductivity than the aforementioned first electrode.Type: GrantFiled: October 23, 2015Date of Patent: February 6, 2018Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Hiroshi Hashigami, Takenori Watabe, Mitsuhito Takahashi, Shintarou Tsukigata, Takashi Murakami, Ryo Mitta, Yoko Endo, Hiroyuki Otsuka
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Patent number: 8685810Abstract: A method for a power layout of an integrated circuit. The method includes providing at least one unit power cell. The unit power cell includes at least one power grid cell. Each power grid cell has at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The first power layer has conductive lines in at least two different directions and the at least one second power layer has conductive lines in at least two different directions. The method further includes filling a target area in the power layout by at least one unit power cell to implement at least one power cell.Type: GrantFiled: March 13, 2013Date of Patent: April 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Chieh Yang
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Patent number: 8421205Abstract: A power layout of an integrated circuit includes at least one power grid cell. Each power gird cell includes at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The at least one first power layer has conductive lines in at least two different directions. The at least one second power layer has conductive lines in at least two different directions.Type: GrantFiled: May 6, 2010Date of Patent: April 16, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chung-Chieh Yang
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Publication number: 20120276725Abstract: Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material.Type: ApplicationFiled: April 26, 2011Publication date: November 1, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Jerome A. Imonigie, Prashant Raghu, Theodore M. Taylor, Scott E. Sills
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Publication number: 20120227810Abstract: Photovoltaic modules comprise solar cells having doped domains of opposite polarities along the rear side of the cells. The doped domains can be located within openings through a dielectric passivation layer. In some embodiments, the solar cells are formed from thin silicon foils. Doped domains can be formed by printing inks along the rear surface of the semiconducting sheets. The dopant inks can comprise nanoparticles having the desired dopant.Type: ApplicationFiled: May 17, 2012Publication date: September 13, 2012Inventor: Henry Hieslmair
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Patent number: 8216940Abstract: A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion.Type: GrantFiled: February 2, 2011Date of Patent: July 10, 2012Assignee: Renesas Electronics CorporationInventor: Koichi Motoyama
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Patent number: 7892976Abstract: A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion.Type: GrantFiled: June 5, 2009Date of Patent: February 22, 2011Assignee: Renesas Electronics CorporationInventor: Koichi Motoyama
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Publication number: 20110021012Abstract: Compositions for forming doped regions in semiconductor substrates, methods for fabricating such compositions, and methods for forming doped regions using such compositions are provided. In one embodiment, a dopant-comprising composition comprises a conductivity-determining type impurity dopant, a silicate carrier, a solvent, and a moisture adsorption-minimizing component. In another embodiment, a dopant-comprising composition comprises a conductivity-determining type impurity dopant, a silicate carrier, a solvent, and a high boiling point material selected from the group consisting of glycol ethers, alcohols, and combinations thereof. The high boiling point material has a boiling point of at least about 150° C.Type: ApplicationFiled: July 20, 2010Publication date: January 27, 2011Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Roger Yu-Kwan Leung, Wenya Fan, Jan Nedbal, Lea M. Dankers
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Patent number: 7842554Abstract: The invention relates to a semiconductive device comprising a die with at least one defined hot-spot area lying in a plane on the die and a cooling structure comprising nanotubes such as carbon nanotubes extending in a plane different than the plane of the hot-spot area and outwardly from the plane of the hot-spot area. The nanotubes are operatively associated with the hot-spot area to decrease any temperature gradient between the hot-spot area and at least one other area on the die defined by a temperature lower than the hot-spot area. A matrix material comprising a second heat conducting material substantially surrounds the nanotubes and is operatively associated with and in heat conducting relation with the other area on the die defined by a temperature lower than the hot-spot area.Type: GrantFiled: July 8, 2008Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Christos Dimitrios Dimitrakopoulos, Christos John Georgiou
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Patent number: 7763530Abstract: The invention relates to a method of doping semiconductor material. Essentially, the method comprises mixing a quantity of particulate semiconductor material with an ionic salt or a preparation of ionic salts. Preferably, the particulate semiconductor material comprises nanoparticles with a size in the range 1 nm to 100 ?m. Most preferably, the particle size is in the range from 50 nm to 500 nm. Preferred semiconductor materials are intrinsic and metallurgical grade silicon. The invention extends to a printable composition comprising the doped semiconductor material as well as a binder and a solvent. The invention also extends to a semiconductor device formed from layers of the printable composition having p and n type properties.Type: GrantFiled: August 23, 2006Date of Patent: July 27, 2010Assignee: University of Cape TownInventors: David Thomas Britton, Margit Härting
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Publication number: 20100175744Abstract: A diffusing agent composition is used for ink-jet printing and contains a P-type impurity-diffusing component (A), a water-soluble polymer compound (B) having an alcoholic hydroxyl group, and a solvent (C) containing an organic solvent having a surface tension of at most about 30 mN/m.Type: ApplicationFiled: January 4, 2010Publication date: July 15, 2010Applicant: TOKYO OHKA KOGYO CO., LTD.Inventors: Takaaki Hirai, Katsuya Tanitsu
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Patent number: 7727868Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host matrix atomic radius and selecting a second dopant element with a second atomic radius smaller than a host matrix atomic radius. The methods and devices further include selecting amounts of each dopant element of the plurality of dopant elements wherein amounts and atomic radii of each of the plurality of dopant elements complement each other to reduce a host matrix lattice strain. The methods and devices further include introducing the plurality of dopant elements to a selected region of the host matrix and annealing the selected region of the host matrix.Type: GrantFiled: August 30, 2005Date of Patent: June 1, 2010Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Jerome M. Eldridge
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Patent number: 7635860Abstract: To increase productivity of organic thin-film transistors, in an organic thin-film transistor manufacturing equipment, a liquid containing at least either one of a wiring material and a semiconductor material is coated on a substrate to form a number of organic thin-film transistors. Substrate carrying means carry the substrate. The substrate is heated by a first heating means, and the temperature of the substrate is controlled by a controller. The liquid containing at least either one of the wiring material and the semiconductor material is heated by a second heating means, and the temperature of this liquid is controlled also by the controller.Type: GrantFiled: January 19, 2007Date of Patent: December 22, 2009Assignee: Hitachi, Ltd.Inventors: Tomohiro Inoue, Akira Doi, Masahiko Ando
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Patent number: 7611920Abstract: A room temperature operation polycrystalline infrared responsive photodetector, manufactured by a process, comprising the steps of patterning vacuum-deposited material and dry-etching a photonic crystal structure with resonant coupling tuned to long wavelengths.Type: GrantFiled: November 17, 2006Date of Patent: November 3, 2009Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Steven R. Jost
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Publication number: 20080111206Abstract: A method of processing a substrate having first and second surfaces applies a first dopant in liquid form on the first surface of the substrate, and applies a second dopant in liquid form on the second surface of the substrate. The method then causes the first and second dopants to diffuse into the substrate.Type: ApplicationFiled: November 2, 2007Publication date: May 15, 2008Applicant: EVERGREEN SOLAR, INC.Inventors: Jack I. Hanoka, Christopher E. Dube, Carolyn K. Schad
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Patent number: 7303967Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.Type: GrantFiled: June 23, 2004Date of Patent: December 4, 2007Assignee: Hynix Semiconductor Inc.Inventor: Seung Hoon Sa