Floating Or Plural Gate Structure (epo) Patents (Class 257/E21.179)
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Patent number: 10103168Abstract: According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction.Type: GrantFiled: June 21, 2017Date of Patent: October 16, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kotaro Noda
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Patent number: 9842850Abstract: An integrated circuit (IC) using high-? metal gate (HKMG) technology with an embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. The logic gate is arranged within a high ? dielectric layer. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate. The control transistor further comprises a charge trapping layer underlying the control gate. The control and select gates are a first material, and the logic gate is a second material. A high-?-last method for manufacturing the IC is also provided.Type: GrantFiled: December 30, 2015Date of Patent: December 12, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Cheng Wu, I-Ching Chen
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Patent number: 9837314Abstract: Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.Type: GrantFiled: February 2, 2017Date of Patent: December 5, 2017Assignee: Tokyo Electron LimitedInventors: Jeffrey Smith, Anton J. deVilliers
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Patent number: 9761314Abstract: A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer.Type: GrantFiled: December 2, 2013Date of Patent: September 12, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-Dal Choi
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Patent number: 9754955Abstract: An integrated circuit (IC) using high-? metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high ? dielectric layers. A high-?-last method for manufacturing the IC is also provided.Type: GrantFiled: December 30, 2015Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Cheng Wu, I-Ching Chen
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Patent number: 9000534Abstract: According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate.Type: GrantFiled: June 17, 2009Date of Patent: April 7, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Andreas H. Knorr, Frank Scott Johnson
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Patent number: 8969947Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.Type: GrantFiled: March 7, 2011Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
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Patent number: 8962416Abstract: A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.Type: GrantFiled: July 30, 2013Date of Patent: February 24, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Cheong Min Hong, Sung-Taeg Kang, Konstantin V. Loiko, Jane A. Yater
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Patent number: 8921915Abstract: A nonvolatile memory device includes a multi-finger type control gate formed over a substrate, a multi-finger type floating gate formed over the substrate and disposed close to the control gate with gaps defined therebetween, and spacers formed on sidewalls of the control gate and the floating gate, and filling the gaps.Type: GrantFiled: August 7, 2013Date of Patent: December 30, 2014Assignee: SK Hynix Inc.Inventor: Sung-Kun Park
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Patent number: 8906762Abstract: Methods for manufacturing non-volatile memory devices including peripheral transistors with reduced and less variable gate resistance are described. In some embodiments, a NAND-type flash memory may include floating-gate transistors and peripheral transistors (or non-floating-gate transistors). The peripheral transistors may include select gate transistors (e.g., drain-side select gates and/or source-side select gates) and/or logic transistors that reside outside of a memory array region. A floating-gate transistor may include a floating gate of a first conductivity type (e.g., n-type) and a control gate including a lower portion of a second conductivity type different from the first conductivity type (e.g., p-type). A peripheral transistor may include a gate including a first layer of the first conductivity type, a second layer of the second conductivity type, and a cutout region including one or more sidewall diffusion barriers that extends through the second layer and a portion of the first layer.Type: GrantFiled: September 27, 2012Date of Patent: December 9, 2014Assignee: Sandisk Technologies, Inc.Inventor: Kenji Sato
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Patent number: 8895390Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.Type: GrantFiled: March 14, 2013Date of Patent: November 25, 2014Assignee: Intermolecular, Inc.Inventor: Dipankar Pramanik
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Patent number: 8895441Abstract: One aspect of the present invention includes a method of fabricating an electronic device. According to one embodiment, the method comprises providing a substrate having dielectric oxide surface areas adjacent to electrically conductive surface areas, chemically bonding an anchor compound with the dielectric oxide surface areas so as to form an anchor layer, initiating the growth of a metal using the electrically conductive surface areas and growing the metal so that the anchor layer also bonds with the metal. The anchor compound has at least one functional group capable of forming a chemical bond with the oxide surface and has at least one functional group capable of forming a chemical bond with the metal. Another aspect of the present invention is an electronic device. A third aspect of the present invention is a solution comprising the anchor compound.Type: GrantFiled: February 24, 2012Date of Patent: November 25, 2014Assignee: Lam Research CorporationInventor: Artur Kolics
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Patent number: 8872239Abstract: An image pickup device according to the present invention is an image pickup device in which a plurality of pixel are arranged in a semiconductor substrate. Each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion (FD) region, a transfer gate that transfers charges in the first semiconductor region to the FD region, and an amplification transistor whose gate is electrically connected to the FD region. The photoelectric conversion element has an outer edge which has a recessed portion in plan view, a source region and a drain region of the amplification transistor are located in the recessed portion, and the FD region is surrounded by the photoelectric conversion region or is located in the recessed portion in plan view.Type: GrantFiled: December 21, 2012Date of Patent: October 28, 2014Assignee: Canon Kabushiki KaishaInventors: Kazuaki Tashiro, Shin Kikuchi
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Patent number: 8836049Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.Type: GrantFiled: June 13, 2012Date of Patent: September 16, 2014Assignee: United Microelectronics Corp.Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
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Patent number: 8829622Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.Type: GrantFiled: June 13, 2012Date of Patent: September 9, 2014Assignee: STMicroelectronics (Crolles 2) SASInventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
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Patent number: 8809934Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.Type: GrantFiled: August 4, 2013Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Hiraku Chakihara, Yasushi Ishii
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Patent number: 8796752Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.Type: GrantFiled: September 6, 2013Date of Patent: August 5, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jae-Hwang Sim
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Patent number: 8765551Abstract: According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.Type: GrantFiled: December 28, 2012Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-youl Yang, Dae-hong Eom, Byoung-moon Yoon, Kyung-hyun Kim, Se-ho Cha
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Patent number: 8759177Abstract: According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks.Type: GrantFiled: August 31, 2012Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Yanai, Koichi Matsuno, Seiro Miyoshi
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Patent number: 8748964Abstract: Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.Type: GrantFiled: October 22, 2010Date of Patent: June 10, 2014Assignee: Micron Technology, Inc.Inventors: Rhett T. Brewer, Durai V. Ramaswamy
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Patent number: 8748249Abstract: A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.Type: GrantFiled: April 26, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-kyu Yang, Ki-hyun Hwang, Phil-ouk Nam, Jae-young Ahn, Han-mei Choi, Dong-chul Yoo
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Patent number: 8741760Abstract: A semiconductor device has a semiconductor substrate, a plurality of first conductive patterns, a second conductive pattern having a top surface of which stepwisely or gradually decreases in height in a direction from a side facing the first conductive pattern toward an opposite side, a first insulation film formed over the plurality of first conductive patterns and the second conductive pattern, and a third conductive pattern formed over the first insulation film.Type: GrantFiled: June 12, 2012Date of Patent: June 3, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Hikaru Kokura
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Patent number: 8722525Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.Type: GrantFiled: June 21, 2011Date of Patent: May 13, 2014Assignee: Micron Technology, Inc.Inventor: Nishant Sinha
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Publication number: 20140120713Abstract: An oxide-containing layer is formed directly on a semiconductor layer in an NVM region, and a first partial layer of a first material is formed over the oxide-containing layer in the NVM region. A first high-k dielectric layer is formed directly on the semiconductor layer in a logic region. A first conductive layer is formed over the first dielectric layer in the logic region. A second partial layer of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer if the cell is a floating gate cell or a select gate if the cell is a split gate cell.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Inventors: MEHUL D. SHROFF, MARK D. HALL, Frank K. Baker, JR.
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Patent number: 8679918Abstract: Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.Type: GrantFiled: May 15, 2007Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 8673716Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.Type: GrantFiled: April 8, 2002Date of Patent: March 18, 2014Assignee: Spansion LLCInventors: Mark T. Ramsbey, Tazrien Kamal, Jean Y. Yang, Emmanuil Lingunis, Hidehiko Shiraiwa, Yu Sun
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Patent number: 8664059Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate; depositing a first material such that the first material overlaps the STI region and a portion of a top surface of the STI region is exposed; etching a recess in the STI region by a first etch, the recess having a bottom and sides; depositing a second material over the first material and on the sides and bottom of the recess in the STI region; and etching the first and second material by a second etch to form a floating gate of the device, wherein the floating gate extends into the recess.Type: GrantFiled: April 26, 2012Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventor: Erwan Dornel
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Patent number: 8647940Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.Type: GrantFiled: August 9, 2013Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Toshitake Yaegashi
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Patent number: 8614473Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: GrantFiled: July 18, 2011Date of Patent: December 24, 2013Assignee: Micron Technology, Inc.Inventor: Todd Abbott
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Patent number: 8587036Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.Type: GrantFiled: December 12, 2008Date of Patent: November 19, 2013Assignee: eMemory Technology Inc.Inventors: Shih-Chen Wang, Wen-Hao Ching
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Patent number: 8580662Abstract: A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is positioned apart from the first and second diffusion regions.Type: GrantFiled: October 7, 2011Date of Patent: November 12, 2013Assignee: Renesas Electronics CorporationInventor: Masakuni Shimizu
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Publication number: 20130292757Abstract: A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.Type: ApplicationFiled: September 6, 2012Publication date: November 7, 2013Inventor: Seiichi ARITOME
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Publication number: 20130277728Abstract: The present disclosure provides a fabricating method of a semiconductor chip which includes the following steps. First, a substrate is provided. The substrate defines a memory unit region and a peripheral logic region. Then, a first spacer is formed around a stack structure of the memory unit region. The first space includes a first silicon oxide layer and the first silicon oxide layer directly contacts with the stack structure. After that, a silicon nitride layer is formed on both the first spacer and the peripheral logic region. Finally, the additional silicon nitride layer on the first spacer is removed but portions of the additional silicon nitride layer around gate structures in the peripheral logic region are remained.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventor: Ching-Hung KAO
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Patent number: 8546217Abstract: A flash memory cell is provided. The flash memory cell includes: a substrate with a source line thereon; a word line and a word line dielectric layer on each side of the source line; an isolating dielectric layer which isolates the source line from the word line and the word line dielectric layer on each side of the source line; a gate stack on an outer side of each word line dielectric layer, including a floating gate dielectric layer, a floating gate, a control gate dielectric layer and a control gate; a first spacer, disposed on an outer sidewall of each word line dielectric layer and on each control gate; and a source region in the substrate and in contact with the source line. The space may be saved and the costs may be reduced.Type: GrantFiled: August 28, 2012Date of Patent: October 1, 2013Assignee: Grace Semiconductor Manufacturing CorporationInventor: Steam Cao
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Patent number: 8541273Abstract: A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness TFD. A capping layer is formed on the substrate having a formed thickness TFC. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness TTD. The thickness of the capping layer is adjusted from TFC to about a target thickness TTC.Type: GrantFiled: September 23, 2010Date of Patent: September 24, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sung Mun Jung, Swee Tuck Woo, Sanford Chu, Liang Choo Hsia
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Patent number: 8507340Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.Type: GrantFiled: February 21, 2013Date of Patent: August 13, 2013Assignee: Renesas Electronics CorporationInventors: Hiraku Chakihara, Yasushi Ishii
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Patent number: 8492210Abstract: The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer.Type: GrantFiled: February 25, 2011Date of Patent: July 23, 2013Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Qingqing Liang, Huilong Zhu, Huicai Zhong
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Patent number: 8482050Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.Type: GrantFiled: July 18, 2011Date of Patent: July 9, 2013Assignee: Micron Technology, Inc.Inventor: Todd Abbott
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Patent number: 8466507Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.Type: GrantFiled: August 1, 2011Date of Patent: June 18, 2013Assignee: Renesas Electronics CorporationInventors: Tatsuya Fukumura, Yoshihiro Ikeda, Shunichi Narumi, Izumi Takesue
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Publication number: 20130134496Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.Type: ApplicationFiled: August 30, 2012Publication date: May 30, 2013Inventors: Sung-Soo AHN, O IK KWON, Bum-Soo KIM, Hyun-Sung KIM, Kyoung-Sub SHIN, Min-Kyung YUN, Seung-Pil CHUNG, Won-Bong JUNG
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Patent number: 8450174Abstract: A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.Type: GrantFiled: June 30, 2011Date of Patent: May 28, 2013Assignee: SanDisk Technologies Inc.Inventor: Masaaki Higashitani
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Patent number: 8450783Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.Type: GrantFiled: December 27, 2010Date of Patent: May 28, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato, Shuhei Nagatsuka, Takanori Matsuzaki, Hiroki Inoue
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Publication number: 20130115766Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method, a tunnel insulating film and a first conductive film are formed on a semiconductor layer. A trench is formed. A first sacrifice film is buried in the trench. A second sacrifice film having density higher than that of the first sacrifice film is formed on the first sacrifice film in the trench. An insulating film is formed on the first conductive film and the second sacrifice film. A second conductive film is formed on the insulating film. The second sacrifice film is exposed. The first sacrifice film and the second sacrifice film are removed.Type: ApplicationFiled: March 21, 2012Publication date: May 9, 2013Inventor: Keisuke NAKAZAWA
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Publication number: 20130099300Abstract: The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an I-shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.Type: ApplicationFiled: November 30, 2011Publication date: April 25, 2013Applicant: PEKING UNIVERSITYInventors: Yimao Cai, Song Mei, Ru Huang
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Patent number: 8426263Abstract: A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.Type: GrantFiled: March 31, 2011Date of Patent: April 23, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Bradley P. Smith, James W. Miller
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Patent number: 8426270Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.Type: GrantFiled: July 22, 2011Date of Patent: April 23, 2013Assignee: Intermolecular, Inc.Inventor: Dipankar Pramanik
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Patent number: 8426272Abstract: Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.Type: GrantFiled: July 10, 2012Date of Patent: April 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-bae Yoon, Jeong-dong Choe, Hee-soo Kang, Dong-hoon Jang, Ki-hyun Kim
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Patent number: 8420482Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.Type: GrantFiled: July 21, 2009Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Juwan Lim, Sungkweon Baek, Kwangmin Park, Seungjae Baik, Kihyun Hwang
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Patent number: 8409951Abstract: Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.Type: GrantFiled: April 4, 2012Date of Patent: April 2, 2013Assignee: SanDisk Technologies Inc.Inventors: Jarrett Jun Liang, Vinod Robert Purayath, Takashi Whitney Orimoto
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Patent number: RE44156Abstract: First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as ?6V˜12V, ?12V˜6V, ?9V˜9V etc.Type: GrantFiled: March 29, 2006Date of Patent: April 16, 2013Assignee: United Microelectronics Corp.Inventors: Rong-Ching Chen, Ching-Chun Huang, Jy-Hwang Lin