Manufacture Of Electrode On Semiconductor Body Using Process Other Than By Epitaxial Growth, Diffusion Of Impurities, Alloying Of Impurity Materials, Or Radiation Bombardment (epo) Patents (Class 257/E21.158)

  • Patent number: 10811320
    Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chi Huang, Kuo-Bin Huang, Ying-Liang Chuang, Ming-Hsi Yeh
  • Patent number: 10777743
    Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Ravasio, Samuele Sciarrillo, Andrea Gotti
  • Patent number: 10332744
    Abstract: Techniques herein include forming single or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. A relatively thin portion of mandrel material stretches from a base of mandrels to each other and underneath sidewall spacers and other fill materials, thereby forming a film of mandrel material over an underlying layer, which provides advantages with etch selectivity in a patterning process. Accordingly a multi-line layer is formed with materials having different etch resistivities to be able to selectively etch one or more of the materials to create features where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 25, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Anton J. deVilliers, Andrew W. Metz
  • Patent number: 10163706
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 10133099
    Abstract: A device substrate manufacturing method includes forming a debonding layer on a carrier substrate. An inorganic adhesive layer is formed on at least a portion of the debonding layer. A process substrate is formed on the carrier substrate. A device is formed on the process substrate, and the process substrate is separated from the carrier substrate.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyunwoo Koo, Taewoong Kim, Sunho Kim, Danbi Choi
  • Patent number: 10068904
    Abstract: A semiconductor device includes first and second active regions and a field insulating film contacting between the first and second active regions, and a gate electrode structure traversing the first and second active regions and the field insulating film, wherein the gate electrode structure includes a first portion positioned across the first active region and the field insulating film, a second portion positioned across the second active region and the field insulating film, and a third portion contacting the first and second portions. The gate electrode structure includes a gate electrode having an insertion film traversing the first and second active regions and the field insulating film second active region, and a filling film on the insertion film. A thickness of the gate electrode in the third portion is different from a thickness of the gate electrode in the first portion and the second portion.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Youn Kim, Gi Gwan Park
  • Patent number: 10020184
    Abstract: A method for cleaning a substrate is provided. The method includes providing a substrate. Metal compound residues are formed over the substrate. The method includes exposing the substrate to an organic plasma to volatilize the metal compound residues. The organic plasma is generated from a gas. The gas includes an organic gas, and the organic gas is made of a hydrocarbon compound or an alcohol compound.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Ping Hong, Yu-Cheng Liu
  • Patent number: 9865504
    Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Ting-Yeh Chen
  • Patent number: 9761548
    Abstract: A bond pad structure includes a first oxide layer that overlies a substrate. A plurality of adhesion structures are formed over the first oxide layer. A second oxide layer is formed over the plurality of adhesion structures and the first oxide layer. Each one of a plurality of contact openings formed within a surface region of the second oxide layer includes one or more sides and is aligned over at least a portion of a top surface of a corresponding one of the plurality of adhesion structures. A barrier layer is formed within the surface region that is over the second oxide layer and within the plurality of contact openings and over the at least a portion of the top surface of the corresponding ones of the plurality of adhesion structures. A metal layer is formed over the barrier layer.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: September 12, 2017
    Assignee: Infineon Technologies AG
    Inventors: Peter Irsigler, Martina Seider-Schmidt, Sebastian Schmidt, Oliver Hellmund
  • Patent number: 9627202
    Abstract: The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: SoonMok Ha, Sung-Wook Hwang, Joonsoo Park, Dae-Yong Kang, Byungjun Jeon
  • Patent number: 9620624
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming a semiconductor layer on a substrate, forming a first insulating film on the semiconductor layer, forming a metal layer on the first insulating film, forming a first portion and a second portion in the metal layer, implanting an impurity into the semiconductor layer by using the first portion and the second portion as masks, forming a gate electrode by reducing the second portion in addition to removing the first portion, and implanting an impurity into the semiconductor layer by using the gate electrode as a mask.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 11, 2017
    Assignee: Japan Display Inc.
    Inventor: Shinichi Kawamura
  • Patent number: 9534287
    Abstract: An ion implantation machine includes an enclosure that is connected to a pump device, a negatively polarized substrate-carrier that is arranged inside the enclosure, and a plasma feed device in the form of a generally cylindrical body extending between an initial section and a terminal section, the device having a main chamber provided with an ionization cell, the main chamber being provided with a gas delivery orifice, and the final section of the main chamber being provided with a head-loss component for creating a pressure drop relative to the body. Furthermore, the plasma feed device also includes an auxiliary chamber arranged beyond the final section, the auxiliary chamber opening out into the enclosure at the terminal section.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: January 3, 2017
    Assignee: ION BEAM SERVICES
    Inventors: Frank Torregrosa, Laurent Roux
  • Patent number: 9530852
    Abstract: It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: December 27, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Junichi Koezuka, Shunpei Yamazaki
  • Patent number: 9524987
    Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9508747
    Abstract: A thin film transistor array substrate is discussed. The thin film transistor array substrate includes, according to one embodiment, gate and data lines crossing each other, a gate insulation film, a gate electrode, an active layer, an etch stop layer formed on the active layer to define a channel region of the active layer, and a source electrode and a drain electrode formed on the active layer. The etch stop layer is between the source and drain electrodes spaced apart from the etch stop layer. The source electrode and the drain electrode include a first electrode layer and a second electrode layer disposed on the first electrode. The first electrode layer is formed from a dry-etchable material and the second electrode layer is formed from a wet-etchable material.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: November 29, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Hee Dong Choi
  • Patent number: 9477127
    Abstract: The present invention provides a manufacture method of a thin film transistor substrate: forming a first metal layer, a first chemical vapor deposition layer, a second metal layer and a second chemical vapor deposition layer on a substrate; forming photoresistor on the second chemical vapor deposition layer; implementing exposure and development to the photoresistor; implementing via etching to a via area where the photoresistor on the second chemical vapor deposition layer is removed; implementing photoresistor ashing to remove the photoresistor in the area of the common capacitor; etching the silicon nitride layer; forming a pixel electrode layer. The present invention is capable of promoting video quality and saving the backlight power consumption.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 25, 2016
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Jinlei Li
  • Patent number: 9437574
    Abstract: An electronic component package includes a substrate and dielectric structure. The dielectric structure includes a top surface having a protrusion portion and a lower portion. The protrusion portion is located at first height that is greater than a second height of the lower portion. A conductive bond pad is located over the dielectric structure. A ball bond electrically couples the bond pad and a bond wire. An intermetallic compound located between the ball bond and bond pad is formed of material of the ball bond and bond pad and electrically couples the bond pad to the ball bond. A portion of the bond pad is vertically located between a portion of the lower portion of the top surface of the dielectric structure and the intermetallic compound. No portion of the bond pad is vertically located between at least a portion of the protrusion portion and the intermetallic compound.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: September 6, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tu-Anh N. Tran, Chu-Chung Lee
  • Patent number: 9035321
    Abstract: There is provided a semiconductor device including an ohmic junction layer which is excellent in surface flatness and uniformity of composition in an interface with a semiconductor substrate and thus can give a sufficiently high adhesiveness with a Schottky junction layer.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 19, 2015
    Assignee: SHOWA DENKO K.K.
    Inventors: Akihiro Matsuse, Kotaro Yano
  • Patent number: 9034756
    Abstract: A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Jung Tsai, Hsiang-Huan Lee, Ming Han Lee
  • Patent number: 9006016
    Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: April 14, 2015
    Assignee: Board of Regents, The University of Texas System
    Inventors: Zeynep Celik-Butler, Suraj K. Patil, Donald Philip Butler
  • Patent number: 8999787
    Abstract: A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 8993430
    Abstract: According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuya Matsuda
  • Patent number: 8981523
    Abstract: Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yan Zun Li, Zhengwen Li, Chengwen Pei, Jian Yu
  • Patent number: 8975633
    Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
  • Patent number: 8975106
    Abstract: A method for forming a chip package includes: providing a substrate having a first and a second surfaces; removing a portion of the substrate to form openings in the substrate, wherein the openings extend from the first surface towards the second surface or from the second surface towards the first surface; after forming the openings, at least a first portion of the substrate serves as a first movable bulk, and at least a second portion of the substrate serves as a second movable bulk, wherein the first movable bulk and the second movable bulk are respectively located between the openings; disposing a protecting substrate on the second surface of the substrate; forming a through-hole in the protecting substrate; and forming a conducting layer on the protecting substrate, wherein the conducting layer extends from a surface of the protecting substrate into the through-hole to electrically connect the second movable bulk.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: March 10, 2015
    Inventor: Chien-Hung Liu
  • Patent number: 8969207
    Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gerard M. Schmid, Jeremy A. Wahl, Richard A. Farrell, Chanro Park
  • Patent number: 8963326
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Patent number: 8962980
    Abstract: A method of readily forming a dye-sensitized solar cell having a porous layer of increased thickness. The dye-sensitized solar cell includes a translucent substrate, and a plurality of collecting electrode traces formed on the translucent substrate. The solar cell also includes a trench that is trapezoidal in cross-section and is formed on the translucent substrate between the collecting electrode traces. The solar cell also includes a porous layer upon which a sensitizing dye is adsorbed. The porous layer covers the translucent substrate within the trench and the collecting electrode traces.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: February 24, 2015
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hirotaka Mori
  • Patent number: 8951833
    Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: February 10, 2015
    Assignee: WaferTech, LLC
    Inventor: Kun-Yi Liu
  • Patent number: 8946721
    Abstract: A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: William K. Henson
  • Patent number: 8946029
    Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Hoong Shing Wong, Min-hwa Chi
  • Patent number: 8946084
    Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, I-Ching Lin
  • Patent number: 8941120
    Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiko Ariyoshi, Takuma Suzuki, Takashi Shinohe
  • Patent number: 8937015
    Abstract: The present invention relates to a method for forming a via in a substrate which includes the flowing steps of: (a) providing a substrate having a first surface and a second surface; (b) forming an accommodating groove and a plurality of pillars on the first surface of the substrate, the accommodating groove having a side wall and a bottom wall, the pillars remaining on the bottom wall of the accommodating groove; (c) forming a first insulating material in the accommodating groove and between the pillars; (d) removing the pillars so as to form a plurality of grooves in the first insulating material; and (e) forming a first conductive metal in the grooves. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Jen Wang, Chung-Hsi Wu
  • Patent number: 8932936
    Abstract: A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chih-Hsiung Peng, Chi-Kang Chang, Chiang Mu-Chi, Sheng-Yu Chang, Hua Feng Chen, Chao-Cheng Chen, Ryan Chia-Jen Chen
  • Patent number: 8933544
    Abstract: An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 13, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Yin Qian, Tiejun Dai, Howard E. Rhodes, Hongli Yang
  • Patent number: 8927993
    Abstract: A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer on a second passivation layer and having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer and having second and third thicknesses, respectively, the second thickness greater than the third thickness; etching the auxiliary insulating layer, the second passivation layer and a first passivation layer to form a drain contact hole; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose the first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: January 6, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Young-Ki Jung, Seok-Woo Lee, Kum-Mi Oh, Dong-Cheon Shin, In-Hyuk Song, Han-Seok Lee, Won-Keun Park
  • Patent number: 8922003
    Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 30, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., Nanyang Technological University
    Inventors: Dexter Xueming Tan, Yoke King Chin, Kin Leong Pey
  • Patent number: 8916925
    Abstract: A vertical semiconductor device includes a first active pillar vertically protruded from a semiconductor substrate; a first vertical gate connected to at least one side of the first active pillar and formed along a direction that crosses a buried bit line; and a first body line connected to at least one side of the first active pillar which is not connected to the first vertical gate.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: December 23, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jeong Seob Kye
  • Patent number: 8907434
    Abstract: A MEMS inertial sensor and a method for manufacturing the same are provided. The method includes: depositing a first carbon layer on a semiconductor substrate; patterning the first carbon layer to form a fixed anchor bolt, an inertial anchor bolt and a bottom sealing ring; forming a contact plug in the fixed anchor bolt and a contact plug in the inertial anchor bolt; forming a first fixed electrode, an inertial electrode and a connection electrode on the first carbon layer, where the first fixed electrode and the inertial electrode constitute a capacitor; forming a second carbon layer on the first fixed electrode and the inertial electrode; and forming a sealing cap layer on the second carbon layer and the top sealing ring. Under an inertial force, only the inertial electrode may move, the fixed electrode will almost not move or vibrate, which improves the accuracy of the MEMS inertial sensor.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 9, 2014
    Assignee: Lexvu Opto Microelectronics Technology (Shanghai) Ltd.
    Inventors: Zhiwei Wang, Deming Tang, Lei Zhang, Jianhong Mao, Fengqin Han
  • Patent number: 8906707
    Abstract: The invention provides a multilayered device and the method for fabricating the same. The multilayered device comprises a substrate, a first layer deposited on the substrate, a second layer deposited on the first layer, and a third layer deposited on the second layer. The coverage of the second layer is determined by a rate of crystallization of the third layer. The rate of crystallization of the third layer is determined by measuring X-ray diffraction of the device.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: December 9, 2014
    Assignee: Industry-University Cooperation Foundation Sogang University
    Inventors: Young Joo Lee, Hyunjung Kim
  • Patent number: 8901010
    Abstract: Methods for protecting a texturized region and a lightly doped diffusion region of a solar cell to improve solar cell lifetime and efficiency are disclosed. In an embodiment, an example method includes providing a solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, a silicon substrate and where the silicon substrate includes a texturized region and a lightly doped diffusion region. The method includes placing the solar cell on a receiving medium with the front side of the solar cell placed on an upper surface of the receiving medium, where the upper surface of the receiving medium prevents damage to the to the lightly doped diffusion region and damage to the texturized region on the front side of the solar cell during a contact printing process or transferring. In an embodiment, the lightly doped diffusion region has a doping concentration below 1×1019 cm?3 and the receiving medium includes a material having a moh's hardness in the range of 5-10.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: SunPower Corporation
    Inventors: Staffan Westerberg, Florito Dennis Tingchuy Vicente, Michael Cudzinovic, Princess Carmi Tomada, Jemellee Guiao
  • Patent number: 8884342
    Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
  • Patent number: 8883636
    Abstract: A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Zih-Song Wang, Shu-Cheng Lin, Yoshikazu Miyawaki
  • Patent number: 8884439
    Abstract: Disclosed herein is a joining electrode including: an insulating layer; a recessed portion formed in the insulating layer; a covering layer formed on a side surface and a bottom surface of the recessed portion; and a joining metallic layer formed on the covering layer and having an upper surface protruding from a surface of the insulating layer.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventor: Kenichi Aoyagi
  • Patent number: 8877627
    Abstract: Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P? region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P? region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P? region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: November 4, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Dunga, Sanghyun Lee, Masaaki Higashitani, Tuan Pham
  • Patent number: 8866134
    Abstract: Provided are a light-emitting device and a photovoltaic cell having excellent characteristics. A light-emitting device (10) includes a cathode (34), an anode (32), a light-emitting layer (50) interposed between the cathode (34) and the anode (32), and an electron injection layer (44) provided between the cathode (34) and the light-emitting layer (50) and connected to the cathode (34), in which at least one of the anode (32) and the cathode (34) contains a conductive material having an aspect ratio of 1.5 or more, and the electron injection layer (44) contains an organic compound having at least one of an ionic group and a polar group.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Takayuki Iljima, Kenta Tanaka, Masanobu Tanaka, Hideyuki Higashimura
  • Patent number: 8866254
    Abstract: Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely filling the inter-row trench with a dielectric material, and forming a fin and a insulating projection at least in part by etching a gate trench in the substrate. In some embodiments, the insulating projection includes at least some of the dielectric material in the inter-row trench.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8865591
    Abstract: A method for forming an n-type contact electrode, which includes an n-type nitride semiconductor such as AlxInyGazN (with x, y, and z being rational numbers that sum to 1.0 and fulfill the relations 0<x?1.0, 0?y?0.1, and 0?z<1.0), includes: a step in which a first electrode metal layer including at least one metal selected from titanium, vanadium, and tantalum is formed on a layer of the aforementioned n-type semiconductor and then heat-treated at a temperature between 800° C. and 1200° C.; and a step in which a second electrode metal layer is formed on top of the first electrode metal layer and then heat-treated at a temperature between 700° C. and 1000° C. The second electrode metal layer contains a layer comprising a metal, such as aluminum, that has a work function between 4.0 and 4.8 eV and a resistivity between 1.5×10?6 ?·cm and 4.0×10?6 ?·cm.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 21, 2014
    Assignee: Tokuyama Corporation
    Inventors: Naoki Tamari, Toru Kinoshita
  • Patent number: 8859312
    Abstract: A method of manufacturing an integrated circuit (IC) for driving a flexible display includes depositing a pattern of spatially non-repetitive features in a first layer on a flexible substrate, said pattern of spatially non-repetitive features not substantially regularly repeating in both of two orthogonal directions (x,y) in the plane of the substrate; depositing a pattern of spatially repetitive features in a second layer on said first layer; aligning said second layer and said first layer so as to allow electrical coupling between said non-repetitive features and said repetitive features, wherein distortion compensation is applied during deposition of said repetitive features to enable said alignment.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: October 14, 2014
    Assignee: Plastic Logic Limited
    Inventors: Carl Hayton, Paul A. Cain