Abstract: Provided is a semiconductor device having, over the main surface of a semiconductor substrate, a main circuit region and a memory cell array of a flash memory. The memory cell array has a floating gate electrode for accumulating charges of data, while the main circuit region has a gate electrode of MIS•FET constituting the main circuit. In the main circuit region, an insulating film made of a silicon nitride film is formed to cover the gate electrode, whereby miniaturization of elements in the main circuit region is not impaired. The memory cell array has no such insulating film. This means that the upper surface of the floating gate electrode is not contiguous to the insulating film but is covered directly with an interlayer insulating film. According to such a constitution, leakage of electrons from the floating gate electrode of the memory cell array can be suppressed or prevented and the flash memory thus obtained has improved data retention characteristics.

Abstract: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).

Abstract: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

Abstract: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

Abstract: A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

Abstract: A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode.

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract: A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

Abstract: Example embodiments may provide nonvolatile memory devices and example methods of fabricating nonvolatile memory devices. Example embodiment nonvolatile memory devices may include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.

Abstract: A method for forming a nonvolatile memory device includes forming a tunnel insulation layer and a first conductive layer over a substrate. A trench is formed by partially etching the first conductive layer, the tunnel insulation layer and the substrate, thereby forming a resultant structure. An insulation layer is formed over the resultant structure to fill the trench. The insulation layer polished using a slurry including a polisher diluted with deionized water to expose the first conductive layer.

Abstract: A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.

Abstract: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during deposition. In a third embodiment, initial temperature of the CVD device is kept at about 400° C., whereby the start of natural oxidation of the deposition surface is prevented and production circumstances of the semiconductor element is not deteriorated. Then, the CVD device is heated up to CVD temperature of about 750° C. or about 650° C., to deposit oxide.

Abstract: A memory cell has a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film. An FET has a lower gate electrode, a second inter-gate insulating film having an opening and arranged on the lower gate electrode, a block film having a function to block diffusion of metal atoms and formed on at least the opening, and an upper gate electrode connected electrically to the lower gate electrode via the block film and arranged on the second inter-gate insulating film. The control gate electrode and the upper gate electrode have a Full-silicide structure.

Abstract: A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.

Abstract: A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof and is so formed that the upper surface thereof will be set with height between those of the upper and bottom surfaces of the first conductor. The second insulator includes a three-layered insulating film formed of a silicon oxide film, a silicon oxynitride film and a silicon oxide film formed on the first conductor and element isolation insulator. The second conductor is formed on the second insulator.

Abstract: The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted through the conductive material to form at least one implant region between and/or beneath the partially formed transistor gates, and subsequently the conductive material is removed from between the gates. The gates can be incorporated into various semiconductor assemblies, including, for example, DRAM assemblies.

Abstract: Provided is a memory device formed using quantum devices and a method for manufacturing the same. A memory device includes a substrate; a source region and a drain region formed in the substrate so as to be separated from each other by a predetermined interval. A memory cell is formed on the surface of the substrate to connect the source region and the drain region, and has a plurality of nano-sized quantum dots filled with material for storing electrons. A control gate is formed on the memory cell and controls the number of electrons stored in the memory cell. It is possible to embody a highly efficient and highly integrated memory device by providing a memory device having nano-sized quantum dots and a method for manufacturing the same.

Abstract: A semiconductor device that reduces the interval between gate electrodes. The semiconductor device includes a semiconductor substrate, a plurality of gate electrodes buried in the semiconductor substrate, a plurality of first insulation layers arranged respectively on the plurality of gate electrodes, a conductive layer formed on the surface of the semiconductor substrate near the plurality of gate electrodes and the plurality of first insulation layers, and a conductor layer arranged on at least the conductive layer.

Abstract: A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width, and a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation films interposed therebetween. The device further includes an element isolating insulation film buried into the element isolation trench. The top surface of the element isolating insulation film is located higher than that of the first charge-storage layer.

Abstract: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A semiconductor device having spacer patterns formed at the sidewalls of gate electrodes and a method of fabricating the same are disclosed. The semiconductor device includes a gate pattern, including a plurality of gate electrodes, formed on a semiconductor substrate, a barrier insulation layer formed on the entire surface of the substrate including the gate pattern, and spacer patterns formed at opposite sidewall regions of the respective gate electrodes surrounded by the barrier insulation layer such that the spacer patterns have a height less than that of the respective gate electrodes.

Abstract: The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

Abstract: A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate and the substrate, and between the floating gate and the control gate.

Abstract: A substrate including a memory cell region and a peripheral circuit region is provided. A first dielectric layer, a first conductive layer and a mask layer are formed on the substrate. Isolation structures are formed, and the isolation structures in the memory cell region are denser than that in the peripheral circuit region. A protective layer is formed on the substrate in the second region. The mask layer in the first region is removed. A second conductive layer is formed on the substrate, wherein the protective layer has an etching selectivity the same to that of the second conductive layer. Portion of the second conductive layer and the protective layer are removed by using the isolation structures as stop layer. Portion of the isolation structures and the mask layer in the peripheral circuit region are removed. A second dielectric layer and a third conductive layer are formed on the substrate.

Abstract: The present invention relates to a method of forming a dielectric layer of a flash memory device. In a process of forming a dielectric layer of a flash memory device, the dielectric layer may include a first oxide layer, a high dielectric layer, and a second oxide layer is formed. Accordingly, a leakage current characteristic and reliability of the flash memory device can be improved.

Abstract: A non-volatile memory device and a fabrication method thereof. A high-k layer is formed between nitrogen-containing insulating layers. Accordingly, an interface reaction between an underlying oxide layer and the high-k insulating layer or between the oxide layer and a floating gate or a control gate can be prohibited and the electrical characteristics of the high-k layer can be improved, and a non-volatile memory device with high performance and high reliability can be fabricated.

Abstract: A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and polysilicon island. The floating gate can bear an inverted T-shape. The floating gate can also be disposed above an isolated semiconductive substrate such as in a shallow-trench isolation semiconductive substrate. Electronic devices may include the floating gate as part of a field effect transistor.

Abstract: Flash memory devices and methods for fabricating the same. In one example embodiment, a method of fabricating a flash memory includes various acts. First, a tunnel oxide layer is formed on an active region of a semiconductor substrate. Next, a gate region is formed by sequentially forming a floating gate, a gate insulating layer, and a control gate over the tunnel oxide layer. Then, a sidewall oxide layer is formed on a gate region. Next, a fluorine plasma ion implantation process is performed on the sidewall oxide layer. Then, a nitride layer is deposited on the sidewall oxide layer. Next, an etch process is performed to form spacer insulating layers.

Abstract: A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of select gate dielectric layers are disposed between the select gates and the substrate. A plurality of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A plurality of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.

Abstract: A storage device has a two bit cell in which the select electrode is nearest the channel between two storage layers. Individual control electrodes are over individual storage layers. Adjacent cells are separated by a doped region that is shared between the adjacent cells. The doped region is formed by an implant in which the select gates of adjacent cells are used as a mask. This structure provides for reduced area while retaining the ability to perform programming by source side injection.

Abstract: A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.

Abstract: A method of manufacturing a semiconductor device includes removing a low-resistivity metal film, conductive layer, third insulating film and an upper part of the electrode layer in a gate electrode isolation region with a gate forming pattern serving as a mask, forming a protecting film so that the protecting film covers the low-resistivity metal film, conductive layer, third insulating film and upper surface of the electrode layer, removing the protecting film formed on the upper surface of the electrode layer located in the upper surface of the electrode layer in the gate electrode isolation region, removing the electrode layer in the gate electrode isolation region, and removing residue of the protecting film.

Abstract: Device isolation insulation layers passing through an insulation layer and a substrate, are formed, and a portion of them is removed. The insulation layer is removed. A gate oxide layer and a first conductive layer sequentially formed over the device isolation insulation layers, are isolated. Portions of the device isolation insulation layers are removed to increase an effective area of the first conductive layer. A laminated layer is formed, over the gate oxide layer and the first conductive layer that are isolated, and a portion of it is removed. A second conductive layer is formed over a remaining portion of the laminated layer, filling a gap created by removing the portion of the laminated layer. Predetermined portions of the second conductive layer are removed, thereby forming gate structures.

Abstract: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate. Therefore, a nonvolatile memory capable of miniaturization can be provided.

Abstract: A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.

Abstract: A memory transistor and a high breakdown voltage MOS transistor are easily formed on the same semiconductor substrate without changing the operational characteristics of the memory transistor. The process of forming the tunnel insulation film of the memory transistor and the process of forming the gate insulation film of the MOS transistor are performed separately. Concretely, an insulation film to be a part of the tunnel insulation film and a silicon nitride film are formed on the whole surface, and then the silicon nitride film in a MOS transistor formation region is selectively removed using a photoresist layer. Then, the MOS transistor formation region is selectively oxidized using the remaining silicon nitride film as an anti-oxidation mask to form the gate insulation film of the MOS transistor having a selected thickness.

Abstract: A thin film transistor includes a substrate, a crystallized semiconductor layer formed over the substrate having a channel region, low-density impurity regions and high-density impurity regions, a gate insulating layer formed on the crystallized semiconductor layer, a first gate electrode formed on the gate insulating layer having a width corresponding to the channel region, a second gate electrode formed on the first gate electrode and on the gate insulating layer such that the second gate electrode overlaps the low-density impurity regions and a source electrode and a drain electrode respectively contacting the high-density impurity regions.

Abstract: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Abstract: A split gate flash memory cell includes a substrate having a device isolation structure; a selective gate structure disposed on the substrate; an interlayer dielectric layer having an opening disposed on the substrate, wherein the opening exposes a portion of the selective gate structure, the substrate and the device isolation structure; a floating gate disposed in the opening and extended to cover a surface of the interlayer dielectric layer; a tunneling dielectric layer disposed between the floating gate and the selective gate structure; a gate dielectric layer disposed between the floating gate and the control gate; a source region disposed in the substrate on one side of the control gate that is not adjacent to the selective gate structure, and a drain region disposed in the substrate on one side of the selective gate that is not adjacent to the control gate.

Abstract: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

Abstract: A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates disposed on the substrate on opposite sides of the floating gate. A first etch process is performed to remove a portion of the field isolation film and thereby expose upper portions of the floating gates. Then, a second etch process is performed to knock off the edges of the floating gates. Thus, a large amount of space is secured between the floating gates for a dielectric film and a control gate.

Abstract: A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.

Abstract: A split-gate flash memory process for improving sharpness and height of a floating-gate tip has steps as follows. Using a dry etching process, a trench is formed in the first polysilicon layer through the pattern opening. An oxide layer is then deposited on the first polysilicon layer through a CVD process to fill the trench. Through a CMP process, portions of the oxide layer are removed to substantially planarize the trench-filled oxide layer as the first polysilicon layer. Using a dry etching process with the trench-filled oxide layer with a mask, the first polysilicon layer is patterned as a floating gate, and the corner edge of the floating gate has a polysilicon tip.

Abstract: A method of manufacturing a semiconductor memory device comprises the steps of: preparing a semiconductor substrate having a gate insulation film and a gate electrode, the gate insulation film being formed on a predetermined active region in the semiconductor substrate, and the gate electrode being formed on the gate insulation film; forming a first insulation film covering the gate electrode and at least a part of the semiconductor substrate; charging the first insulation film; and forming a second insulation film for charge storage on the first insulation film.

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract: A method of fabricating a nonvolatile memory cell includes providing a substrate with a trench, with a sidewall where a tunnel oxide layer and a floating gate are successively formed, forming a control gate in the trench, performing a high density plasma deposition process to form an HDP oxide layer on the top surface of control gate.