Heterojunction Gate Structure (epo) Patents (Class 257/E21.188)
  • Patent number: 8906758
    Abstract: The present invention may provide an integrated device, which may include a substrate having first and second regions, the first region spaced apart from the second region, a first heterojunction bipolar transistor (HBT) device formed on the first region of the substrate, the first HBT device having a first collector layer formed above the first region of the substrate, the first collector layer having a first collector thickness and a first collector doping level, and a second HBT device formed on the second region of the substrate, the second HBT device having a second collector layer formed above the second region of the substrate, the second collector layer having a second collector thickness and a second collector doping level, the second collector thickness substantially greater than the first collector thickness, the second collector doping level lower than the first collector doping level.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: December 9, 2014
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventor: Miguel E. Urteaga
  • Patent number: 7488638
    Abstract: A method for fabricating integrable PMOSFET semiconductor structures in a P-doped substrate which are distinguished by a high dielectric strength is provided. In order to fabricate the PMOSFET semiconductor structure, a mask is applied to a semiconductor substrate for the definition of a window delimited by a peripheral edge. An N-doped well is thereupon produced in the P-doped semiconductor substrate by means of high-voltage ion implantation through the window delimited by the mask, the edge zone of said N-doped well reaching as far as the surface of the semiconductor substrate. The individual regions for the source, drain and bulk of the PMOSFET semiconductor structure are then produced in the P-doped inner zone enclosed by the well. The P-doped inner zone forms the drift zone of the PMOSFET structure. Since the drift zone has the weak basic doping of the substrate, the PMOSFET has a high dielectric strength.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: February 10, 2009
    Assignee: PREMA Semiconductor GmbH
    Inventors: Hartmut Grutzediek, Joachim Scheerer
  • Patent number: 7297589
    Abstract: A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the subcollector region including depositing a material composition transition from a relatively larger bandgap material nearer the substrate to a relatively smaller bandgap material adjacent the collector; and the step of depositing the collector region including depositing a material composition transition from a relatively smaller bandgap material adjacent the subcollector to a relatively larger bandgap material adjacent the base.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: November 20, 2007
    Assignee: The Board of Trustees of The University of Illinois
    Inventor: Milton Feng
  • Patent number: 7271422
    Abstract: In a semiconductor optical device, a first conductive type semiconductor region includes first and second semiconductor portions. The first and second semiconductor portions are made of nitride mixed semiconductor crystal. This first semiconductor portion has a first region and a second region. The second semiconductor portion is provided on the first region of the first semiconductor portion. A second conductive type semiconductor region is made of nitride mixed semiconductor crystal. The second conductive type semiconductor region includes a first region and a second region. This second region of the first semiconductor portion of the first conductive type semiconductor region and the second region of the second conductive type semiconductor region constitute a pn junction. The sides of the second semiconductor portion of the first conductive type semiconductor region and the second region of the second conductive type semiconductor region constitute a pn junction.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: September 18, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Jun-ichi Hashimoto, Tsukuru Katsuyama