Abstract: A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

Abstract: A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.

Abstract: Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

Abstract: A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.

Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.

Abstract: The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end

Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.

Abstract: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Abstract: A semiconductor memory device includes a semiconductor substrate having a projection, an upper end portion of the projection being curved, a first element isolation insulating film formed on the substrate surface at the root of the projection, having an upper surface lower than an upper surface of the projection, a second element isolation insulating film formed in the projection, a gate insulating film formed on the projection, and including a charge storage layer, and a gate electrode formed on the gate insulating film. A height of a first portion where the gate electrode is in contact with the gate insulating film above the upper surface of the first element isolation insulating film is smaller than that of a second portion where the gate electrode is in contact with the gate insulating film above an upper end of the second element isolation insulating film.

Abstract: A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

Abstract: Provided are a non-volatile memory device that may expand to a stacked structure and may be more easily highly integrated and an economical method of fabricating the non-volatile memory device. The non-volatile memory device may include at least one semiconductor column. At least one first control gate electrode may be arranged on a first side of the at least one semiconductor column. At least one second control gate electrode may be arranged on a second side of the at least one semiconductor column. A first charge storage layer may be between the at least one first control gate electrode and the at least one semiconductor column. A second charge storage layer may be between the at least one second control gate electrode and the at least one semiconductor column.

Abstract: A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.

Abstract: Provided is a nonvolatile semiconductor memory device and a method of manufacturing the same. The nonvolatile semiconductor memory device may include a tunnel insulating layer formed on a semiconductor substrate, a charge trap layer including a dielectric layer doped with a transition metal formed on the tunnel insulating layer, a blocking insulating layer formed on the charge trap layer, and a gate electrode formed on the blocking insulating layer. The dielectric layer may be a high-k dielectric layer, for example, a HfO2 layer. Thus, the data retention characteristics of the nonvolatile semiconductor memory device may be improved because a deeper charge trap may be formed by doping the high-k dielectric layer with a transition metal.

Abstract: A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes.

Abstract: Provided may be a method of fabricating a flash memory device having metal nano particles. The method of manufacturing a flash memory device may include forming a metal oxide thin layer on a semiconductor substrate, forming a floating gate of an amorphous metal silicon oxide thin layer by performing a thermal treatment process on the semiconductor substrate where the metal oxide thin layer is formed, and forming metal nano particles in the floating gate by projecting an electron beam on the floating gate, the metal nano particles being surrounded by a silicon oxide layer.

Abstract: Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches.

Abstract: A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the GOX. A layer of bottom oxide (BOX) is grown on top of the silicon substrate and a conformal layer of top oxide (TOX) is grown along the bottom and the sidewalls of the polysilicon gate. Two charge trapping inserts are located beside the GOX and between the BOX and the TOX. The polysilicon gate needs to be at least partially over each of the two charge trapping inserts. The charge trapping inserts are made from a non-conductive charge trapping material. A method for fabricating such a device is also described.

Abstract: Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.

Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate. Related structures are also discussed.

Abstract: A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

Abstract: Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.

Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Abstract: A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.

Abstract: A method for preparing a multi-level flash memory device comprises forming a dielectric stack including a charge-trapping layer on a semiconductor substrate, forming an insulation structure having a depression on the charge-trapping layer, removing a portion of the charge-trapping layer from the depression such that the charge-trapping layer is segmented to form a plurality of storage nodes, forming a gate oxide layer isolating the storage nodes and forming a damascene gate including a polysilicon layer filling the depression.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.

Abstract: Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.

Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

Abstract: A non-volatile memory structure includes a substrate having two doped regions, a charge-trapping structure positioned substantially between the two doped regions, and a conductive structure positioned on the charge-trapping structure, wherein the charge-trapping structure includes a silicon-oxy-nitride layer and metallic nano-dots embedded in the silicon-oxy-nitride layer. The non-volatile memory structure formed by performing a first thermal oxidation process to form a high-k dielectric layer on a substrate, forming a metal-containing semiconductor layer including silicon or germanium on the high-k dielectric layer, forming a silicon layer on the metal-containing semiconductor layer, and performing a second thermal oxidation process to convert the metal-containing semiconductor layer to a silicon-oxy-nitride layer with embedded metallic nano-dots, wherein at least one of the first thermal oxidation process and the second thermal oxidation process is performed in a nitrogen-containing atmosphere.

Abstract: Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.

Abstract: Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.

Abstract: A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.

Abstract: A semiconductor device according to an embodiment of the present invention has a bit line and a word line. The device includes a substrate, a first gate insulation film formed on the substrate, a charge storage layer formed on the first gate insulation film, a second gate insulation film formed on the charge storage layer, and a gate electrode formed on the second gate insulation film, the width between side surfaces of the second gate insulation film in the bit line direction being smaller than the width between side surfaces of the gate electrode in the bit line direction.

Abstract: Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the nanoparticles are coordinated to hydrophobic ligands, and the first coordination complexes are dispersed within a non-polar solvent. While the first coordination complexes are within the non-polar solvent, the ligands are reacted with one or more reactants to convert the first coordination complexes into second coordination complexes that contain hydrophilic ligands. The second coordination complexes are then extracted from the non-polar solvent into water, to form a mixture of the second coordination complexes and the water. In some embodiments, the mixture may be dispersed across a semiconductor substrate to form a uniform distribution of the nanoparticles across the substrate. In some embodiments, the nanoparticles may then be incorporated into flash memory devices as charge-trapping centers.

Abstract: A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and the wordline includes an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed.

Abstract: Data storage device, comprising: a stack of layers formed by an alternation of first layers with a conductivity of less than approximately 0.01 (?·cm)?1 and second layers with a conductivity greater than approximately 1 (?·cm)?1, a plurality of columns disposed in the stack of layers, and passing through each layer in this stack. Each of the columns is formed by at least one portion of semiconductor material surrounded by least one electrical charge storage layer electrically insulated from the portion of semiconductor material and from the stack; and means of applying voltage to the terminals of the columns comprising a network of moving microspikes.

Abstract: A method of manufacturing a semiconductor device, comprises forming a gate insulating film on a surface of a semiconductor substrate, forming a first group of at least one strip-like gate electrode and a second group of strip-like gate electrodes on a surface of the gate insulating film, each strip-like gate electrode having a first face contacting the gate insulating film, a second face vertically extending from a long side of the first face and a third face curved and extending between the first and second faces, and a gap between the third faces of the adjacent gate electrode being narrower, at the surface of the gate insulating film, than a gap between the second faces of the adjacent gate electrode, and introducing dopant atoms into the surface of the semiconductor substrate through the gaps between the gate electrodes, thereby forming diffusion layers in the semiconductor substrate.

Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

Abstract: A method forms a nonvolatile memory device using a semiconductor substrate. A charge storage layer is formed overlying the semiconductor substrate and a layer of gate material is formed overlying the charge storage layer to form a control gate electrode. A protective layer overlies the layer of gate material. Dopants are implanted into the semiconductor substrate and are self-aligned to the control gate electrode on at least one side of the control gate electrode to form a source and a drain in the semiconductor substrate on opposing sides of the control gate electrode. The protective layer prevents the dopants from penetrating into the control gate electrode. The protective layer that overlies the layer of gate material is removed. Electrical contact is made to the control gate electrode, the source and the drain. In one form a select gate is also provided in the memory device.

Abstract: A non-volatile memory device includes a buffer oxide film on a substrate; a polysilicon layer on the buffer oxide film; a silicon oxy-nitride (SiON) layer on the polysilicon layer, a first insulator layer on the SiON layer, a nitride film on the first insulator, a second insulator layer on the nitride film, an electrode on the second insulator, and a source/drain in the polysilicon layer.

Abstract: The present invention relates to a method of fabricating a flash memory device. According to a method of fabricating a flash memory device in accordance with an aspect of the present invention, a semiconductor substrate over which a tunnel insulating layer and a first conductive layer are formed is provided. A first oxide layer is formed on the first conductive layer using a plasma oxidization process in a state where a back bias voltage is applied. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. A second conductive layer is formed on the second oxide layer.

Abstract: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

Abstract: A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.

Abstract: An electronic device can include a silicon nitride layer. In an embodiment, the silicon nitride layer can include boron, grains, or both. The silicon nitride layer may be used as part of a charge storage layer within a nonvolatile memory cell within the electronic device. In a particular embodiment, the boron within the silicon nitride layer may be no greater than approximately 9 atomic % of the layer. The boron can be incorporated into the silicon nitride layer as it is being formed. The layer can be formed using chemical vapor deposition, physical vapor deposition, another suitable formation process, or any combination thereof.

Abstract: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.

Abstract: A semiconductor device and a method of fabricating the same are provided. First, a first oxide layer and a nitride layer are formed on a base having a first region and a second region. Next, the nitride layer is oxidized. A part of nitride in the nitride layer moves to the first oxide layer and the base. An upper portion of the nitride layer is converted to an upper oxide layer. Then, the upper oxide layer, the nitride layer and the first oxide layer in the second region are removed. Thereon, a second oxide layer is grown on the base in the second region. Nitride in the second region moves to the second oxide layer.