Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, a plurality of static random access memory (SRAM) cells arranged in a second memory array, and a controller configured to access the first memory array and the second memory array with different access rate. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, a ferroelectric layer over the gate electrode, a first electrode over the gate electrode, and a second electrode over the first electrode. The ferroelectric layer is formed between the first and second electrodes.

Abstract: In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer.

Abstract: A method of producing a semiconductor device includes forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor having a specified operating temperature range. Forming each transistor cell includes forming a gate structure having a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and including a ferroelectric insulator. The method further includes doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

Abstract: A read-disturb-based read temperature information utilization system includes a read-disturb-based read temperature information utilization subsystem coupled to a storage subsystem including storage devices that each generate local read-disturb-based read temperature information associated with that storage device. The read-disturb-based read temperature information utilization subsystem retrieves at least some of the local read-disturb-based read temperature information generated by each storage device and a number of reads associated with that storage device and, based on the number of reads associated with each of the storage devices, normalizes the at least some of the local read-disturb-based read temperature information retrieved from each of the storage devices to generate normalized local read-disturb-based read temperature information for each of the storage devices.

Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. The first memory array and the second memory array share the same bus. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, and a ferroelectric layer over the gate electrode.

Abstract: Ferroelectric structures, including a ferroelectric field effect transistors (FeFETs), and methods of making the same are disclosed which have improved ferroelectric properties and device performance. A FeFET device including a ferroelectric material gate dielectric layer and a metal oxide semiconductor channel layer is disclosed having improved ferroelectric characteristics, such as increased remnant polarization, low defects, and increased carrier mobility for improved device performance.

Abstract: A selector device may include a first electrode, a tunneling layer, and a ferroelectric layer. The tunneling layer may be between the first electrode and the ferroelectric layer, and a thickness and dielectric constant of the tunneling layer relative to a thickness and dielectric constant of the ferroelectric layer may cause a depolarizing electric field induced in the first tunneling layer to be greater than or approximately equal to an electric field induced in an opposite direction by ferroelectric dipoles in the ferroelectric layer when a voltage is applied across the selector device. The device may also include a second electrode, and the ferroelectric layer may be between the tunneling layer and the second electrode. A seconding layer may also be added between the ferroelectric layer and the second electrode for bipolar selectors.

Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. This ferroelectric material may be of the composition HFxZr1-xO2. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). A ferroelectric layer formed with chlorine-free precursors has no chlorine residue. The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Abstract: Various aspects relate to a memory cell including: a field-effect transistor memory structure, wherein a source/drain current through the field-effect transistor memory structure is a function of a gate voltage supplied to a gate of the field-effect transistor memory structure and a memory state in which the field-effect transistor memory structure is residing in; and an access device coupled to the gate of the field-effect transistor memory structure, wherein the access device is configured to control a voltage present at the gate of the field-effect transistor memory structure.

Abstract: A selector device may include a first electrode, a tunneling layer, and a ferroelectric layer. The tunneling layer may be between the first electrode and the ferroelectric layer, and a thickness and dielectric constant of the tunneling layer relative to a thickness and dielectric constant of the ferroelectric layer may cause a depolarizing electric field induced in the first tunneling layer to be greater than or approximately equal to an electric field induced in an opposite direction by ferroelectric dipoles in the ferroelectric layer when a voltage is applied across the selector device. The device may also include a second electrode, and the ferroelectric layer may be between the tunneling layer and the second electrode. A second ing layer may also be added between the ferroelectric layer and the second electrode for bipolar selectors.

Abstract: A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.

Abstract: A memory device has an SRAM that stores a logic state. A first MTJ has two terminals. A second one of the terminals is coupled to a storing node. A first terminal of a second MTJ is coupled to the storing node. The first and second MTJs are programmed to a first resistance by flowing current from the first second terminals and to a second resistance by flowing current from the second to first terminal. A storing circuit is coupled to the storing node, the SRAM cell, and a non-volatile word line. The storing circuit couples the logic state of the SRAM cell to the storing node during a store mode. The logic state of the SRAM cell is stored in the first and second MTJs by applying a storing voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity then a second polarity.

Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL and a portion of the magnetoresistive stack. The method can further include depositing a photoresist layer on the hard mask before the first etching process and removing the photoresist layer from the hard mask following the first etching process. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.

Abstract: A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k dielectric layer, the first high-k dielectric layer having a first thickness and comprising hafnium. The second circuit element comprises a second electrode structure that includes a second high-k dielectric layer having a ferroelectric behavior, wherein the second high-k dielectric layer has a second thickness and comprises hafnium, and wherein the second thickness is greater than the first thickness.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. In addition, the insertion layer is made of M1Ox, and M1 is a metal, O is oxygen, and x is a value greater than 4.

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

Abstract: Disclosed herein is a thermally-assisted magnetic tunnel junction structure including a thermal barrier. The thermal barrier is composed of a cermet material in a disordered form such that the thermal barrier has a low thermal conductivity and a high electric conductivity. Compared to conventional magnetic tunnel junction structures, the disclosed structure can be switched faster and has improved compatibility with standard semiconductor fabrication processes.

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: A mechanism is provided for a spin torque transfer random access memory device. A tunnel barrier is disposed on a reference layer, and a free layer is disposed on the tunnel barrier. The free layer includes an iron layer as a top part of the free layer. A metal oxide layer is disposed on the iron layer, and a cap layer is disposed on the metal oxide layer.

Abstract: A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes.

Abstract: In certain embodiments, a field effect transistor (FET) can include a substrate, a source electrode, a drain electrode, a ferroelectric material layer, a first gate electrode, and a second gate electrode to maintain an optimal polarization state of the ferroelectric material layer. In other embodiments, a FET can include a film, first and second gates on the film, a ferroelectric material layer covering the film and gates, an insulating layer substantially covering the ferroelectric material layer, a source and a drain on the insulating layer, and a pentacene layer.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a ferroelectric film and an upper electrode, and an interlayer insulation film formed over the oxidation resistance film so as to cover the ferroelectric capacitor, wherein there are formed, in the interlayer insulation film, a first via-plug in a first contact hole exposing the first electrode and a second via-plug in a second contact hole exposing the lower electrode, and wherein there is formed another conductive plug in the interlayer insulation film in an opening exposing the oxidation resistant film.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.

Abstract: A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second electrode apart at a predetermined interval from the word line perpendicular electrode to have a column type, where a ferroelectric material is filled in a space where the first electrode are separated from the second electrode. The serial PN diode switch, which is connected between a bit line and the ferroelectric capacitor, selectively switches a current direction between the bit line and the ferroelectric capacitor depending on voltage change between the bit line and the ferroelectric capacitor.

Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared by the following steps. A single-crystalline MgO (001) substrate 11 is prepared. An epitaxial Fe(001) lower electrode (a first electrode) 17 with the thickness of 50 nm is grown on a MgO(001) seed layer 15 at room temperature, followed by annealing under ultrahigh vacuum (2×10?8 Pa) and at 350° C. A MgO(001) barrier layer 21 with the thickness of 2 nm is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) with the thickness of 10 nm is then formed on the MgO(001) barrier layer 21 at room temperature. This is successively followed by the deposition of a Co layer 21 with the thickness of 10 nm on the Fe(001) upper electrode (the second electrode) 23.

Abstract: A method for manufacturing an integrated circuit including a ferroelectric memory cell is disclosed. One embodiment of the method includes: forming a amorphous oxide layer over a carrier, the amorphous layer including: O and any of the group of: Hf, Zr and (Hf,Zr), forming a covering layer on the amorphous layer, and heating the amorphous layer up to a temperature above its crystallization temperature to at least partly alter its crystal state from amorphous to crystalline, resulting in a crystallized oxide layer.

Abstract: According to the present invention, there is provided a method for manufacturing a semiconductor device, including the steps of forming an insulating film on a silicon substrate, forming a first conductive film on the insulating film, forming an aluminum crystal layer on the first conductive film, forming a ferroelectric film containing Pb(ZrxTi1-x)O3 (where 0?x?1) on the aluminum crystal layer, forming a second conductive film on the ferroelectric film, and patterning the first conductive film, the ferroelectric film, and the second conductive film to form a capacitor including a lower electrode, a capacitor dielectric film, and an upper electrode which are laminated sequentially.

Abstract: A ferroelectric capacitor and a method of manufacturing the same are provided, wherein the ferroelectric capacitor of a semiconductor device, which sequentially includes a lower electrode, a ferroelectric layer, and an upper electrode on a conductive layer connected to a transistor formed on a semiconductor substrate, includes an oxidation preventing layer between the conductive layer and the lower electrode. The oxidation preventing layer prevents the conductive layer from being oxidized during high-temperature heat treatment of the ferroelectric layer. Accordingly, the oxidation resistivity of the interfaces of the conductive layer, used as a storage node, and the lower electrode, which faces the conductive layer, increases, so a temperature at which a ferroelectric thin layer is formed can be also increased. Consequently, a ferroelectric thin layer having excellent characteristics may be obtained.

Abstract: A ferroelectric device employs ferroelectric electrodes as local interconnect(s). One or more circuit features are formed within or on a semiconductor body. A first dielectric layer is formed over the semiconductor body. Lower contacts are formed within the first dielectric layer. A bottom electrode is formed over the first dielectric layer and on the lower contacts. A ferroelectric layer is formed on the bottom electrode. A top electrode is formed on the ferroelectric layer. A second dielectric layer is formed over the first dielectric layer. Upper contacts are formed within the second dielectric layer and in contact with the top electrode. Conductive features are formed on the upper contacts.

Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.

Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.

Abstract: A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second electrode apart at a predetermined interval from the word line perpendicular electrode to have a column type, where a ferroelectric material is filled in a space where the first electrode are separated from the second electrode. The serial PN diode switch, which is connected between a bit line and the ferroelectric capacitor, selectively switches a current direction between the bit line and the ferroelectric capacitor depending on voltage change between the bit line and the ferroelectric capacitor.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode including metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.

Abstract: In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

Abstract: In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film.

Abstract: A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20. of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: A method for improving signal levels between capacitively-coupled chips in proximity communication (PxC) includes depositing a high permittivity dielectric material layer over a signal pad of a first chip, and placing a second chip in close proximity to the first chip such that faces of the signal pads align to enable for capacitive signal coupling. The high permittivity dielectric material layer that fills at least a portion of a gap between the first chip and the second chip, and improves capacitive coupling between signal pads of the first chip and the second chip by providing for an increased permittivity in the gap between the first chip and the second chip. The increased permittivity ensures that electric fields are substantially confined to a space between the signal pad of the first chip and the signal pad of the second chip.

Abstract: Ferroelectric structures and methods of making the structures are presented. The ferroelectric structures can include an electrode in contact with a ferroelectric thin film. The contact can be arranged so that a portion of the atoms of the ferroelectric thin film are in contact with at least a portion of the atoms of the electrode. The electrode can be made of metal, a metal alloy, or a semiconducting material. A second electrode can be used and placed in contact with the ferroelectric thin film. Methods of making and using the ferroelectric structures are also presented.

Abstract: MgO tunnel barriers are formed by depositing a thin layer of Mg on a suitable underlayer, and then directing oxygen and additional Mg towards the Mg layer. The oxygen reacts with the additional Mg and the Mg in the Mg layer to form a MgO tunnel barrier that enjoys excellent tunneling characteristics. The MgO tunnel barriers so formed may be used in magnetic tunnel junctions having tunneling magnetoresistance (TMR) values of greater than 100%. The highest TMR values are observed for junctions that have been annealed and that have a (100) crystallographic orientation.

Abstract: A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.

Abstract: Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, the piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.

Abstract: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.

Abstract: An interlayer insulating film (14) covering a ferroelectric capacitor is formed and a contact hole (19) reaching a top electrode (11a) is formed in the interlayer insulating film (14). An Al wiring (17) connected to the top electrode (11a) via the contact hole (19) is formed on the interlayer insulating film (14). A planar shape of the contact hole (19) is an ellipse.

Abstract: A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrOx film containing crystallized small crystals when formed is formed on the ferroelectric film first, and then an IrOx film containing columnar crystals is formed.

Abstract: A method of manufacturing a semiconductor device including forming a lower electrode over a substrate, increasing the temperature of the substrate with the lower electrode to a predetermined temperature under mixture gas atmosphere of inert gas and oxygen gas, forming a dielectric film on the lower electrode by using an organic metal raw material after the temperature reaches the predetermined temperature, and forming an upper electrode on the dielectric film.