Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, memristor devices. In one aspect, a memristor device comprises an electrode (301,303) and an alloy electrode (502,602). The device also includes an active region (510,610) sandwiched between the electrode and the alloy electrode. The alloy electrode forms dopants in a sub-region of the active region adjacent to the alloy electrode. The active region can be operated by selectively positioning the dopants within the active region to control the flow of charge carriers between the electrode and the alloy electrode.

Abstract: A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.

Abstract: A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance.

Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

Abstract: A memristor includes a first electrode of a nanoscale width; a second electrode of a nanoscale width; and an active region disposed between the first and second electrodes. The active region has a both a non-conducting portion and a source of dopants portion induced by electric field. The non-conducting portion comprises an electronically semiconducting or nominally insulating material and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field. The non-conducting portion is in contact with the first electrode and the source of dopants portion is in contact with the second electrode. The second electrode comprises a metal reservoir for the dopants. A crossbar array comprising a plurality of the nanoscale switching devices is also provided. A process for making at least one nanoscale switching device is further provided.

Abstract: The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel.

Abstract: Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.

Abstract: Ion Implantation is used to form the memristor material and electrode structure with memristance. First, numerous electron-rich element atoms are implanted into a layer made of transition metal or non-metal. Then, a treating process (such as annealing) is proceeded to expel some electron-rich element atoms away the layer. After that, some electron-rich element vacancy rich regions are formed inside the layer, and then a memristor material is formed. Significantly, the usage of ion implantation can precisely control and flexibly adjust the distribution of the implanted atoms, and then both the amount and distribution of these depleted regions can be effectively adjusted. Hence, the quality of the memristor material is improved.

Abstract: A method of processing a nonvolatile memory device includes forming a first electrode, depositing a layer of sol-gel solution on the first electrode, hydrolyzing the layer of sol-gel solution to form a layer of variable electric resistance material, and forming a second electrode on the layer of variable electric resistance material.

Abstract: Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.

Abstract: A memory cell for use in an integrated circuit comprises a read transistor and a gated diode. The read transistor has a source terminal. The gated diode has a gate terminal in signal communication with the read transistor. A variable source voltage acts on the source terminal of the read transistor when the memory cell is in operation. The variable source voltage is temporarily altered when the memory cell is read. For example, the source voltage may be reduced when the read transistor is implemented using an N-type transistor and increased when the read transistor is implemented using P-type transistor. This acts to impart the memory cell with faster read speed, higher read margin, and lower standby current.

Abstract: An integrated circuit includes a field plated resistor having enhanced area thereover for routing metal conductors, formed in the same layer of metal as forms contacts to the resistor, is fabricated by a sequence of processing steps. A resistor having a resistor body and a contact region at each end thereof is formed in an active region of a semiconductor substrate. A first layer of insulative material is formed over the resistor and a window is created through the first layer of insulative material to the resistor body to form a first contact region. A layer of polysilicon is formed over the first insulative layer to define a field plate, the polysilicon field plate being contiguous with the first contact region of the resistor and extending over the resistor body to substantially to the other contact region, as layout, design, and fabrication rules permit. A second insulative layer is formed over the polysilicon layer.

Abstract: A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which lie within the trenches are doped by means of a drive-in. In one embodiment, the semiconductor structure is patterned in planar regions outside the trenches and selectively doped by an implantation process.

Abstract: A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.