Device Comprising One Or Two Electrodes, E.g., Diode, Resistor Or Capacitor With Pn Or Schottky Junctions (epo) Patents (Class 257/E21.351)
  • Patent number: 9773925
    Abstract: A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: September 26, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 9753002
    Abstract: A humidity sensor and a method of manufacturing the same are provided where voids are formed within interconnects configured to facilitate the operation of the device and a humidity sensing material is deposited within the voids to detect the humidity. The accuracy with respect to the measurement of the humidity sensor is improved and manufacturing costs are lowered. The humidity sensor includes a substrate, a first interlayer insulating layer disposed on the substrate, first and second metal electrodes disposed adjacent to each other on the first interlayer insulating layer, an etch stop layer covering the first interlayer insulating layer and the first and second metal electrodes, a second interlayer insulating layer disposed on the first etch stop layer, voids formed within the second interlayer insulating layer, and a humidity sensing material deposited in the voids.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: September 5, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Francois Hebert, Ihl Hyun Cho
  • Patent number: 9041120
    Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Stephan Voss, Peter Tuerkes, Holger Huesken
  • Patent number: 9018060
    Abstract: A variable capacitance sensor includes a first conductive electrode comprising electrically interconnected first conductive sheets; a second conductive electrode comprising electrically interconnected second conductive sheets, wherein the first conductive sheets are at least partially interleaved with the second conductive sheets, and wherein the second conductive electrode is electrically insulated from the first conductive electrode; and microporous dielectric material at least partially disposed between and contacting the first conductive sheets and the second conductive sheets. A method of making a variable capacitance sensor by replacing ceramic in a ceramic capacitor with a microporous material is also disclosed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: April 28, 2015
    Assignee: 3M Innovative Properties Company
    Inventors: Stefan H. Gryska, Michael C. Palazzotto
  • Patent number: 8975633
    Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
  • Patent number: 8969892
    Abstract: Disclosed is a light emitting structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer disposed on between the first and second semiconductor layers, a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer. The first semiconductor layer is formed, at an edge portion thereof, with a hole, in which a portion of the first electrode is arranged.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: March 3, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: WooSik Lim, SungKyoon Kim, MinGyu Na, SungHo Choo, MyeongSoo Kim, HeeYoung Beom
  • Patent number: 8896085
    Abstract: A semiconductor light-emitting element manufacturing method including: a first step in which a first n-type semiconductor layer is laminated onto a substrate in a first organometallic chemical vapor deposition apparatus; and a second step in which a regrowth layer, a second n-type semiconductor layer, an active layer, and a p-type semiconductor layer are sequentially laminated onto the aforementioned first n-type semiconductor layer in a second organometallic chemical vapor deposition apparatus.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: November 25, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Hiromitsu Sakai
  • Patent number: 8853790
    Abstract: An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8765569
    Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: July 1, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Wim Deweerd, Hiroyuki Ode
  • Patent number: 8728878
    Abstract: A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: May 20, 2014
    Assignee: PFC Device Corp.
    Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
  • Patent number: 8716745
    Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 6, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8703573
    Abstract: A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other, forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Dong-Hyun Kim, Kyung-Min Chung, Dong-Hyun Im
  • Patent number: 8669623
    Abstract: A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: March 11, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Christopher Lawrence Rexer
  • Patent number: 8587094
    Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisao Kawasaki
  • Publication number: 20130285112
    Abstract: An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jam-Wem LEE, Yi-Feng CHANG
  • Patent number: 8569819
    Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ??cm. Advantageously, the electrode layers are conductive molybdenum oxide.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: October 29, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Hiroyuki Ode
  • Patent number: 8563388
    Abstract: A method for producing a plurality of integrated semiconductor components on a carrier, in which an active basic structure is introduced into the carrier in a continuous fashion at least across a portion of the boundaries of the semiconductor components to be created. The regions of the semiconductor components on the carrier are defined, and a covering layer is applied to the carrier in the region of each semiconductor component with the aid of a mask. The carrier is severed to form the individual semiconductor components at the boundaries thereof.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: October 22, 2013
    Assignee: Semikron Elektronik GmbH & Co., KG
    Inventor: Sven Berberich
  • Patent number: 8530953
    Abstract: A transistor power switch device comprising an array of vertical transistor elements for carrying current between the first and second faces of a semiconductor body and a vertical avalanche diode electrically in parallel with the array of vertical transistors. The array of transistor elements includes at the first face an array of source regions of a first semiconductor type, at least one p region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the p region, and a conductive layer contacting the source regions and insulated from the control electrode.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: September 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean Michel Reynes, Beatrice Bernoux, Rene Escoffier, Pierre Jalbaud, Ivana Deram
  • Patent number: 8507978
    Abstract: An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: August 13, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Madhur Bobde, Lingpeng Guan
  • Patent number: 8497154
    Abstract: A method for manufacturing a solar cell system includes the following steps. First, a number of P-N junction cell preforms are provided. The number of the P-N junction cell preforms is M. The M P-N junction cell preforms is named from a first P-N junction cell preform to a Mth P-N junction cell preform. Second, the M P-N junction cell preforms are arranged along a straight line. Third, an inner electrode preform is formed between each two adjacent P-N junction cell preforms, wherein at least one inner electrode is a carbon nanotube array. Axial directions of the carbon nanotubes in the carbon nanotube array are parallel to the straight line.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: July 30, 2013
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8492255
    Abstract: A Schottky diode with a small footprint and a high-current carrying ability is fabricated by forming an opening that extends into an n-type semiconductor material. The opening is then lined with a metallic material such as platinum. The metallic material is then heated to form a salicide region where the metallic material touches the n-type semiconductor material.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: July 23, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon D. Haynie, Ann Gabrys
  • Patent number: 8492254
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: July 23, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tomonori Mizushima
  • Patent number: 8486780
    Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode layers are conductive molybdenum oxide.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: July 16, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Hiroyuki Ode
  • Patent number: 8476672
    Abstract: The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.
    Type: Grant
    Filed: April 2, 2011
    Date of Patent: July 2, 2013
    Assignee: Peking University
    Inventors: Ru Huang, Lijie Zhang
  • Patent number: 8435873
    Abstract: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: May 7, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Vladimir Frank Drobny
  • Patent number: 8410534
    Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8399948
    Abstract: Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a first conductive type semiconductor layer; an active layer including a barrier layer and a well layer alternately disposed on the first conductive type semiconductor layer; and a second conductive type semiconductor layer on the active layer. At least one well layer includes an indium cluster having a density of 1E11/cm2 or more.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 19, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Ho Sang Yoon, Sang Kyun Shim
  • Patent number: 8395200
    Abstract: A method for manufacturing a capacitor on an integrated circuit includes providing an inter-metal dielectric layer on a substrate, a bottom layer having a first and second portions, a first insulating layer having via plug openings on the bottom layer, and via plugs disposed in the via plug openings. The via plugs include a first and second via plugs and are electrically coupled to the first portion of the bottom layer. The method further includes providing a capacitor layer having a first barrier metal layer coupled to the first via plug. The capacitor layer also has a capacitor dielectric layer overlying the first barrier metal layer and a second barrier metal overlying the capacitor dielectric layer. The method further includes defining a first and second capacitor layer portions. The first capacitor layer portion has two opposite sides and spacers disposed on their surface.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Zhen Chen, Yung Feng Lin, Lin Huang
  • Patent number: 8314474
    Abstract: Various on-chip capacitors and methods of making the same are disclosed. In one aspect, a method of manufacturing a capacitor is provided that includes forming a first conductor structure on a semiconductor chip and forming a passivation structure on the first conductor structure. An under bump metallization structure is formed on the passivation structure. The under bump metallization structure overlaps at least a portion of the first conductor structure to provide a capacitor.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: November 20, 2012
    Assignee: ATI Technologies ULC
    Inventors: Neil McLellan, Fei Guo, Daniel Chung, Terence Cheung
  • Publication number: 20120161280
    Abstract: A capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the first metal plate. A portion of the first metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A second metal plate is disposed on and conformal with the second dielectric layer. A portion of the second metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A third dielectric layer is disposed above the first metal plate, the second dielectric layer, and the second metal plate, and disposed between the first metal plate and the second dielectric layer and between the second metal plate and the second dielectric layer.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventor: Nick Lindert
  • Patent number: 8129814
    Abstract: An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the cobalt silicide region. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation. An n+-type contact region is laterally separated by the p-type region from the first silicide region and a second cobalt silicide region is formed in the n-type contact region. The silicided regions are defined by openings in a silicon blocking dielectric layer. Dielectric material is left over the p-type region. The p-type region may be formed simultaneously with source/drain regions of a PMOS transistor.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Prakash Pendharkar, Eugen Pompiliu Mindricelu
  • Patent number: 8129772
    Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Publication number: 20120018775
    Abstract: The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.
    Type: Application
    Filed: April 2, 2011
    Publication date: January 26, 2012
    Applicant: PEKING UNIVERSITY
    Inventors: Ru Huang, Lijie Zhang
  • Patent number: 8076195
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Mike Violette
  • Patent number: 8067277
    Abstract: An active matrix pixel device is provided, for example an electroluminescent display device, the device comprising circuitry supported by a substrate and including a polysilicon TFT (10) and an amorphous silicon thin film PIN diode (12). Polysilicon islands are formed before an amorphous silicon layer is deposited for the PIN diode. This avoids the exposure of the amorphous silicon to high temperature processing. The TFT comprises doped source/drain regions (16a,17a), one of which (17a) may also provide the n-type or p-type doped region for the diode. Advantageously, the requirement to provide a separate doped region for the photodiode is removed, thereby saving processing costs. A second TFT (10b) having a doped source/drain region (16b,17b) of the opposite conductivity type may provide the other doped region (16b) for the diode, wherein the intrinsic region (25) is disposed laterally between the two TFTs, overlying each of the respective polysilicon islands.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: November 29, 2011
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Steven C. Deane
  • Patent number: 8039328
    Abstract: A process for forming a trench Schottky barrier device includes the forming of an oxide layer within the trenches in the surface of a silicon wafer, and then depositing a full continuous metal barrier layer over the full upper surface of the wafer including the trench interiors and the mesas between trenches with a barrier contact made to the mesas only. Palladium, titanium or any conventional barrier metal can be used.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: October 18, 2011
    Assignee: International Rectifier Corporation
    Inventors: Giovanni Richieri, Rossano Carta
  • Patent number: 7989244
    Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: August 2, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Kyoung-kook Kim, Kwang-ki Choi, June-o Song, Suk-ho Yoon, Kwang-hyeon Baik, Hyun-soo Kim
  • Patent number: 7985615
    Abstract: The present invention relates to embodiments of TPV cell structures based on carbon nanotube and nanowire materials. One embodiment according to the present invention is a p-n junction carbon nanotube/nanowire TPV cell, which is formed by p-n junction wires. A second embodiment according to the present invention is a carbon nanotube/nanowire used as a p-type (or n-type), and using bulk material as the other complementary type to a form p-n junction TPV cell. A third embodiment according to the present invention uses a controllable Schottky barrier height between a one-dimensional nanowire and a metal contact to form the built-in potential of the TPV cells.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: July 26, 2011
    Assignee: The Regents of the University of California
    Inventors: Fei Liu, Ma Siguang, Kang L. Wang
  • Patent number: 7982239
    Abstract: In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: July 19, 2011
    Assignee: Northrop Grumman Corporation
    Inventors: Ty R. McNutt, Eric J. Stewart, Rowland C. Clarke, Ranbir Singh, Stephen Van Campen, Marc E. Sherwin
  • Publication number: 20110114146
    Abstract: A uniwafer device for thermoelectric applications includes one or more first thermoelectric elements and one or more second thermoelectric elements comprising respectively a first and second patterned portion of a substrate material. Each first/second thermoelectric element is configured to be functionalized as an n-/p-type semiconductor with a thermoelectric figure of merit ZT greater than 0.2. The second patterned portion is separated from the first patterned portion by an intermediate region functionalized partially for thermal isolation and/or partially for electric interconnecting. The one or more first thermoelectric elements and the one or more second thermoelectric elements are spatially configured to allow formation of a first contact region and a second contact region respectively connecting to each of the one or more first thermoelectric elements and/or each of the one or more second thermoelectric elements to form a continuous electric circuit.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 19, 2011
    Applicant: Alphabet Energy, Inc.
    Inventor: Matthew L. Scullin
  • Patent number: 7943472
    Abstract: Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating p-type region encircles each anode of a CoSi2 Schottky diode comprising of one or more CoSi2 anodes. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Eugen Pompiliu Mindricelu
  • Patent number: 7939415
    Abstract: By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the lower portion of the substrate contact may be formed concurrently with the fabrication of trench capacitors, complex patterning steps may be avoided which may otherwise have to be introduced when the substrate contacts are to be formed separately from contact elements connecting to the device level.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: May 10, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ralf Richter
  • Patent number: 7915658
    Abstract: A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: March 29, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mario M. Pellela, Donggang D. Wu, James F. Buller
  • Patent number: 7888229
    Abstract: The present invention relates to methods of manufacturing an electrochemical energy storage device, such as a hybrid capacitor. The method comprises saturating a porous electrically conductive material in a solution comprising an organic solvent and a metal complex or a mixture of metal complexes; assembling a capacitor comprising the positive electrode made of porous electrically conductive material saturated with a metal complex, a negative electrode, and a separator in a casing; introducing the electrolyte solution into the casing; sealing the casing; and subsequent charge-discharge cycling of the capacitor. The charge-discharge cycling deposits a layer of an energy-accumulating redox polymer on the positive electrode. The electrolyte solution for filling the hybrid capacitor contains an organic solvent, a metal complex, and substances soluble to a concentration of no less than 0.01 mol/L and containing ions that are electrochemically inactive within the range of potentials between ?3.0 V to +1.5 V.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: February 15, 2011
    Assignee: GEN 3 Partners, Inc.
    Inventors: Irina Chepurnaya, Alexander Timonov, Sergey Logvinov, Sam Kogan
  • Patent number: 7875525
    Abstract: A stack-type capacitor includes a lower electrode, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, wherein the lower electrode includes a first metal layer having a cylindrical shape and a second metal layer filled in the first metal layer. In the capacitor, an amount of oxygen included in the lower electrode is decreased to suppress oxidation of a TiN layer. Thus, a stable stack-type capacitor may be formed, which increases greatly the performance of highly integrated DRAMs.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Hion-suck Baik, Soon-ho Kim, Jae-young Choi
  • Patent number: 7863172
    Abstract: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n? doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n? doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: January 4, 2011
    Assignee: Power Integrations, Inc.
    Inventors: TingGang Zhu, Bryan S. Shelton, Marek K. Pabisz, Mark Gottfried, Linlin Liu, Milan Pophristic, Michael Murphy, Richard A. Stall
  • Publication number: 20100301450
    Abstract: A semiconductor device is made by forming a smooth conductive layer over a substrate. A first insulating layer is formed over a first surface of the smooth conductive layer. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The substrate is removed. A second conductive layer is formed over a second surface of the smooth conductive layer opposite the first surface of the smooth conductive layer. A third insulating layer is formed over the second conductive layer. The second conductive layer, smooth conductive layer, first insulating layer, and first conductive layer constitute a MIM capacitor. A portion of the second conductive layer includes an inductor. The smooth conductive layer has a smooth surface to reduce particles and hill-locks which decreases ESR, increases Q factor, and increases ESD of the MIM capacitor.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 2, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventor: Yaojian Lin
  • Patent number: 7838349
    Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: November 23, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
  • Publication number: 20100279483
    Abstract: A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.
    Type: Application
    Filed: July 13, 2010
    Publication date: November 4, 2010
    Inventors: David S. Collins, Jeffrey B. Johnson, Xuefeng Liu, Bradley A. Orner, Robert M. Rassel, David C. Sheridan
  • Patent number: RE42283
    Abstract: A TFT liquid crystal display device is disclosed, which includes two substrates and a liquid crystal layer provided in between the substrates, one substrate having a surface providing with a plurality of data signal lines, a plurality of scan lines, a plurality of pixel electrodes, and a plurality of functional components having source electrode, gate electrodes and drain electrodes. Moreover, the projection of one of the signal electrode and the drain electrode on the gate electrode having at least one bridging zone and one conducting zone. The width of the bridging zone in the direction in parallel to one side of the gate electrode is smaller than the width of the conducting zone in the direction in parallel to the side of the gate electrode.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: April 12, 2011
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Hung-Jen Chu, Ming-Hsuan Chang, Chien-Kuo Ho, Nai-Jen Hsiao