Capacitor With Pn - Or Schottky Junction, E.g., Varactor (epo) Patents (Class 257/E21.364)
  • Patent number: 8796809
    Abstract: A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: August 5, 2014
    Assignee: Cree, Inc.
    Inventor: Christopher Harris
  • Patent number: 8735257
    Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen
  • Patent number: 8716126
    Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Peter Baars, Frank Feustel
  • Patent number: 8669623
    Abstract: A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: March 11, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Christopher Lawrence Rexer
  • Publication number: 20130292683
    Abstract: An electronic device comprising a substrate; a pair of stacks of polar semiconductor materials which create a charge by spontaneous and/or piezoelectric polarization; one of the pair of stacks having a spontaneous and/or piezoelectric polarity which is in a direction opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced. A method of substantially eliminating the bias required to offset polarization charges in an electronic device having a heterobarrier comprising providing a substrate; growing at least one pair of stacks of semiconductor materials; one of the pair of stacks having a spontaneous and/or piezoelectric polarity which is opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced to substantially eliminate the need for a voltage bias.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Applicant: U.S. Government as represented by the Secretary of the Army
    Inventor: PANKAJ B. SHAH
  • Publication number: 20130200494
    Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.
    Type: Application
    Filed: February 5, 2012
    Publication date: August 8, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Zhiying CHEN, Jianping ZHAO, Lee CHEN, Merritt FUNK, Radha SUNDARARAJAN
  • Patent number: 8492823
    Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventor: Edward J. Nowak
  • Patent number: 8450832
    Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Manju Sarkar, Purakh Raj Verma
  • Patent number: 8450827
    Abstract: Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen
  • Publication number: 20130113081
    Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 9, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: ZHIHONG CHEN, SHU-JEN HAN, SIYURANGA O. KOSWATTA, ALBERTO VALDES GARCIA
  • Publication number: 20130100090
    Abstract: This disclosure provides systems, methods and apparatus for electromechanical systems variable capacitance devices. In one aspect, an electromechanical systems variable capacitance device includes a substrate with a first metal layer including a first bias electrode overlying the substrate. A member suspended above the first metal layer includes a dielectric beam and a second metal layer including a first radio frequency electrode and a ground electrode. The member and the first metal layer define a first air gap. A third metal layer over the member includes a second bias electrode, and the third metal layer and the member define a second air gap. The member includes a plane of symmetry substantially parallel a plane containing the first bias electrode.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Daniel FELNHOFER, Wenyue ZHANG, Je-Hsuing LAN
  • Publication number: 20130049646
    Abstract: An energy conversion device, and methods of manufacturing and operating the same. The energy conversion device includes: a monolithic single-crystal silicon layer that includes a plurality of doping regions; a vibrator that is disposed in the single-crystal silicon layer and is connected to a doping region of the plurality of doping regions; a first diode that is a PN junction diode and allows an input signal applied to the vibrator to pass therethrough; and a second diode that is a PN junction diode and allows a signal output from the vibrator to pass therethrough.
    Type: Application
    Filed: June 19, 2012
    Publication date: February 28, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Che-heung KIM, Jong-oh KWON
  • Patent number: 8362591
    Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Hsien-Pin Hu, Jhe-Ching Lu, Chin-Wei Kuo, Ming-Fa Chen, Sally Liu
  • Publication number: 20120319176
    Abstract: In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung CHEN, Chewn-PU JOU, Chin Wei KUO, Sally LIU
  • Patent number: 8324064
    Abstract: Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: December 4, 2012
    Assignee: Freescale Semiconductors, Inc.
    Inventors: Pamela J. Welch, Wen Ling M. Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi
  • Publication number: 20120262229
    Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas M. Daley, Mete Erturk, Edward J. Gordon
  • Patent number: 8264047
    Abstract: A semiconductor component includes a semiconductor body having a first surface and a second surface, and having an inner region and an edge region. The semiconductor component further includes a pn-junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region. A first trench extends from the first side in the edge region into the semiconductor body. The trench has sidewalls that are arranged opposite to another and that are beveled relative to a horizontal direction of the semiconductor body.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: September 11, 2012
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Patent number: 8242581
    Abstract: Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: August 14, 2012
    Assignee: Altera Corporation
    Inventors: Albert Ratnakumar, Wilson Wong, Jun Liu, Qi Xiang, Jeffrey Xiaoqi Tung
  • Publication number: 20120181656
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Inventors: Wolfgang Lehnert, Michael Stadtmueller, Stefan Pompl, Markus Meyer
  • Publication number: 20120146188
    Abstract: A PN-junction varactor in a BiCMOS process is disclosed which comprises an N-type region, a P-type region and N-type pseudo buried layers. Both of the N-type and P-type regions are formed in an active area and contact with each other, forming a PN-junction; the P-type region is situated on top of the N-type region. The N-type pseudo buried layers are formed at bottom of shallow trench field oxide regions on both sides of the active area and contact with the N-type region; deep hole contacts are formed on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region. A manufacturing method of PN-junction varactor in a BiCMOS process is also disclosed.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 14, 2012
    Inventors: Fan Chen, Xiongbin Chen
  • Patent number: 8163612
    Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Erik M Dahlstrom, Alvin J Joseph, Robert M Rassel, David C Sheridan
  • Patent number: 8148193
    Abstract: A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole spaced apart from the opening to expose the conductive pattern, a semiconductor pattern and a heater electrode pattern electrically connected to the exposed active region and provided in the opening, a contact plug connected to the exposed conductive pattern and provided to fill the contact hole, and a phase change material layer provided on the heater electrode pattern.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jae-Hee Oh
  • Patent number: 8115281
    Abstract: A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: February 14, 2012
    Assignee: Atmel Corporation
    Inventors: Adam H. Pawlikiewicz, Samir el Rai
  • Publication number: 20120021586
    Abstract: Methods are disclosed for forming an improved varactor diode having first and second terminals. The methods include providing a substrate having a first surface in which are formed isolation regions separating first and second parts of the diode. A varactor junction is formed in the first part with a first side coupled to the first terminal and a second side coupled to the second terminal via a sub-isolation buried layer (SIBL) region extending under the bottom and partly up the sides of the isolation regions to a further doped region that is ohmically connected to the second terminal. The first part does not extend to the SIBL region. The varactor junction desirably comprises a hyper-abrupt doped region. The combination provides improved tuning ratio, operating frequency and breakdown voltage of the varactor diode while still providing adequate Q.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Pamela J. Welch, Wen Ling M. Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi
  • Publication number: 20110298551
    Abstract: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 8, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Tsung YEN, Hsien-Pin HU, Jhe-Ching LU, Chin-Wei KUO, Ming-Fa CHEN, Sally LIU
  • Patent number: 8063426
    Abstract: An insulated gate semiconductor device (30) includes a gate (34), a source terminal (36), a drain terminal (38) and a variable input capacitance at the gate. A ratio between the input capacitance (Cfiss) when the device is on and the input capacitance Ciiss when the device is off is less than two and preferably substantially equal to one. This is achieved in one embodiment of the invention by an insulation layer 32 at the gate having an effective thickness dins larger than a minimum thickness.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: November 22, 2011
    Assignee: North-West University
    Inventors: Barend Visser, Ocker Cornelis De Jager
  • Patent number: 8053866
    Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: November 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pamela J. Welch, Wen Ling M. Huang, David G. Morgan, Hernan A. Reuda, Vishal P. Trivedi
  • Publication number: 20110230032
    Abstract: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Inventor: Edward B. Harris
  • Publication number: 20110204969
    Abstract: Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.
    Type: Application
    Filed: February 19, 2010
    Publication date: August 25, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chung CHEN, Chewn-Pu Jou, Chin Wei Kuo, Sally Liu
  • Patent number: 7989868
    Abstract: A MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, includes: gate insulating layers arranged at equal intervals in the form of a (n×m) matrix, and a gate electrode placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire, which is electrically connected to the gate contact; source/drain contacts arranged at equal intervals in a matrix to form apexes of a square centered at the gate electrode and contact a doping region except for the bottom of the gate insulating layers; and a second metal wire, which is electrically connected to the source/drain contacts.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: August 2, 2011
    Assignee: Korea University Industrial & Academic Collaboration Foundation
    Inventors: Jae-Sung Rieh, Yong Ho Oh, Sue Yeon Kim, Seung Yong Lee
  • Patent number: 7989302
    Abstract: Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Alvin J. Joseph, Robert M. Rassel, Yun Shi
  • Patent number: 7985615
    Abstract: The present invention relates to embodiments of TPV cell structures based on carbon nanotube and nanowire materials. One embodiment according to the present invention is a p-n junction carbon nanotube/nanowire TPV cell, which is formed by p-n junction wires. A second embodiment according to the present invention is a carbon nanotube/nanowire used as a p-type (or n-type), and using bulk material as the other complementary type to a form p-n junction TPV cell. A third embodiment according to the present invention uses a controllable Schottky barrier height between a one-dimensional nanowire and a metal contact to form the built-in potential of the TPV cells.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: July 26, 2011
    Assignee: The Regents of the University of California
    Inventors: Fei Liu, Ma Siguang, Kang L. Wang
  • Patent number: 7919382
    Abstract: An improved varactor diode (40) is obtained by providing a substrate (70) having a first surface (73) and in which are formed a first N region (46) having a first peak dopant concentration (47) located at a first depth (48) beneath the surface (73), and a first P region 49having a second peak dopant concentration (50) greater than the first peak dopant concentration located at a second depth (51) beneath the surface less than the first depth (48), and a second P region (42) having a third peak dopant concentration (43) greater than the second peak dopant concentration and located at a third depth at or beneath the surface (73) less than the second depth (51), so that the first P region (49) provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge (44) of the second P region (42) up to the second peak dopant concentration (50).
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: April 5, 2011
    Assignee: Freescale Semicondcutor, Inc.
    Inventor: Vishal P. Trivedi
  • Patent number: 7915658
    Abstract: A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: March 29, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mario M. Pellela, Donggang D. Wu, James F. Buller
  • Publication number: 20110031588
    Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).
    Type: Application
    Filed: August 6, 2009
    Publication date: February 10, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Pamela J. Welch, Wen Ling Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi
  • Patent number: 7821103
    Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chun-Li Liu, Olin K. Hartin, Jay P. John, Vishal P. Trivedi, James A. Kirchgessner
  • Publication number: 20100244113
    Abstract: The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor.
    Type: Application
    Filed: September 23, 2009
    Publication date: September 30, 2010
    Applicant: KOREA UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATION
    Inventors: Jae-Sung Rieh, Yong Ho Oh, Sue Yeon Kim, Seung Yong Lee
  • Patent number: 7804119
    Abstract: Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: September 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Alvin J. Joseph, Robert M. Rassel, Yun Shi
  • Publication number: 20100237468
    Abstract: On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state.
    Type: Application
    Filed: September 2, 2009
    Publication date: September 23, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas M. Daley, Mete Erturk, Edward J. Gordon
  • Publication number: 20100213513
    Abstract: A hyperabrupt diode structure includes a substrate formed from a low-ohmic contact material, a graded semiconductor layer comprising gallium arsenide, an offset layer comprising indium gallium phosphide over the graded semiconductor layer, a contact layer comprising gallium arsenide over the offset layer, a first electrical contact on the substrate, the first electrical contact forming a cathode of the hyperabrupt diode structure, and a second electrical contact over the contact layer, the second electrical contact forming an anode of the hyperabrupt diode structure.
    Type: Application
    Filed: February 26, 2009
    Publication date: August 26, 2010
    Applicant: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, HsiangChih Sun
  • Patent number: 7781284
    Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: August 24, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 7718503
    Abstract: A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: May 18, 2010
    Assignee: GlobalFoundries Inc.
    Inventors: Mario M. Pellela, Donggang D. Wu, James F. Buller
  • Patent number: 7714412
    Abstract: The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Douglas B. Hershberger, Robert M. Rassel
  • Patent number: 7704845
    Abstract: Disclosed is a varactor and/or variable capacitor. The varactor/variable capacitor includes a plurality of first conductive-type wells vertically formed on a substrate, a plurality of second conductive-type ion implantation areas formed in the first conductive-type wells, at least one second conductive-type plug electrically connected to the second conductive-type ion implantation areas, an isolation layer formed at sides of an uppermost second conductive-type ion implantation area, and a first conductive-type ion implantation area in an uppermost first conductive-type well electrically disconnected from the uppermost second conductive-type ion implantation area by the isolation area.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: April 27, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Su Lim
  • Patent number: 7700453
    Abstract: Method of fabricating a varactor that includes providing a semiconductor substrate, doping a lower region of the semiconductor substrate with a first dopant at a first energy level, doping a middle region of the semiconductor substrate with a second dopant at a second energy level lower than the first energy level, and doping an upper region of the semiconductor substrate with a third dopant at a third energy level lower than the second energy level.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: April 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Stephen S. Furkay, Jeffrey B. Johnson, Robert M. Rassel, David C. Sheridan
  • Publication number: 20100093148
    Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.
    Type: Application
    Filed: December 17, 2009
    Publication date: April 15, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erik M. Dahlstrom, Alvin J. Joseph, Robert M. Rassel, David C. Sheridan
  • Patent number: 7682919
    Abstract: A method in the fabrication of an integrated circuit including a PMOS varactor and an npn transistor, comprises the steps of (i) simultaneously forming buried n+-doped regions (31) for the PMOS varactor and the npn transistor in a p-doped substrate (10, 41); (ii) simultaneously forming n-doped wells (41) above the buried n+-doped regions (31); (iii) simultaneously forming field isolation areas (81) around the n-doped regions (41); (iv) forming a PMOS gate region (111, 194) and a p-doped base each in a respective one of the n-doped wells (41); and (v) simultaneously forming n+-doped contacts to the buried n+-doped regions (31); the contacts being separated from the n-doped wells (41). Source and drain regions may be formed in the PMOS n-well (inversion mode) or the PMOS n+-doped contact may be formed in the PMOS n-well instead of being separated from there (accumulation mode).
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: March 23, 2010
    Assignee: Infineon Technologies AG
    Inventor: Ted Johansson
  • Publication number: 20100059850
    Abstract: A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.
    Type: Application
    Filed: September 8, 2008
    Publication date: March 11, 2010
    Inventor: Christopher Harris
  • Publication number: 20100059860
    Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 11, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chun-Li Liu, Olin L. Hartin, Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Patent number: 7629668
    Abstract: The electrode of a thin-type capacitor is connected to the rear surface of a p-type semiconductor substrate which is brought to a ground potential, by a conductive DAF (Die Attach Film) or by a conductive adhesive, and the electrodes of the front surface of the p-type semiconductor substrate are respectively connected with and stacked on the terminals of a thin-type inductor by bumps, whereby manufacturing costs can be reduced while the occurrence of noise can be suppressed and packaging area can be made small.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: December 8, 2009
    Assignee: Fuji Electric Technology Co., Ltd.
    Inventors: Jun Yabuzaki, Takeshi Yokoyama, Tomonori Seki