Diode (epo) Patents (Class 257/E21.366)
  • Patent number: 9029921
    Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 8999770
    Abstract: A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 7, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Tien-Ming Lin, Chih-Hsuan Sun, Wei-Yu Yeh
  • Patent number: 8916872
    Abstract: A method of forming a stacked low temperature diode and related devices. At least some of the illustrative embodiments are methods comprising forming a metal interconnect disposed within an inter-layer dielectric. The metal interconnect is electrically coupled to at least one underlying integrated circuit device. A barrier layer is deposited on the metal interconnect and the inter-layer dielectric. A semiconductor layer is deposited on the barrier layer. A metal layer is deposited on the semiconductor layer. The barrier layer, the semiconductor layer, and the metal layer are patterned. A low-temperature anneal is performed to induce a reaction between the patterned metal layer and the patterned semiconductor layer. The reaction forms a silicided layer within the patterned semiconductor layer. Moreover, the reaction forms a P-N junction diode.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 23, 2014
    Assignee: Inoso, LLC
    Inventors: Ziep Tran, Kiyoshi Mori, Giang Trung Dao, Michael Edward Ramon
  • Patent number: 8759164
    Abstract: In a method for manufacturing an integral imaging device, a layer of curable adhesive is first applied on a flexible substrate and half cured such that the curable adhesive is solidified but is capable of deforming under external forces. Then the curable adhesive is printed into a lenticular lens having a predetermined shape and size using a roll-to-roll processing device and fully cured such that the curable adhesive is capable of withstanding external forces to hold the predetermined shape and size. Last, a light emitting diode display is applied on the flexible substrate opposite to the lenticular lens such that an image plane of the light emitting diode display coincides with a focal plane of the lenticular lens.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: June 24, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chia-Ling Hsu
  • Patent number: 8716745
    Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 6, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8652958
    Abstract: A vertical geometry light emitting diode with a strain relieved superlattice layer on a substrate comprising doped AlXInYGa1-X-YN. A first doped layer is on the strain relieved superlattice layer AlXInYGa1-X-YN and the first doped layer has a first conductivity. A multilayer quantum well is on the first doped layer comprising alternating layers quantum wells and barrier layers. The multilayer quantum well terminates with a barrier layer on each side thereof. A second doped layer is on the quantum well wherein the second doped layer comprises AlXInYGa1-X-YN and said second doped layer has a different conductivity than said first doped layer. A contact layer is on the third doped layer and the contact layer has a different conductivity than the third doped layer. A metallic contact is in a vertical geometry orientation.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: February 18, 2014
    Assignee: Nitek, Inc.
    Inventor: Asif Khan
  • Patent number: 8633500
    Abstract: Light emitting diodes and methods for manufacturing light emitting diodes are disclosed herein. In one embodiment, a method for manufacturing a light emitting diode (LED) comprises applying a first light conversion material to a first region on the LED and applying a second light conversion material to a second, different region on the LED. A portion of the LED is exposed after applying the first and second light conversion materials.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: January 21, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Charles M. Watkins
  • Patent number: 8633521
    Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: January 21, 2014
    Assignee: STMicroelectronics N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 8604529
    Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 10, 2013
    Assignee: Intellectual Ventures II LLC
    Inventor: Han-Seob Cha
  • Patent number: 8507328
    Abstract: A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: August 13, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Tien-Ming Lin, Chih-Hsuan Sun, Wei-Yu Yeh
  • Patent number: 8415685
    Abstract: A light-emitting element has a cathode, an anode, a light-emitting portion interposed between the cathode and the anode and having a light-emitting layer that emits light on energization between the cathode and the anode, and a hole-injection layer interposed between and in direct contact with the anode and the light-emitting layer and having a capability of receiving holes, and the hole-injection layer is mainly composed of a benzidine derivative.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: April 9, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Tetsuji Fujita, Hidetoshi Yamamoto, Shinichi Iwata, Koji Yasukawa
  • Patent number: 8354287
    Abstract: The present invention provides a method for manufacturing an organic EL device. When an organic EL element which is composed of a pair of electrodes in which at least one of the electrodes is transparent or translucent, and an organic EL layer which comprises a light-emitting layer held between the electrodes, and a sealing layer which includes at least one layer of inorganic film being in contact with the organic EL element and which seals the organic EL element are formed on a substrate, a first sealing film which is included in the sealing layer and in contact with the organic EL element is formed by the facing target sputtering method, and the other inorganic film which is included in the sealing layer is formed by any method other than the facing target sputtering method.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: January 15, 2013
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Makoto Sasaki, Shinichi Morishima, Norihito Ito
  • Patent number: 8273589
    Abstract: Light emitting diodes and methods for manufacturing light emitting diodes are disclosed herein. In one embodiment, a method for manufacturing a light emitting diode (LED) comprises applying a first light conversion material to a first region on the LED and applying a second light conversion material to a second, different region on the LED. A portion of the LED is exposed after applying the first and second light conversion materials.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Charles M. Watkins
  • Patent number: 8258559
    Abstract: The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: September 4, 2012
    Assignee: Siliconfile Technologies Inc.
    Inventor: Byoung-Su Lee
  • Patent number: 8198114
    Abstract: A vertical nitride-based semiconductor LED comprises a structure support layer; a p-electrode formed on the structure support layer; a p-type nitride semiconductor layer formed on the p-electrode; an active layer formed on the p-type nitride semiconductor layer; an n-type nitride semiconductor layer formed on the active layer; an n-electrode formed on a portion of the n-type nitride semiconductor layer; and a buffer layer formed on a region of the n-type nitride semiconductor layer on which the n-electrode is not formed, the buffer layer having irregularities formed thereon. The surface of the n-type nitride semiconductor layer coming in contact with the n-electrode is flat.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: June 12, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Sang Ho Yoon, Su Yeol Lee, Doo Go Baik, Seok Beom Choi, Tae Sung Jang, Jong Gun Woo
  • Patent number: 8178378
    Abstract: A vertical nitride-based semiconductor LED comprises a structure support layer; a p-electrode formed on the structure support layer; a p-type nitride semiconductor layer formed on the p-electrode; an active layer formed on the p-type nitride semiconductor layer; an n-type nitride semiconductor layer formed on the active layer; an n-electrode formed on a portion of the n-type nitride semiconductor layer; and a buffer layer formed on a region of the n-type nitride semiconductor layer on which the n-electrode is not formed, the buffer layer having irregularities formed thereon. The surface of the n-type nitride semiconductor layer coming in contact with the n-electrode is flat.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: May 15, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Ho Yoon, Su Yeol Lee, Doo Go Baik, Seok Beom Choi, Tae Sung Jang, Jong Gun Woo
  • Patent number: 8154052
    Abstract: In some embodiments of the invention, a device includes a substrate and a semiconductor structure. The substrate includes a wavelength converting element comprising a wavelength converting material disposed in a transparent material, a seed layer comprising a material on which III-nitride material will nucleate, and a bonding layer disposed between the wavelength converting element and the seed layer. The semiconductor structure includes a III-nitride light emitting layer disposed between an n-type region and a p-type region, and is grown on the seed layer.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 10, 2012
    Assignees: Koninklijke Philips Electronics N.V., Philips Lumileds Lighting Company, LLC
    Inventors: Nathan F. Gardner, Aurelien J. F. David, Oleg B. Shchekin
  • Patent number: 8124432
    Abstract: In an InGaN-based nitride semiconductor optical device having a long wavelength (440 nm or more) equal to or more than that of blue, the increase of a wavelength is realized while suppressing In (Indium) segregation and deterioration of crystallinity. In the manufacture of an InGaN-based nitride semiconductor optical device having an InGaN-based quantum well active layer including an InGaN well layer and an InGaN barrier layer, a step of growing the InGaN barrier layer includes: a first step of adding hydrogen at 1% or more to a gas atmosphere composed of nitrogen and ammonia and growing a GaN layer in the gas atmosphere; and a second step of growing the InGaN barrier layer in a gas atmosphere composed of nitrogen and ammonia.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: February 28, 2012
    Assignee: Opnext Japan, Inc.
    Inventors: Tomonobu Tsuchiya, Shigehisa Tanaka, Akihisa Terano, Kouji Nakahara
  • Patent number: 8076197
    Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: December 13, 2011
    Assignee: Intellectual Ventures II LLC
    Inventor: Han-Seob Cha
  • Patent number: 8034716
    Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: October 11, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung T. Doan, Raymond A. Turi, Graham R. Wolstenholme
  • Patent number: 8008694
    Abstract: A light source with enhanced brightness includes an angle-selective optical filter and a light emitting diode (LED) having a high reflective layer. The angle-selective filter is located on the top surface of emitting diode to pass lights at specified angles. According to one embodiment, the angle-selective filter includes index-alternating layers. With a reflective polarizer, the light source can produce polarized light with enhanced brightness.
    Type: Grant
    Filed: September 22, 2007
    Date of Patent: August 30, 2011
    Assignee: YLX, Ltd.
    Inventors: Li Xu, Yi Li
  • Patent number: 8003421
    Abstract: A method for manufacturing a compound semiconductor substrate includes at least the processes of epitaxially growing a quaternary light emitting layer composed of AlGaInP on a GaAs substrate; vapor-phase growing a p-type GaP window layer on a first main surface of the quaternary light emitting layer, the first main surface being opposite to the GaAs substrate; removing the GaAs substrate; and epitaxially growing an n-type GaP window layer on a second main surface of the light emitting layer, the second main surface being located at a side where the GaAs substrate is removed. The method includes the process of performing a heat treatment under a hydrogen atmosphere containing ammonia after the process of removing the GaAs substrate and before the process of epitaxially growing the n-type GaP window layer.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: August 23, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yukari Suzuki, Jun Ikeda, Masataka Watanabe
  • Patent number: 7781248
    Abstract: There are provided a method of manufacturing a nitride semiconductor light emitting device and a nitride semiconductor light emitting device manufactured using the same. A method of manufacturing a nitride semiconductor light emitting device according to an aspect of the invention includes: forming a mask layer on a substrate; removing a portion of the mask layer to form openings provided as regions where light emitting structures are formed; forming a light emitting structure by sequentially growing a first conductivity type nitride semiconductor layer, an active layer, and a second conductivity type nitride semiconductor layer on the substrate through each of the openings of the mask layer; and forming first and second electrodes to be electrically connected to the first and second conductivity type nitride semiconductor layers, respectively.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: August 24, 2010
    Assignee: Samsung LED Co., Ltd.
    Inventors: Hyun Wook Shim, Yong Chun Kim, Joong Seo Kang
  • Patent number: 7772599
    Abstract: A gallium-nitride-based semiconductor stacked structure includes a low-temperature-deposited buffer layer and an active layer. The low-temperature-deposited buffer layer is composed of a Group III nitride material that has been grown at low temperature and includes a single-crystal layer in an as-grown state, the single-crystal layer being present in the vicinity of a junction area that is in contact with a (0001) (c) plane of a sapphire substrate. The active layer is composed of a gallium-nitride (GaN)-based semiconductor layer that is provided on the low-temperature-deposited buffer layer. The single-crystal layer is composed of a hexagonal AlXGaYN (0.5<X?1, X+Y=1) crystal that contains aluminum in a predominant amount with respect to gallium such that a [2.?1.?1.0.] direction of the AlXGaYN crystal orients along with a [2.?1.?1.0.] direction of the (0001) bottom plane of the sapphire substrate.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: August 10, 2010
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 7772020
    Abstract: A vertical topology device includes a conductive adhesion structure having a first surface and a second surface, a conductive thick film support formed on the first surface, and a semiconductive device having an upper electrical contact and located over the conductive adhesion layer. Electrical current can flow between the conductive thick film and the upper electrical contact.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: August 10, 2010
    Assignee: LG Electronics Inc.
    Inventor: Myung Cheol Yoo
  • Patent number: 7701023
    Abstract: A TFA (thin film on ASIC) image sensor with stability-optimized photodiode for converting electromagnetic radiation into an intensity-dependent photocurrent. The TFA includes an intermetal dielectric layer, pixel back electrodes, vias, metal contacts, a transparent conductive oxide (TCO) layer, and an intrinsic absorption layer with a thickness between 300 nm and 600 nm. The pixel back electrodes are disposed over the intermetal dielectric layer, which is disposed over the ASIC. The vias connect to the pixel back electrodes and the metal contacts, which are formed in the intermetal dielectric layer. The TCO is disposed above the intrinsic absorption layer, which is disposed above the pixel back electrodes.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: April 20, 2010
    Assignee: STMicroelectronics N.V.
    Inventors: Peter Rieve, Marcus Walder, Konstantin Seibel, Jens Prima, Arash Mirhamed
  • Patent number: 7541252
    Abstract: A method of fabricating a semiconductor device includes forming a conductive layer on a semiconductor substrate, forming an insulating layer on the conductive layer, forming a word line and isolation trenches by patterning the insulating layer and the conductive layer, forming an isolation layer that fills the isolation trenches, forming a cell contact hole in the insulating layer such that the cell contact hole is self-aligned with the word line and exposes the word line, and forming a cell diode in the cell contact hole.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 2, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Ho Eun, Jae-Hee Oh, Jae-Hyun Park, Jung-In Kim, Seung-Pil Ko, Yong-Tae Oh
  • Patent number: 7456034
    Abstract: A nitride semiconductor device comprises: a well layer of nitride semiconductor containing In and Ga; barrier layers of nitride semiconductor sandwiching the well layer, containing Al and Ga, and having a larger band gap energy than the well layer; and a thin film layer provided between the well layer and the barrier layer. The thin film layer is formed during lowering of the substrate temperature after formation of the barrier layer or during elevation of the substrate temperature after formation of the well layer.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: November 25, 2008
    Assignee: Panasonic Corporation
    Inventors: Norio Ikedo, Yasuyuki Fukushima, Masaaki Yuri
  • Publication number: 20080157111
    Abstract: Light-emitting devices, and related components, systems and methods are disclosed.
    Type: Application
    Filed: November 26, 2007
    Publication date: July 3, 2008
    Applicant: Luminus Devices, Inc.
    Inventors: Alexei A. Erchak, Elefterios Lidorikis, Chiyan Luo
  • Publication number: 20080128722
    Abstract: A method for fabrication of a semiconductor device, the semiconductor device having a plurality of epitaxial layers on a substrate. The plurality of epitaxial layers include an active region in which light is able to be generated. The method comprises applying at least one first ohmic contact layer to a front surface of the epitaxial layer, the first ohmic contact layer also acting as a reflector. The substrate is then remove from a rear surface of the epitaxial layers. The rear surface is then textured.
    Type: Application
    Filed: March 1, 2005
    Publication date: June 5, 2008
    Inventors: Shu Yuan, Xuejun Kang
  • Patent number: 7381997
    Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: June 3, 2008
    Assignee: International Business Machines Corporation
    Inventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
  • Publication number: 20080121914
    Abstract: Provided are a flip-chip nitride-based light emitting device having an n-type clad layer, an active layer and a p-type clad layer sequentially stacked thereon, comprising a reflective layer formed on the p-type clad layer and at least one transparent conductive thin film layer made up of transparent conductive materials capable of inhibiting diffusion of materials constituting the reflective layer, interposed between the p-type clad layer and reflective layer; and a process for preparing the same. In accordance with the flip-chip nitride-based light emitting device of the present invention and a process for preparing the same, there are provided advantages such as improved ohmic contact properties with the p-type clad layer, leading to increased wire bonding efficiency and yield upon packaging the light emitting device, capability to improve luminous efficiency and life span of the device due to low specific contact resistance and excellent current-voltage properties.
    Type: Application
    Filed: July 12, 2005
    Publication date: May 29, 2008
    Inventors: Tae-Yeon Seong, June-O Song, Kyoung-Kook Kim, Woong-Ki Hong
  • Publication number: 20080121904
    Abstract: There is obtained a semiconductor light-emitting device capable of obtaining a high light reflectance through the use of a high-reflection metal layer formed on the side of an electrode on one side and capable of preventing migration of atoms from the high-reflectance metal layer. Semiconductor layers of the opposite conduction types are formed on the opposite sides of an active layer, and an ohmic contact layer being a thin film for contriving a decrease in contact resistance, a transparent and conductive layer, and a high-reflection metal layer for reflecting light generated in the active layer are sequentially layered on one of the semiconductor layers. Since the transparent conductive layer functions also as a barrier layer and it transmits light, a high light take-out efficiency can be obtained through the reflection at the high-reflectance metal layer.
    Type: Application
    Filed: March 31, 2005
    Publication date: May 29, 2008
    Applicant: SONY CORPORATION
    Inventors: Jun Suzuki, Masato Doi, Hiroyuki Okuyama, Goshi Biwa
  • Patent number: 7368309
    Abstract: The present invention relates to nitride semiconductor, and more particularly, to GaN-based nitride semiconductor and fabrication method thereof. The nitride semiconductor according to the present invention comprises a substrate; a GaN-based buffer layer formed in any one of a group of three-layered structure AlyInxGa1?(x+y)N/InxGa1?xN/GaN where 0?x?1 and 0?y?1, two-layered structure InxGa1?xN/GaN where 0?x?1 and superlattice structure of InxGa1?xN/GaN where 0?x?1; and a GaN-based single crystalline layer.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: May 6, 2008
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 7335927
    Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: February 26, 2008
    Assignee: Internatioanl Business Machines Corporation
    Inventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
  • Patent number: 7314770
    Abstract: A method of making a light emitting device is disclosed. The method includes the steps of providing a light emitting diode and forming an encapsulant in contact with the light emitting diode; wherein forming the encapsulant includes contacting the light emitting diode with a photopolymerizable composition consisting of a silicon-containing resin and a metal-containing catalyst, wherein the silicon-containing resin consists of silicon-bonded hydrogen and aliphatic unsaturation, and applying actinic radiation having a wavelength of 700 nm or less to initiate hydrosilylation within the silicon-containing resin.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: January 1, 2008
    Assignee: 3M Innovative Properties Company
    Inventors: Larry D. Boardman, D. Scott Thompson, Catherine A. Leatherdale, Andrew J. Ouderkirk
  • Patent number: 7282382
    Abstract: The invention relates to a method for producing a photodiode contact for a TFA image sensor which includes a photodiode, produced by deposition of a multilayer system and a transparent conductive contact layer on an ASIC circuit that has been coated with an intermediate metal dielectric component and that has vias in a photoactive zone which are arranged on a pixel grid. Said vias extend through the intermediate metal dielectric component and are linked with respective strip conductors of the CMOS-ASIC circuit. A pixel-grid structured barrier layer, and on top thereof a CMOS metallization, are arranged on the intermediate metal dielectric component. The aim of the invention is to improve the characteristic variables of the photodiode by simple technological means.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 16, 2007
    Assignee: STMicroelectronics N.V.
    Inventors: Peter Rieve, Konstantin Seibel, Michael Wagner
  • Patent number: 7271019
    Abstract: Disclosed are a semiconductor device and method of manufacturing the same comprising a substrate, a mesa region adjacent to the substrate, an electroplated metal layer, for reducing the thermal resistance of the device, surrounding the mesa region, an insulator layer separating a side portion of the mesa region from the electroplated metal layer, a heat sink, a bonding layer adjacent to the heat sink, and a second metal layer in between the substrate and the heat sink, wherein the substrate is adjacent to the bonding layer, and wherein the electroplated metal layer dimensioned and configured to have a thickness of at least half a thickness of the mesa region; and to laterally spread heat away from the mesa region. The mesa region comprises a first cladding layer adjacent to the substrate, an active region adjacent the first cladding layer, and a second cladding layer adjacent to the active region.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: September 18, 2007
    Assignee: United States of America as represented by the Secretary of the Army
    Inventors: John T. Pham, John D. Bruno, Richard L. Tober
  • Patent number: 7224026
    Abstract: Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at least 100 nm long and less than 100 nm wide. The current-voltage characteristic of the diode devices are similar to a conventional diode, but both the threshold voltage (from 0V to a few volts) and the current level (from nA to ?A) can be tuned by orders of magnitude by changing the device geometry. Standard silicon wafers can be used as substrates. A full family of logic gates, such as OR, AND, and NOT, can be constructed based on this device solely by simply etching insulative lines in the substrate.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: May 29, 2007
    Assignee: The University of Manchester
    Inventors: Amin Song, Pär Omling
  • Patent number: 7112511
    Abstract: A method for fabricating a CMOS image sensor with a prism includes the steps of: forming a plurality of photodiodes corresponding to respective unit pixels on a substrate; sequentially forming an inter-layer insulation layer and an uppermost metal line on the substrate and the photodiodes; etching the inter-layer insulation layer to form a plurality of trenches corresponding to the respective photodiodes; depositing a high density plasma (HDP) oxide layer such that the HDP oxide layer disposed between the trenches has a tapered profile; depositing a nitride layer having a higher refractive index than that of the inter-layer insulation layer to fill the trenches; and depositing an insulation layer having a lower refractive index than that of the nitride layer to fill the trenches, thereby forming a prism, wherein the prism induces a total reflection of lights incident to the photodiodes disposed in edge regions of a pixel array.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: September 26, 2006
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Hee Jeong Hong