Structurally Associated With Other Devices (epo) Patents (Class 257/E21.39)
E Subclasses
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Patent number: 8772183Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.Type: GrantFiled: October 20, 2011Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yen Hsieh, Chang Ming-Ching, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
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Patent number: 8691634Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.Type: GrantFiled: August 7, 2013Date of Patent: April 8, 2014Assignee: General Electric CompanyInventors: Ahmed Elasser, Stephen Daley Arthur, Alexey Vert, Stanislav Ivanovich Soloviev, Peter Almern Losee
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Publication number: 20130320398Abstract: An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventor: Da-Wei Lai
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Publication number: 20130153953Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Ahmed Elasser, Arthur Stephen Daley, Alexey Vert, Stanislav I. Soloviev, Peter Almern Losee
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Patent number: 8420454Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device coupled in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal coupled to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, coupled between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal coupled to the control terminal; and a Zener diode, coupled between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.Type: GrantFiled: January 31, 2011Date of Patent: April 16, 2013Assignee: STMicroelectronics S.r.l.Inventors: Cesare Ronsisvalle, Vincenzo Enea
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Publication number: 20120199874Abstract: An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation.Type: ApplicationFiled: February 4, 2011Publication date: August 9, 2012Applicant: Analog Devices, Inc.Inventors: Javier A. Salcedo, Karl Sweetland
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Publication number: 20110180845Abstract: An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.Type: ApplicationFiled: April 5, 2011Publication date: July 28, 2011Inventor: Shekar Mallikarjunaswamy
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Publication number: 20110121361Abstract: The present invention provides a device for electrostatic discharge and the method of manufacturing thereof. P-well is formed on the substrate, and a first N+ doped region, a second N+ doped region and a P+ doped region are formed in the P-well; both ends of each doped region adopt shallow trench isolation for isolation. A lightly doped source-drain region portion is formed between the first N+ doped region and the shallow trench isolation connected thereto. Under the source-drain region, a halo injection with an inverse type is formed. The reverse conduction voltage of the collector of the bipolar transistor is lowered through the introduction of special doped region and the adoption of lightly doped source-drain technology for manufacturing the source-drain region as well as the manufacturing of halo injection with inverse type under the source-drain region, thus reducing the trigger voltage of the device.Type: ApplicationFiled: December 22, 2008Publication date: May 26, 2011Applicant: GRACE SEMICONDUCTOR MANUFACTURING CORPORATIONInventors: Yi Shan, Jun He
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Publication number: 20090250706Abstract: The present invention provides an optically triggered switch and a method of forming the optically triggered switch. The optically triggered switch includes a silicon layer having at least one trench formed therein and at least one silicon diode formed in the silicon layer. The switch also includes a first thyristor formed in the silicon layer. The first thyristor is physically and electrically isolated from the silicon diode by the trench and the first thyristor is configured to turn on in response to electromagnetic radiation generated by the silicon diode.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventor: THOMAS J. KRUTSICK
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Patent number: 7374974Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.Type: GrantFiled: March 5, 2004Date of Patent: May 20, 2008Assignee: T-RAM Semiconductor, Inc.Inventors: Andrew Horch, Scott Robins