Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.

Abstract: A display device free of contact resistance between a drain electrode (or a source electrode) and a pixel electrode. The display device includes a gate electrode, a gate insulating layer covering the gate electrode, a semiconductor layer formed over the gate insulating layer, and a source electrode and a drain electrode separated from each other and in partial-contact with and over the semiconductor layer, and one of the source electrode and the drain electrode also serves as a pixel electrode, the other of the source electrode and the drain electrode also serves as a signal line, and a low resistant conductive layer is preferably formed over the other of the source electrode and the drain electrode. The low resistant conductive layer can be formed by an electroplating method or the like.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

Abstract: Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.

Abstract: A field effect transistor comprising a semiconductor substrate comprising an electrically conducting channel layer therein; a plurality of source and drain fingers on a first face of the substrate, each finger separated from the adjacent finger by a gate channel; the gate channels comprising at least one active gate channel defined by a source finger and a drain finger arranged on the first face such that current is free to flow between them via the electrically conducting channel layer, and, a plurality of inactive gate channels, each inactive gate channel being defined by either two fingers of the same type or a source finger and a drain finger, the source finger and drain finger being arranged on the first face such that current is not free to flow between them via the electrically conducting channel layer; the gate channels being arranged such that each active gate channel has a gate channel on each side; each active gate channel comprising a gate therein for controlling current flow in the electrically c

Abstract: Apparatuses and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.

Abstract: An electrostatic discharge (ESD) protection device (11, 60, 80) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24), comprises, first (70, 90) and second (72, 92) merged bipolar transistors (70, 90; 72, 92). A base (62, 82) of the first (70, 90) transistor serves as collector of the second transistor (72, 92) and the base of the second transistor (72, 92) serves as collector of the first (70, 90) transistor, the bases (62, 82) having, respectively, first width (74, 94) and second width (76, 96). A first resistance (78, 98) is coupled between an emitter (67, 87) and base (62, 82) of the first transistor (70, 90) and a second resistance (79, 99) is coupled between an emitter (68, 88) and base (64, 42) of the second transistor (92, 92). ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths (74, 94; 76, 96) and resistances (78, 98; 79, 99).

Abstract: Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

Abstract: In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

Abstract: A method is provided for modifying a circuit containing a plurality of electrodes, within a substrate, comprising the steps of: (a) selecting at least two electrodes for making a connection; (b) removing materials covering the electrodes with a focused ion beam (FIB) or a laser to form contact holes for respectively exposing the electrodes; (c) depositing in the contact holes a conductive material for forming electrically conductive piers, by applying the focused ion beam (FIB) or laser, with gas molecules ejected from a nozzle; (d) disposing an electrically conductive viscid material over each of the electrically conductive piers; and (e) disposing an electrically conductive bridge floor to connect with the electrically conductive viscid material to form an electrically conductive bridge.

Abstract: Provided are a capacitor of a semiconductor device having an increased capacitance within a minimum area, and a fabrication method thereof. The capacitor includes a first electrode on a substrate, a first insulator on the first electrode, a second electrode on the first insulator, a second insulator on the second electrode where the second insulator is in contact with the first insulator, and a third electrode on the second insulator where the third electrode is in contact with the first electrode. In embodiments, the capacitance can be desirably adjusted within a limited area by alternately overlaying electrodes and insulator layers connected at alternating sides to the electrode or insulator layer below, which makes it possible to design the semiconductor device flexibly and maximize the capacitance.