Abstract: Techniques for fabricating metal lines in semiconductor systems are disclosed. The metal may be tungsten. A hybrid Chemical Vapor Deposition (CVD)/Physical Vapor Deposition (PVD) process may be used. A layer of tungsten may be formed using CVD. This CVD layer may be formed over a barrier layer, such as, but not limited to, TiN or WN. This CVD layer may completely fill some feature such as a trench or via. Then, a layer of tungsten may be formed over the CVD layer using PVD. The layers of tungsten may then be etched to form a wire or line. Techniques for forming metal wires using a hybrid CVD/PVD process may provide for low resistivity with a barrier metal, low surface roughness, and good gap filling.

Abstract: A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.

Abstract: A sensor assembly for electric field sensing is provided. The sensor assembly may include an array of Micro-Electro-Mechanical System (MEMS)-based resonant tunneling devices. A resonant tunneling device may be configured to generate a resonant tunneling signal in response to the electric field. The resonant tunneling device may include at least one electron state definer responsive to changes in at least one respective controllable characteristic of the electron state definer. The changes in the controllable characteristic are configured to affect the tunneling signal. An excitation device may be coupled to the resonant tunneling device to effect at least one of the changes in the controllable characteristic affecting the tunneling signal. A controller may be coupled to the resonant tunneling device and the excitation device to control the changes of the controllable characteristic in accordance with an automated control strategy configured to reduce an effect of noise on a measurement of the electric field.

Abstract: Light emitters using nanotubes and methods of making same. A light emitter includes a nanotube article in electrical communication with a first and a second contact, a substrate having a predefined region with a relatively low thermal conductivity said region in predefined physical relation to said nanotube article; and a stimulus circuit in electrical communication with the first and second contacts. The stimulus circuit provides electrical stimulation sufficient to induce light emission from the nanotube article in the proximity of the predefined region. The predefined region is a channel formed in the substrate or a region of material with relatively low thermal conductivity. The light emitter can be integrated with semiconductor circuits including CMOS circuits. The light emitter can be integrated into optical driver circuits (on- and off-chip drivers) and opto-isolators.

Abstract: A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.

Abstract: A manufacturing method of a flat panel display according to an exemplary embodiment of the present invention includes: coating a first adhering member on a first supporting plate; disposing a first substrate on the first adhering member; using ultrasonic waves to adhere the first supporting plate and the first substrate; and forming a gate line, a data line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor on the first substrate. According to the manufacturing method of the flat panel display according to an exemplary embodiment of the present invention, the first adhering member made of the plurality of adhering particles is melted by using the ultrasonic waves without an additional adhering film to adhere the flexible first substrate and the first supporting plate, thereby reducing the overall manufacturing cost.

Abstract: A thermionic electron emitter/collector includes a substrate and a doped diamond electron emitter/collector layer on the substrate. The doped diamond electron emitter/collector layer has at least a first and a second doping concentration as a function of depth such that the first doping concentration is different from the second doping concentration.

Abstract: A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.

Abstract: A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.

Abstract: A first opening and a second opening are formed at the same time over a first metal wiring and a second metal wiring, respectively which are provided as the same layer on a substrate on which a transistor for selecting a memory cell is formed. Then, a variable resistor and an upper electrode are deposited on a whole surface so as to completely fill the first opening with the upper electrode but not to completely fill the second opening with it. Thereafter, a variable resistive element is formed in the first opening and a via hole to connect to the third metal wiring (bit line), in the second opening, at the same time, by performing back-etching until a surface of the second metal wiring is exposed at a bottom of the second opening.

Abstract: A method of operating and process for fabricating an electron source. A conductive rod is covered by an insulating layer, by dipping the rod in an insulation solution, for example. The rod is then covered by a field emitter material to form a layered conductive rod. The rod may also be covered by a second insulating material. Next, the materials are removed from the end of the rod and the insulating layers are recessed with respect to the field emitter layer so that a gap is present between the field emitter layer and the rod. The layered rod may be operated as an electron source within a vacuum tube by applying a positive bias to the rod with respect to the field emitter material and applying a higher positive bias to an anode opposite the rod in the tube. Electrons will accelerate to the charged anode and generate soft X-rays.

Abstract: A Light Modulating sensing MOSFET transistor includes: a substrate receiving light radiation, the substrate having two source and drain areas separated by a channel extending along a first direction; a gate conductive beam extending along a second direction being substantially perpendicular to the first direction, the beam being fixed at each of its two opposite ends on at least one supporting area and being located above the channel area, the gate beam being substantially opaque and flexible so as to perform progressive modulation of the light reaching the channel in accordance with its bending controlled by the difference of voltage between the gate and the bulk and causing the beam to bend and to come closer to the surface of the channel. A process for manufacturing a light Modulating sensing MOSFET transistor is also provided.

Abstract: A nitride semiconductor device comprises: a laminated body; a first and second main electrode provided in a second and third region, respectively, adjacent to either end of the first region on the major surface of the laminated body; and a third main electrode. The laminated body includes a first semiconductor layer of a nitride semiconductor and a second semiconductor layer of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer, the second semiconductor layer being provided on the first semiconductor layer. The third main electrode is provided on the major surface of the laminated body and opposite to the control electrode across the second main electrode.

Abstract: A method of forming an electronic device on a metal substrate deposits a first seed layer of a first metal on at least one master surface with a roughness less than 400 nm. A supporting metal layer is bonded to the first seed layer to form the metal substrate 10. The metal substrate is removed from the master surface, and at least one electronic device is formed on the seed layer of the metal substrate.

Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.

Abstract: A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.

Abstract: A method of using helium to create ultra shallow junctions is disclosed. A pre-implantation amorphization using helium has significant advantages. For example, it has been shown that dopants will penetrate the substrate only to the amorphous-crystalline interface, and no further. Therefore, by properly determining the implant energy of helium, it is possible to exactly determine the junction depth. Increased doses of dopant simply reduce the substrate resistance with no effect on junction depth. Furthermore, the lateral straggle of helium is related to the implant energy and the dose rate of the helium PAI, therefore lateral diffusion can also be determined based on the implant energy and dose rate of the helium PAI. Thus, dopant may be precisely implanted beneath a sidewall spacer, or other obstruction.

Abstract: A quantum well is formed in a substrate to define a hub, ports extending from the hub, and a deflective structure in the hub. Electrons move through the hub and ports according to the ballistic electron effect. Gates control the movement of the electrons, causing them to be incident on the deflective structure on one side or the other, thus controlling the direction in which they are deflected and the port through which they pass.

Abstract: A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.

Abstract: A resistor structure includes a substrate, a well of a predetermined conductive type positioned in the substrate, a gate structure positioned on the substrate, a first doping region of the predetermined conductive type positioned at a first side of the gate structure, a second doping region of the predetermined conductive type positioned at a second side of the gate structure. The predetermined conductive type can be P type or N type. A fabricating process of the resistor can be integrated into a conventional MOS transistor fabricating process. Moreover, the resistor has better heat dissipation than conventional resistors.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device having a thyristor formed by joining a first p-type semiconductor layer, a first n-type semiconductor layer, a second p-type semiconductor layer, and a second n-type semiconductor layer in order, the method including the steps of: forming the second p-type semiconductor layer including a p-type impurity in a surface layer of a semiconductor substrate; forming the first n-type semiconductor layer including an n-type impurity on the semiconductor substrate including the second p-type semiconductor layer by epitaxial growth; forming a non-doped semiconductor layer on the first n-type semiconductor layer by epitaxial growth; and forming the first p-type semiconductor layer including a p-type impurity on the non-doped semiconductor layer by epitaxial growth.

Abstract: A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.

Abstract: A quantum well is formed in a substrate to define a hub, ports extending from the hub, and a deflective structure in the hub. Electrons move through the hub and ports according to the ballistic electron effect. Gates control the movement of the electrons, causing them to be incident on the deflective structure on one side or the other, thus controlling the direction in which they are deflected and the port through which they pass.

Abstract: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

Abstract: A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1?xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1?N; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

Abstract: The present invention provides a GaN based DHFET that helps confine the 2DEG to the channel layer, and reduces the 2DHG. The present invention provides a GaN DHFET having a channel layer comprising GaN and a buffer layer comprising AlxGa1?xN. The Al content in the buffer layer is specifically chosen based on the thickness of the channel layer using a graph. By choosing the Al content in the buffer layer and thickness of the channel layer in accordance with the graph provided in the present invention, the ability of the buffer layer to help confine the 2DEG to the channel layer is improved.

Abstract: A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.