Multi-step Process For The Manufacture Of Unipolar Device (epo) Patents (Class 257/E21.394)

  • Patent number: 8877575
    Abstract: The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: November 4, 2014
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Mieno Fumitake
  • Publication number: 20130187160
    Abstract: An integrated circuit includes a junction field effect transistor (JFET) and a power metal oxide semiconductor field effect transistor (MOSFET) on a same substrate. The integrated circuit includes a drain sense terminal for sensing the drain of the power MOSFET through the JFET. The JFET protects a controller or other electrical circuit coupled to the drain sense terminal from high voltage that may be present on the drain of the power MOSFET. The JFET and the power MOSFET share a same drift region, which includes an epitaxial layer formed on the substrate. The integrated circuit may be packaged in a four terminal small outline integrated circuit (SOIC) package. The integrated circuit may be employed in a variety of applications including as an ideal diode.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Inventor: Tiesheng LI
  • Publication number: 20130168741
    Abstract: The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.
    Type: Application
    Filed: September 25, 2012
    Publication date: July 4, 2013
    Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (Beijing), Semiconductor Manufacturing International Corporation (Shanghai)
    Inventors: Semiconductor Manufacturing International (Shanghai), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (Beijing)
  • Publication number: 20120302026
    Abstract: A method for forming a transistor includes providing a substrate, forming a well region in the substrate, and forming a gate structure on a surface of the well region. The gate structure includes a gate oxide layer on the surface of the well region and a gate on the gate oxide layer. The method further includes forming source/drain regions in the substrate at opposite sides of the gate structure and performing an ion doping to the substrate to adjust a threshold voltage. The ion doping is performed after the source/drain regions are formed to reduce the impact to the diffusion of the ions caused by heat treatments performed before the ion doping. The method further includes heating the substrate after the ion doping at a temperature from about 400° C. to about 500° C.
    Type: Application
    Filed: October 14, 2011
    Publication date: November 29, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Meng ZHAO
  • Patent number: 8148217
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Sanae Ito, Takahisa Kanemura
  • Patent number: 8125023
    Abstract: In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: February 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ohta, Wataru Saito, Syotaro Ono, Munehisa Yabuzaki, Nana Hatano, Miho Watanabe
  • Patent number: 8120063
    Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Jack T. Kavalieros
  • Patent number: 8043904
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Sanae Ito, Takahisa Kanemura
  • Patent number: 8035141
    Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Abhishek Dube, Jinghong Li, Viorel Ontalus, Zhengmao Zhu
  • Publication number: 20100123133
    Abstract: A device comprising a channel for charge carriers comprising non-ferromagnetic semiconducting in which charge carriers exhibit spin-orbit coupling, a region of semiconducting material of opposite conductivity type to the channel and configured so as to form a junction with the channel for injecting spin-polarised charge carriers into an end of the channel and at least one lead connected to the channel for measuring a transverse voltage across the channel.
    Type: Application
    Filed: August 21, 2009
    Publication date: May 20, 2010
    Inventors: Joerg Wunderlich, Tomas JUNGWIRTH, Andrew IRVINE, Jairo SINOVA
  • Patent number: 7662679
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: February 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Sanae Ito, Takahisa Kanemura
  • Patent number: 7598132
    Abstract: An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integration period, incident light causes electrons to be accumulated inside the buried accumulation region. The resistance characteristic of the channel region changes in response to a field created by the charges accumulated in the accumulation region. Thus, when a voltage is applied to one side of the channel, the current read out from the other side is characteristic of the amount of stored charges.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 6, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Dmitri Jerdev, Nail Khaliullin
  • Publication number: 20090191678
    Abstract: A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion.
    Type: Application
    Filed: April 6, 2009
    Publication date: July 30, 2009
    Inventors: Hamza Yilmaz, Daniel Calafut, Steven Sapp, Nathan Kraft, Ashok Challa
  • Patent number: 7494856
    Abstract: A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Ted R. White, Bich-Yen Nguyen
  • Patent number: 7224026
    Abstract: Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at least 100 nm long and less than 100 nm wide. The current-voltage characteristic of the diode devices are similar to a conventional diode, but both the threshold voltage (from 0V to a few volts) and the current level (from nA to ?A) can be tuned by orders of magnitude by changing the device geometry. Standard silicon wafers can be used as substrates. A full family of logic gates, such as OR, AND, and NOT, can be constructed based on this device solely by simply etching insulative lines in the substrate.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: May 29, 2007
    Assignee: The University of Manchester
    Inventors: Amin Song, Pär Omling