Thermal Treatment For Modifying Property Of Semiconductor Body, E.g., Annealing, Sintering (epo) Patents (Class 257/E21.497)
  • Patent number: 10141425
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Patent number: 9640678
    Abstract: The present invention concerns a method for the manufacture of the first layer of a back contact layer for thin-layer solar cells in superstrate configuration. In the prior art, this layer is deposited as a compound, for example as a layer of Sb2Te3. In accordance with the invention, however, a tellurium-rich surface layer of the cadmium telluride layer is produced, on which a first material is deposited which is capable of forming an electrically conductive second material with tellurium and of producing the second material by reaction of the first material and tellurium in the surface layer. The second material forms the first layer of the back contact layer.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: May 2, 2017
    Assignees: China Triumph International Engineering Co., Ltd., CTF Solar GmbH
    Inventors: Bastian Siepchen, Bettina Späth, Shou Peng
  • Patent number: 9570317
    Abstract: A microelectronic method for etching a layer to be etched, including: modifying the layer to be etched from a surface of the layer to be etched and over a depth corresponding to at least a portion of thickness of the layer to be etched to form a film, with the modifying including implanting light ions into the layer to be etched; and removing the film includes a selective etching of the film relative to at least one layer underlying the film.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 14, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE JOSEPH FOURIER
    Inventors: Nicolas Posseme, Olivier Joubert, Laurent Vallier
  • Patent number: 9018021
    Abstract: A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 28, 2015
    Assignee: Siltronic AG
    Inventor: Georg Brenninger
  • Patent number: 8946894
    Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: February 3, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Tarak A. Railkar, Deep C. Dumka
  • Patent number: 8854614
    Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Kang, Taegon Kim, Hanmei Choi, Eunyoung Jo, Gonsu Kang, Sungho Kang, Sungho Heo
  • Patent number: 8835333
    Abstract: A heat treatment method of the present invention includes mounting a plurality of semiconductor wafers upright on a treatment boat in parallel to each other, inserting the treatment boat in a space above an injector located in a tube to be oriented to plane surfaces of the semiconductor wafers in parallel to an extending direction of the tube, and heating the tube while continuously supplying source gas into the tube through openings of the injector.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: September 16, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Narihito Ota, Kunihiko Nishimura
  • Patent number: 8796687
    Abstract: A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Mallanagouda Dyamanagouda Patil, Lili Tian, Natesan Venkataraman
  • Patent number: 8603850
    Abstract: To provide a method for manufacturing a solar cell, whereby solar cells can be mass-produced by a simple process at low cost. A first conductivity-type silicon powder (11) is prepared, a silicon powder layer (11a) is formed by disposing the powder in the form of a layer, the powder layer is melted by heating the powder layer to the melting point of silicon or higher, and a first conductivity-type silicon layer (11b) is formed by cooling the melted layer. A second conductivity-type silicon powder (12) is prepared, a second conductivity-type silicon powder layer (12a) is formed by disposing the powder in the form of a layer on the first conductivity-type silicon layer (11b), the powder layer is melted by heating the powder layer to the melting point of silicon or higher, and a second conductivity-type silicon layer (12b) is formed by cooling the melted layer.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 10, 2013
    Assignee: Sanki Dengyo Co., Ltd.
    Inventors: Hiroaki Oka, Nariaki Oka
  • Patent number: 8575014
    Abstract: The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James J. Chambers, Mark R. Visokay
  • Patent number: 8546805
    Abstract: Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings the wafer surface temperature up to the annealing temperature. The anneal laser beam can have a different wavelength, or the same wavelength but different orientation relative to the wafer surface. Reflectivity maps of the wafer surface at the preheat and anneal wavelengths are measured and used to select first and second intensities that ensure good anneal temperature uniformity as a function of wafer position.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: October 1, 2013
    Assignee: Ultratech, Inc.
    Inventors: Xiaohua Shen, Yun Wang, Xiaoru Wang
  • Patent number: 8524518
    Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Calvin Wade Sheen
  • Patent number: 8518838
    Abstract: Methods used to perform an annealing process on desired regions of a substrate are disclosed. In one embodiment, an amount of energy is delivered to the surface of the substrate to preferentially melt certain desired regions of the substrate to remove unwanted damage created from prior processing steps (e.g., crystal damage from implant processes), more evenly distribute dopants in various regions of the substrate, and/or activate various regions of the substrate. The preferential melting processes will allow more uniform distribution of the dopants in the melted region, due to the increased diffusion rate and solubility of the dopant atoms in the molten region of the substrate. The creation of a melted region thus allows: 1) the dopant atoms to redistribute more uniformly, 2) defects created in prior processing steps to be removed, and 3) regions that have hyper-abrupt dopant concentrations to be formed.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 27, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Paul Carey, Aaron Muir Hunter, Dean Jennings, Abhilash J. Mayur, Stephen Moffatt, William Schaffer, Timothy N. Thomas, Mark Yam
  • Patent number: 8501521
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a copper species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 6, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8486753
    Abstract: Disclosed are a patterning method of a metal oxide thin film using nanoimprinting, and a manufacturing method of a light emitting diode (LED). The method for forming a metal oxide thin film pattern using nanoimprinting includes: coating a photosensitive metal-organic material precursor solution on a substrate; preparing a mold patterned to have a protrusion and depression structure; pressurizing the photosensitive metal-organic material precursor coating layer with the patterned mold; forming a cured metal oxide thin film pattern by heating the pressurized photosensitive metal-organic material precursor coating layer or by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer while being heated; and removing the patterned mold from the metal oxide thin film pattern, and selectively further includes annealing the metal oxide thin film pattern.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: July 16, 2013
    Assignee: Korea Institute of Machinery and Materials
    Inventors: Hyeong Ho Park, Jun Ho Jeong, Ki Don Kim, Dae Geun Choi, Jun Hyuk Choi, Ji Hye Lee, Soon Won Lee
  • Patent number: 8476104
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region, forming a first electrode layer overlying the surface region, forming a copper layer overlying the first electrode layer and forming an indium layer overlying the copper layer to form a multi-layered structure. The multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material having a copper sulfide surface region. The thickness of the copper sulfide material is selectively removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 2, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8461061
    Abstract: A method of supporting a plurality of planar substrates in a tube shaped furnace for conducting a thermal treatment process is disclosed. The method uses a boat fixture having a base frame including two length portions and a first width portion, a second width portion, and one or more middle members connected between the two length portions. Additionally, the method includes mounting a removable first grooved rod respectively on the first width portion, the second width portion, and each of the one or more middle members, each first grooved rod having a first plurality of grooves characterized by a first spatial configuration. The method further includes inserting one or two substrates of a plurality of planar substrates into each groove in the boat fixture separated by a distance.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: June 11, 2013
    Assignee: Stion Corporation
    Inventors: Paul Alexander, Jurg Schmitzberger, Ashish Tandon, Robert D. Wieting
  • Patent number: 8435826
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region and forming a first electrode layer overlying the surface region. The method forms a bulk copper indium disulfide material from a multi-layered structure comprising a copper species, an indium species, and a sulfur species overlying the first electrode layer. The bulk copper indium disulfide material comprises one or more portions of a copper poor copper indium disulfide material, a copper poor surface regions, and one or more portions of a sulfur deficient copper indium disulfide material characterized by at least a CuInS2-x species, where 0<x<2. The copper poor surface and one or more portions of the copper poor copper indium disulfide material are subjected to a sodium species derived from a sodium sulfide material to convert the copper poor surface from an n-type characteristic to a p-type characteristic.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 7, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Publication number: 20130099237
    Abstract: Hydrogen concentration and oxygen vacancies in an oxide semiconductor film are reduced. Reliability of a semiconductor device which includes a transistor using an oxide semiconductor film is improved. One embodiment of the present invention is a semiconductor device which includes a base insulating film; an oxide semiconductor film formed over the base insulating film; a gate insulating film formed over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film provided therebetween. The base insulating film shows a signal at a g value of 2.01 by electron spin resonance. The oxide semiconductor film does not show a signal at a g value of 1.93 by electron spin resonance.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 25, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Patent number: 8420554
    Abstract: A wafer support ring and a method of using the same are disclosed herein. The support ring supports a wafer during a first processing operation. A top surface of the support ring is in contact with a first plurality of locations on a surface of the wafer during the first processing operation. A second wafer support structure is used to support the wafer during a second processing operation. A top surface of the second wafer support structure is in contact with a second, different plurality of locations on the surface of the wafer during the second processing operation. The wafer support ring may also have an outer lip disposed about an outer periphery of the support ring that has a depth such that it does not form part of the top surface of the support ring.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: April 16, 2013
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Brian Lawrence Gilmore
  • Patent number: 8420981
    Abstract: A substrate thermal processing system. The system has at least one substrate holding module having a housing configured for holding an isolated environment therein. A substrate heater is located in the housing and has a substrate heating surface. A substrate cooler is located in the housing and having a substrate cooling surface. A gas feed opening into the housing and feeding inert or reducing gas into the housing when the substrate is heated by the heating surface. A gas restrictor is within the housing restricting the fed gas between the substrate heating surface and a surrounding atmospheric region substantially surrounding the substrate heating surface in the housing and forming an aperture through which the fed gas communicates with the atmospheric region.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: April 16, 2013
    Assignee: Tel Nexx, Inc.
    Inventors: Daniel Goodman, Arthur Keigler, David G. Guarnaccia, Matthew R. Jeffers
  • Patent number: 8394662
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: March 12, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8383441
    Abstract: Methods for manufacturing micromachined devices and the devices obtained are disclosed. In one embodiment, the method comprises providing a structural layer comprising an amorphous semiconductor material, forming a shielding layer on a first portion of the structural layer and leaving exposed a second portion of the structural layer, and annealing the second portion using a first fluence. The method further comprises removing the shielding layer, and annealing the first portion and the second portion using a second fluence that is less than half the first fluence. In an embodiment, the device comprises a substrate layer, an underlying layer formed on the substrate layer, and a sacrificial layer formed on only a portion of the underlying layer. The device further comprises a structural layer that is in contact with the underlying layer and comprises a first region annealed using a first fluence and a second region annealed using a second fluence.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: February 26, 2013
    Assignees: IMEC, American University Cairo, Katholieke Universiteit
    Inventors: Joumana El Rifai, Ann Witvrouw, Ahmed Abdel Aziz, Sherif Sedky
  • Patent number: 8293643
    Abstract: A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., John M. Cotte, Kathryn C. Fisher, Laura L. Kosbar, Christian Lavoie, Zhu Liu, Kenneth P. Rodbell, Xiaoyan Shao
  • Patent number: 8237202
    Abstract: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kuk Jeong, Andrew-tae Kim, Dong-suk Shin
  • Patent number: 8232552
    Abstract: This invention provides an amorphous oxide semiconductor thin film, which is insoluble in a phosphoric acid-based etching solution and is soluble in an oxalic acid-based etching solution by optimizing the amounts of indium, tin, and zinc, a method of producing the amorphous oxide semiconductor thin film, etc. An image display device (1) comprises a glass substrate (10), a liquid crystal (40) as a light control element, a bottom gate-type thin film transistor (1) for driving the liquid crystal (40), a pixel electrode (30), and an opposing electrode (50). The amorphous oxide semiconductor thin film (2) in the bottom gate-type thin film transistor (1) has a carrier density of less than 10+18 cm?3, is insoluble in a phosphoric acid-based etching liquid, and is soluble in an oxalic acid-based etching liquid.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: July 31, 2012
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue
  • Patent number: 8187901
    Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 29, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Calvin Wade Sheen
  • Publication number: 20120115254
    Abstract: A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar heater zone includes one or more heater elements made of an insulator-conductor composite. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic sheets having planar heater zones, power supply lines, power return lines and vias.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 10, 2012
    Applicant: Lam Research Corporation
    Inventor: Harmeet Singh
  • Patent number: 8169059
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Oliver Nagy
  • Publication number: 20120070936
    Abstract: In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed.
    Type: Application
    Filed: June 3, 2011
    Publication date: March 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Supratik Guha, David B. Mitzi, Teodor K. Todorov, Kejia Wang
  • Patent number: 8138061
    Abstract: The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, John A. Ott, Alexander Reznicek, Devendra K. Sadana, Katherine L. Saenger
  • Patent number: 8129224
    Abstract: A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Siva P Gurrum, Kapil H Sahasrabudhe, Vikas Gupta
  • Patent number: 8093144
    Abstract: A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form the feature.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: January 10, 2012
    Assignee: Massachusetts Institute of Technology
    Inventors: Joseph M. Jacobson, David Kong, Vikas Anant, Ashley Salomon, Saul Griffith, Will DelHagen, Vikrant Agnihotri
  • Patent number: 8053330
    Abstract: The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials.
    Type: Grant
    Filed: August 8, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, John A. Ott, Alexander Reznicek, Devendra K. Sadana, Katherine L. Saenger
  • Publication number: 20110269316
    Abstract: A wafer support ring and a method of using the same are disclosed herein. The support ring supports a wafer during a first processing operation. A top surface of the support ring is in contact with a first plurality of locations on a surface of the wafer during the first processing operation. A second wafer support structure is used to support the wafer during a second processing operation. A top surface of the second wafer support structure is in contact with a second, different plurality of locations on the surface of the wafer during the second processing operation. The wafer support ring may also have an outer lip disposed about an outer periphery of the support ring that has a depth such that it does not form part of the top surface of the support ring.
    Type: Application
    Filed: May 3, 2010
    Publication date: November 3, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: Brian Lawrence Gilmore
  • Patent number: 8030189
    Abstract: A method for maintaining a smooth surface of crystallizable material is disclosed. First, a substrate is provided. A target material layer is then formed on the substrate, with the target material being a crystallizable material. A protecting layer is subsequently formed on the target material layer. Next, an annealing treatment is implemented, with the surface of the target material layer, facing the protecting layer, being maintained in its original smooth state by the pressure and/or adhesion of the protecting layer. Finally, the protecting layer is removed to leave an open and smooth surface of the processed crystallizable material.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: October 4, 2011
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Cha-Hsin Chao, Wen-Han Lin
  • Patent number: 8030099
    Abstract: The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such on-chip interconnects, is provided. Measurements are performed on the test structure under test conditions for current density and temperature. The test structure is arranged such that failure of one of the on-chip interconnects within the parallel connection changes the test conditions for at least one of the other individual on-chip interconnects of the parallel connection. From these measurements, time to failure characteristics are determined, whereby the change in the test conditions is compensated for.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: October 4, 2011
    Assignees: IMEC, Universiteit Hasselt
    Inventor: Ward De Ceuninck
  • Patent number: 8012873
    Abstract: A method for annealing a semiconductor device having at least one polysilicon region formed on a substrate, comprises growing dielectric material on the substrate adjacent to the polysilicon region. The method continues by polishing a surface of the dielectric material and by depositing a layer of a semi-transparent material on both the surface of the dielectric material and the surface of the polysilicon region. The method concludes by annealing the semiconductor device.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: September 6, 2011
    Assignee: SuVolta, Inc.
    Inventor: Nicholas K. Eib
  • Patent number: 8008171
    Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: August 30, 2011
    Assignees: Tatung Company, Tatung University
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Patent number: 7998848
    Abstract: The laser beam with a wavelength having a higher energy than the band gap energy of the material forming the carrier moving layer is irradiated to activate the impurities contained in the constituent layer of the field effect transistor in the method of producing the field effect transistor. The method of the invention does not apply the heating of the substrate or the sample stage to raise the temperature of the semiconductor layer using the thermal conductivity so as to activate the impurities. Thus, the implanted impurities can be activated without deteriorating the performance of the device and reliability.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: August 16, 2011
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yuki Niiyama, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Hiroshi Kambayashi, Takehiko Nomura
  • Publication number: 20110180886
    Abstract: Methods for manufacturing micromachined devices and the devices obtained are disclosed. In one embodiment, the method comprises providing a structural layer comprising an amorphous semiconductor material, forming a shielding layer on a first portion of the structural layer and leaving exposed a second portion of the structural layer, and annealing the second portion using a first fluence. The method further comprises removing the shielding layer, and annealing the first portion and the second portion using a second fluence that is less than half the first fluence. In an embodiment, the device comprises a substrate layer, an underlying layer formed on the substrate layer, and a sacrificial layer formed on only a portion of the underlying layer. The device further comprises a structural layer that is in contact with the underlying layer and comprises a first region annealed using a first fluence and a second region annealed using a second fluence.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 28, 2011
    Applicants: IMEC, AMERICAN UNIVERSITY IN CAIRO, KATHOLIEKE UNIVERSITEIT LEUVEN, K.U. LEUVEN R&D
    Inventors: Joumana El Rifai, Ann Witvrouw, Ahmed Kamal Said Abdel Aziz, Sherif Sedky
  • Patent number: 7977217
    Abstract: A method of crystallizing silicon including preparing a substrate having an amorphous silicon film formed thereon, aligning a mask having a first energy region and a second energy region over a first region of the amorphous silicon film formed on the substrate, irradiating a laser beam through the first and second energy regions of the mask onto the first region of the amorphous silicon film, crystallizing the first region of the amorphous silicon film by irradiating the laser beam through the first energy region of the mask, and activating the crystallized first region by irradiating the laser beam through the second energy region.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: July 12, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: JaeSung You
  • Publication number: 20110114623
    Abstract: A substrate thermal processing system. The system has at least one substrate holding module having a housing configured for holding an isolated environment therein. A substrate heater is located in the housing and has a substrate heating surface. A substrate cooler is located in the housing and having a substrate cooling surface. A gas feed opening into the housing and feeding inert or reducing gas into the housing when the substrate is heated by the heating surface. A gas restrictor is within the housing restricting the fed gas between the substrate heating surface and a surrounding atmospheric region substantially surrounding the substrate heating surface in the housing and forming an aperture through which the fed gas communicates with the atmospheric region.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 19, 2011
    Applicant: Nexx Systems, Inc
    Inventors: Daniel Goodman, Arthur Keigler, David G. Guarnaccia, Matthew R. Jeffers
  • Patent number: 7939456
    Abstract: A microwave heating system comprises a microwave applicator cavity; a microwave power supply to deliver power to the applicator cavity; a dielectric support to support a generally planar workpiece; a dielectric gas manifold to supply a controlled flow of inert gas proximate to the periphery of the workpiece to provide differential cooling to the edge relative to the center; a first temperature measuring device configured to measure the temperature near the center of the workpiece; and, a second temperature measuring device configured to measure the temperature near the edge of the workpiece. The gas flow is controlled to minimize the temperature difference from center to edge, and may be recipe driven or controlled in real time, based on the two temperature measurements. The method is particularly useful for monolithic semiconductor wafers, various semiconducting films on substrates, and dielectric films on semiconducting wafers.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: May 10, 2011
    Assignee: Lambda Technologies, Inc.
    Inventors: Iftikhar Ahmad, Keith R. Hicks
  • Patent number: 7923378
    Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: April 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa
  • Patent number: 7906402
    Abstract: Methods for compensating for a thermal profile in a substrate heating process are provided herein. In some embodiments, a method of processing a substrate includes determining an initial thermal profile of a substrate that would result from subjecting the substrate to a process; determining a compensatory thermal profile based upon the initial thermal profile and a desired thermal profile; imposing the compensatory thermal profile on the substrate prior to performing the process on the substrate; and performing the process to create the desired thermal profile on the substrate. The initial substrate thermal profile can also be compensated for by adjusting a local mass heated per unit area, a local heat capacity per unit area, or an absorptivity or reflectivity of a component proximate the substrate prior to performing the process. Heat provided by an edge ring to the substrate may be controlled prior to or during the substrate heating process.
    Type: Grant
    Filed: October 4, 2009
    Date of Patent: March 15, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Joseph M. Ranish, Bruce E. Adams
  • Patent number: 7902070
    Abstract: A method and system for producing a noble metal film includes the step of sputtering a noble metal on a substrate thus obtaining a film. The method and system further includes the step of subjecting the film to a thermal treatment, thus obtaining the noble metal film.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: March 8, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventors: Sabrina Conoci, Salvatore Petralia
  • Publication number: 20110049512
    Abstract: The invention provides a method for developing a thin film from oxide or silicate of hafnium nitride, and also provides asymmetric guanidinate coordinate compounds. The invention furthermore provides a method for producing an electronic circuit that includes a step for developing a thin film from oxide or silicate of hafnium nitride through the method of the invention.
    Type: Application
    Filed: March 16, 2009
    Publication date: March 3, 2011
    Inventors: Stéphane Daniele, Mohamad Eleter, Catherine Dubourdieu, Virginie Brize
  • Patent number: 7863204
    Abstract: A substrate treating device comprising a treatment chamber for storing and treating substrates and a heating device having a heating element and a heat insulator and heating the substrates in the treatment chamber by the heating element. The heating element is so formed that only its one end is held by a holding part, and a projection projected to the treatment chamber side at the intermediate part of the heating element and positioned in proximity to or in contact with the heating element is formed on the heat insulator. A pin with an enlarged part is passed through the heating element and the heat insulator at the intermediate part of the heating element and the enlarged part is positioned in proximity to or in contact with the heating element. The plurality of projections may be formed on the heat insulator and the pins may be disposed between these plurality of projections.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: January 4, 2011
    Assignees: Hitachi Kokusai Electric Inc., Teitokusha Co., Ltd.
    Inventors: Toshimitsu Miyata, Akira Hayashida, Masakazu Shimada, Kimio Kitamura, Kenji Tanaka
  • Publication number: 20100323532
    Abstract: The present invention generally describes one ore more methods that are used to perform an annealing process on desired regions of a substrate. In one embodiment, an amount of energy is delivered to the surface of the substrate to preferentially melt certain desired regions of the substrate to remove unwanted damage created from prior processing steps (e.g., crystal damage from implant processes), more evenly distribute dopants in various regions of the substrate, and/or activate various regions of the substrate. The preferential melting processes will allow more uniform distribution of the dopants in the melted region, due to the increased diffusion rate and solubility of the dopant atoms in the molten region of the substrate. The creation of a melted region thus allows: 1) the dopant atoms to redistribute more uniformly, 2) defects created in prior processing steps to be removed, and 3) regions that have hyper-abrupt dopant concentrations to be formed.
    Type: Application
    Filed: August 12, 2010
    Publication date: December 23, 2010
    Inventors: Paul Carey, Aaron Muir Hunter, Dean Jennings, Abhilash J. Mayur, Stephen Moffatt, William Schaffer, Timothy N. Thomas, Mark Yam