Device Having Semiconductor Body Other Than Carbon, Si, Ge, Sic, Se, Te, Cu 2 O, Cui, And Group Iii-v Compounds With Or Without Impurities, E.g., Doping Materials (epo) Patents (Class 257/E21.459)

  • Patent number: 9847480
    Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. A portion of the resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode embedded in the dielectric layer. A resistance variable layer disposed over the first electrode and a portion of the dielectric layer. A second electrode disposed over the resistance variable layer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo-Chi Tu
  • Patent number: 9450102
    Abstract: Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 5×1015/cm2 and less than or equal to 5×1016/cm2, or greater than or equal to 5×1015/cm2 and less than or equal to 3×1016/cm2.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Satoshi Toriumi, Kazuki Tanemura
  • Patent number: 9006040
    Abstract: A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chang Hsieh, Kong-Beng Thei
  • Patent number: 8987727
    Abstract: An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Patent number: 8987717
    Abstract: An organic light emitting diode (OLED) display is provided. The OLED display includes: a substrate; a first electrode on the substrate; a first pixel defining layer exposing at least a portion of the first electrode; a medium layer on the first pixel defining layer and the first electrode, the medium layer including a first region and a second region; a second pixel defining layer overlapping the first pixel defining layer with the first region therebetween; a light emission layer overlapping the first electrode with the first region therebetween; and a second electrode covering the second pixel defining layer and the light emission layer.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jin Goo Kang
  • Patent number: 8946894
    Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: February 3, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Tarak A. Railkar, Deep C. Dumka
  • Patent number: 8927985
    Abstract: A semiconductor device includes first and second conductive layers over an insulating surface, a first insulating layer over the first and second conductive layers, first and second oxide semiconductor layers over the first insulating layer, third and fourth conductive layers over the first oxide semiconductor layer, a second insulating layer over the third and fourth conductive layers, and a fifth conductive layer over the second insulating layer. In the semiconductor device, the third conductive layer is electrically connected to the second conductive layer, the fifth conductive layer is electrically connected to the fourth conductive layer, the first oxide semiconductor layer has a region overlapping with the first conductive layer, the second oxide semiconductor layer has a region overlapping with the fifth conductive layer, and the second oxide semiconductor layer has a region intersecting with the second conductive layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideki Matsukura
  • Patent number: 8907333
    Abstract: Composite of layers which comprises a dielectric layer and a layer which comprises pyrogenic zinc oxide and is bonded to the dielectric layer. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to the dielectric layer in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm, and the zinc oxide layer is dried and then treated at temperatures of less than 200° C. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to a substrate layer or a composite of substrate layers in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm to form a zinc oxide layer, and then the zinc oxide layer and the substrate layer are treated at temperatures of less than 200° C., and then a dielectric layer is applied to the zinc oxide layer. Field-effect transistor which has the composite of layers.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: December 9, 2014
    Assignees: Evonik Degussa GmbH, Forschungszentrum Karlsruhe GmbH
    Inventors: Frank-Martin Petrat, Heiko Thiem, Sven Hill, Andre Ebbers, Koshi Okamura, Roland Schmechel
  • Patent number: 8901552
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (?-Al2O3, ?-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or ?-Fe2O3) is used.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takayuki Inoue, Masashi Tsubuku, Kengo Akimoto, Akiharu Miyanaga
  • Patent number: 8883558
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Patent number: 8809852
    Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Patent number: 8785920
    Abstract: An amorphous oxide thin film containing amorphous oxide is exposed to an oxygen plasma generated by exciting an oxygen-containing gas in high frequency. The oxygen plasma is preferably generated under the condition that applied frequency is 1 kHz or more and 300 MHz or less and pressure is 5 Pa or more. The amorphous oxide thin film is preferably exposed by a sputtering method, ion-plating method, vacuum deposition method, sol-gel method or fine particle application method.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: July 22, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Kazuyoshi Inoue, Futoshi Utsuno, Katsunori Honda
  • Patent number: 8784699
    Abstract: An oxide including indium (In), gallium (Ga) and zinc (Zn), wherein diffraction peaks are observed at positions corresponding to incident angles (2?) of 7.0° to 8.4°, 30.6° to 32.0°, 33.8° to 35.8°, 53.5° to 56.5° and 56.5° to 59.5° in an X-ray diffraction measurement (CuK? rays), and one of diffraction peaks observed at positions corresponding to incident angles (2?) of 30.6° to 32.0° and 33.8° to 35.8° is a main peak and the other is a sub peak.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: July 22, 2014
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Masayuki Itose, Hirokazu Kawashima
  • Patent number: 8785242
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8753983
    Abstract: A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: June 17, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jin-Wook Jang, Lalgudi M. Mahalingam, Audel A. Sanchez, Lakshminarayan Viswanathan
  • Patent number: 8728860
    Abstract: Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8723173
    Abstract: The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Yoshiaki Ito
  • Patent number: 8697488
    Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 8697467
    Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: April 15, 2014
    Assignee: The Regents of the University of California
    Inventors: Ali Javey, Alexandra C. Ford, Johnny C. Ho
  • Patent number: 8691612
    Abstract: Provided is a method of enhancing thermoelectric performance by surrounding crystalline semiconductors with nanoparticles by contacting a bismuth telluride material with a silver salt under a substantially inert atmosphere and a temperature approximately near the silver salt decomposition temperature; and recovering a metallic bismuth decorated material comprising silver telluride crystal grains.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 8, 2014
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Hyun-Jung Kim, Sang Hyouk Choi, Glen C. King, Yeonjoon Park, Kunik Lee
  • Patent number: 8685787
    Abstract: One object is to have stable electrical characteristics and high reliability and to manufacture a semiconductor device including a semi-conductive oxide film. Film formation is performed by a sputtering method using a target in which gallium oxide is added to a material that is easy to volatilize compared to gallium when the material is heated at 400° C. to 700° C. like zinc, and a formed film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film and the oxide is crystallized. Further, a semi-conductive oxide film is deposited thereover, whereby a semi-conductive oxide having a crystal which succeeds a crystal structure of the oxide that is crystallized by heat treatment is formed.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8658463
    Abstract: A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 25, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Janice H. Nickel, Matthew D. Pickett
  • Patent number: 8623698
    Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 8617915
    Abstract: In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Supratik Guha, David B. Mitzi, Teodor K. Todorov, Kejia Wang
  • Publication number: 20130334631
    Abstract: Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely-directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random access memory (STT-MRAM) systems, and methods of fabrication.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Wayne I. Kinney, Witold Kula, Stephen J. Kramer
  • Patent number: 8597976
    Abstract: The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: December 3, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai
  • Publication number: 20130293286
    Abstract: A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Xia Li, Jung Pill Kim, Taehyun Kim
  • Patent number: 8552434
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Patent number: 8546797
    Abstract: In a ZnO based compound semiconductor device, nitrogen (N) doped (Mg)ZnO:N layer is inserted as a diffusion barrier layer 9 between a ZnO based n-type layer 3 to which n-type dopants are doped and an active layer 4 or a p-type layer 5. The diffusion barrier layer 9 prevents diffusion of the n-type dopants to the active layer 4 or the p-type layer 5. Crystalline quality of the active layer 4 of the ZnO based compound semiconductor device is not deteriorated by the diffusion of the n-type dopants.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: October 1, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Tomofumi Yamamuro, Hiroyuki Kato, Akio Ogawa
  • Patent number: 8546182
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: October 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Patent number: 8513054
    Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 8513743
    Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8481363
    Abstract: The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, a buffer layer over the source electrode layer and the drain electrode layer, and a semiconductor layer over the buffer layer. A part of the semiconductor layer overlapping with the gate electrode layer is over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer contains a metal oxide having n-type conductivity. The semiconductor layer and the source and drain electrode layers are electrically connected to each other through the buffer layer.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8481362
    Abstract: The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor that includes a zinc oxide (ZnO series) electrode having one or more of Si, Mo, and W as a source electrode and a drain electrode, and a method of manufacturing the same.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: July 9, 2013
    Assignee: LG Chem, Ltd.
    Inventor: Jung-Hyoung Lee
  • Patent number: 8471252
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: June 25, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8450835
    Abstract: One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: May 28, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Xiying Chen, Mark H. Clark, S. Brad Herner, Tanmay Kumar
  • Patent number: 8450145
    Abstract: A first opening and a second opening are formed at the same time over a first metal wiring and a second metal wiring, respectively which are provided as the same layer on a substrate on which a transistor for selecting a memory cell is formed. Then, a variable resistor and an upper electrode are deposited on a whole surface so as to completely fill the first opening with the upper electrode but not to completely fill the second opening with it. Thereafter, a variable resistive element is formed in the first opening and a via hole to connect to the third metal wiring (bit line), in the second opening, at the same time, by performing back-etching until a surface of the second metal wiring is exposed at a bottom of the second opening.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: May 28, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yushi Inoue
  • Patent number: 8394671
    Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Publication number: 20130056723
    Abstract: The present disclosure provides for electronic devices that use low cost, conductive materials as transparent conductors. The devices contain corrosion preventative conductive polymer layers and conductive innerlayer barriers that separate corrosive electrolyte from the conductors which are prone to corrosion and dissolution, while providing an uninterrupted electrical circuit. The present disclosure also allows for the use of layers which have been applied from aqueous media thereby reducing both the cost and the environmental impact of the electronic devices. Methods of manufacture are also provided.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Applicant: WARNER BABCOCK INSTITUTE FOR GREEN CHEMISTRY
    Inventors: John C. Warner, Michael S. Viola
  • Patent number: 8389326
    Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 8377718
    Abstract: A method of forming a crystalline Pr1-xCaxMnO3 (PCMO) material includes forming an amorphous PCMO material, crystallizing the amorphous PCMO material, and removing a portion of the crystalline PCMO material. A semiconductor structure including the crystalline PCMO material is also disclosed where the crystalline PCMO material has a thickness of less than about 50 nm. A method of forming a semiconductor device structure is also disclosed.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: February 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
  • Publication number: 20130009128
    Abstract: A nanoscale switching device has an active region containing a switching material. The switching device has a first electrode and a second electrode with nanoscale widths, and the active region is disposed between the first and second electrodes. A protective cladding layer surrounds the active region. The protective cladding layer is formed of a cladding material unreactive to the switching material. An interlayer isolation layer formed of a dielectric material is disposed between the first and second electrodes and outside the protective cladding layer.
    Type: Application
    Filed: March 31, 2010
    Publication date: January 10, 2013
    Inventors: Gilberto Ribeiro, Janice H Nickel, Jianhua YA Yang
  • Patent number: 8344387
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Publication number: 20120319104
    Abstract: Provided is a method of producing a circuit board of which the aperture ratio is increased. The method of producing a circuit board of the present invention is a method of producing a circuit board that includes a thin film transistor, the thin film transistor including an oxide semiconductor layer, the method including steps of: forming the oxide semiconductor layer; and converting the oxide semiconductor layer into a conductive form.
    Type: Application
    Filed: November 4, 2010
    Publication date: December 20, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihito Hara, Yukinobu Nakata
  • Publication number: 20120286260
    Abstract: A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kosei NODA, Shunpei YAMAZAKI, Tatsuya HONDA, Yusuke SEKINE, Hiroyuki TOMATSU
  • Publication number: 20120281451
    Abstract: The invention provides a Ferro-RRAM, a method of operating the Ferro-RRAM, and a method of fabricating the Ferro-RRAM, and pertains to the technical field of memory. The Ferro-RRAM comprises an upper electrode, a lower electrode, and a ferroelectric semiconducting thin-film layer provided between the upper electrode and the lower electrode and serving as a storage function layer; wherein the ferroelectric semiconducting thin-film layer is operable to generate a diode conduction characteristic by ferroelectric domain reorientation, and is operable to modulate the diode conduction characteristic by variation of the ferroelectric domain orientation; the Ferro-RRAM stores information according to variation of modulation of the diode conduction characteristic. The Ferro-RRAM has such characteristics of being simple in structure and fabrication, non-destructive readout and nonvolatile storage.
    Type: Application
    Filed: January 12, 2011
    Publication date: November 8, 2012
    Applicant: FUDAN UNIVERSITY
    Inventors: Anquan Jiang, Xiaobing Liu
  • Publication number: 20120225513
    Abstract: Provided is a method of enhancing thermoelectric performance by surrounding crystalline semiconductors with nanoparticles by contacting a bismuth telluride material with a silver salt under a substantially inert atmosphere and a temperature approximately near the silver salt decomposition temperature; and recovering a metallic bismuth decorated material comprising silver telluride crystal grains.
    Type: Application
    Filed: March 5, 2012
    Publication date: September 6, 2012
    Applicant: U. S.A. as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Hyun-Jung Kim, Sang Hyouk Choi, Glen C. King, Yeonjoon Park, Kunik Lee
  • Publication number: 20120187399
    Abstract: Disclosed is a substrate for a flexible device which, when a TFT is produced on a flexible substrate in which a metal layer and a polyimide layer are laminated, can suppress deterioration of the electrical performance of the TFT due to the surface irregularities of the metal foil surface and can suppress detachment or cracks of the TFT. Also disclosed is a substrate for a thin film element which has excellent surface smoothness and is capable of suppressing deterioration of the characteristics of thin film elements. Also disclosed are methods for manufacturing substrates for thin film elements.
    Type: Application
    Filed: September 29, 2010
    Publication date: July 26, 2012
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Shunji Fukuda, Katsuya Sakayori, Keita Arihara, Koji Ichimura, Kei Amagai
  • Patent number: 8227359
    Abstract: A method for manufacturing a Group III nitride semiconductor layer according to the present invention includes a sputtering step of disposing a substrate and a target containing a Group III element in a chamber, introducing a gas for formation of a plasma in the chamber and forming a Group III nitride semiconductor layer added with Si as a dopant on the substrate by a reactive sputtering method, wherein a Si hydride is added in the gas for formation of a plasma.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 24, 2012
    Assignee: Showa Denko K.K.
    Inventors: Yasunori Yokoyama, Hisayuki Miki
  • Publication number: 20120180663
    Abstract: Embodiments of the present invention provide a vacuum trap labyrinth with improved trapping characteristics. The vacuum trap labyrinth comprised of an inner part and an outer part that fit together while in use, and come apart for easy cleaning during maintenance. The vacuum trap labyrinth is installed in a catchpot. In one embodiment, an O-ring is used to seal off an area of the catchpot to facilitate a visual inspection.
    Type: Application
    Filed: January 18, 2011
    Publication date: July 19, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Charles Easton, Joseph P. DeGeorge