Treatment Of Semiconductor Body Using Process Other Than Electromagnetic Radiation (epo) Patents (Class 257/E21.482)
  • Patent number: 10153338
    Abstract: A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 8927440
    Abstract: A film deposition apparatus that laminates layers of reaction product by repeating cycles of sequentially supplying process gases that mutually reacts in a vacuum atmosphere includes a turntable receiving a substrate, process gas supplying portions supplying mutually different process gases to separated areas arranged in peripheral directions, and a separation gas supplying portion separating the process gases, wherein at least one process gas supplying portion extends between peripheral and central portions of the turntable and includes a gas nozzle discharging one process gas toward the turntable and a current plate provided on an upstream side to allow the separation gas to flow onto its upper surface, wherein a gap between the current plate and the turntable is gradually decreased from a central side of the turntable to a peripheral side of the turntable, and the gap is smaller on the peripheral side by 1 mm or greater.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: January 6, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Shigehiro Miura
  • Patent number: 8786089
    Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventors: Kazuto Watanabe, Atsushi Matsushita, Hiroshi Horikoshi, Iwao Sugiura, Yuuji Nishimura, Syota Yamabata
  • Patent number: 8741740
    Abstract: An SOI substrate is manufactured by forming an embrittled layer in a bond substrate by increasing the dose of hydrogen ions in the formation of the embrittled layer to a value more than the dose of hydrogen ions of the lower limit for separation of the bond substrate, separating the bond substrate attached to the base substrate, forming an SOI substrate in which a single crystal semiconductor film is formed over the base substrate, and irradiating a surface of the single crystal semiconductor film with laser light.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hajime Tokunaga
  • Patent number: 8551880
    Abstract: A method for fabricating a semiconductor device is described. A substrate is provided having a patterned dielectric layer disposed thereon. A trench is formed in the dielectric layer. The surfaces of the trench are treated with an ammonia-based plasma process. A metal layer is then formed in the trench.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: October 8, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Amit Khandelwal, Linh H. Thanh
  • Patent number: 8528499
    Abstract: Disclosed is a substrate processing apparatus and method. The substrate processing apparatus includes a process chamber (10) providing an internal space, in which a process is carried out onto a substrate; a support member (30) installed in the process chamber (10) to support the substrate; and a shower head (20) located above the support member (30) to supply a source gas toward the support member (30), wherein the shower head (20) includes a first injection surface (24) located at a position separated from the upper surface of the substrate by a first distance, and provided with outlets of first injection holes (24a) to inject the source gas; and a second injection surface (26) located at a position separated from the upper surface of the substrate by a second distance being different from the first distance, and provided with outlets of second injection holes (26a) to inject the source gas.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: September 10, 2013
    Assignee: Eugene Technology Co., Ltd.
    Inventors: Sung-Tae Je, Il-Kwang Yang, Chan-Yong Park
  • Patent number: 8507307
    Abstract: The present invention relates to devices, particularly photovoltaic devices, incorporating Group IIB/VA semiconductors such phosphides, arsenides, and/or antimonides of one or more of Zn and/or Cd. In particular, the present invention relates to methodologies, resultant products, and precursors thereof in which electronic performance of the semiconductor material is improved by causing the Group IIB/VA semiconductor material to react with at least one metal-containing species (hereinafter co-reactive species) that is sufficiently co-reactive with at least one Group VA species incorporated into the Group IIB/VA semiconductor as a lattice substituent (recognizing that the same and/or another Group VA species also optionally may be incorporated into the Group IIB/VA semiconductor in other ways, e.g., as a dopant or the like).
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: August 13, 2013
    Assignees: Dow Global Technologies LLC, California Institute of Technology
    Inventors: Gregory M. Kimball, Marty W. DeGroot, Nathan S. Lewis, Harry A. Atwater
  • Patent number: 8445352
    Abstract: A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on the long-term reliability of a semiconductor device. In a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate, there is applied a metal contamination removal process, on a silicon carbide surface, including a step of oxidizing the silicon carbide surface and a step of removing a film primarily including silicon dioxide formed on the silicon carbide surface by the step.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: May 21, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Tomoyuki Someya
  • Patent number: 8431495
    Abstract: An apparatus and method are provided which allow the low cost patterned deposition of material onto a workpiece. A stencil mask, having chamfered edges is applied to the surface of the workpiece. The material is then deposited onto the workpiece, such as by PECVD. Because of the chamfered edges, the material thickness is much more uniform than is possible with traditional stencil masks. Stencil masks having a variety of cross sectional patterns are disclosed which improve deposition uniformity.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: April 30, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Helen Maynard, George Papasouliotis
  • Publication number: 20120299134
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 29, 2012
    Applicant: MagIC Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8318585
    Abstract: To facilitate bonding of articles at a low temperature without degrading electrical contact between the articles. An oxide film reducing treatment with hydrogen radicals is carried out for surfaces of lead-out electrodes (5) and bump electrodes (6) on the lead-out electrodes (5) of a semiconductor chip (2) and surfaces of lead-out electrodes (8) of an intermediate substrate (3), and, after that, the bump electrodes (6) of the semiconductor chip (2) and the lead-out electrodes (8) of the intermediate substrate (3) are aligned with each other. After that, a pressure is applied to bond the bump electrodes (6) and the lead-out electrodes (8).
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: November 27, 2012
    Assignees: Shinko Seiki Company, Limited
    Inventors: Yasuhide Ohno, Keisuke Taniguchi, Tatsuya Takeuchi, Taizo Hagihara
  • Patent number: 8298915
    Abstract: Method for forming a semi-conducting structure includes the formation of at least one part of a circuit or a component, in or on a superficial layer of a substrate, the substrate including a buried layer underneath the superficial layer, and an underlying layer serving as first support, a transfer of said substrate onto a handle substrate, and then an elimination of the first support, the formation of an electrically conducting or ground plane forming layer, on at least one part of said buried layer, the formation, on said electrically conducting or ground plane forming layer, of a bonding layer, a transfer of the structure obtained onto a second support and an elimination of said handle substrate.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: October 30, 2012
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventor: Bernard Aspar
  • Publication number: 20120202355
    Abstract: A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 9, 2012
    Applicant: Spansion LLC
    Inventors: Rinji Sugino, Bradley Marc Davis, Lei Xue, Kenichi Ohtsuka
  • Publication number: 20120193809
    Abstract: An integrated circuit device includes a bottom wafer having a first dielectric block and a first conductive block on the first dielectric block; at least one stacking wafer having a second dielectric block and at least one second conductive block on the second dielectric block, wherein the stacking wafers are bonded to the bottom wafer by an adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer; and a conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the conductive via is positioned within the first conductive block and the second conductive block.
    Type: Application
    Filed: February 1, 2011
    Publication date: August 2, 2012
    Applicant: Nanya Technology Corp.
    Inventor: Jui Hsuan Chung
  • Patent number: 8216945
    Abstract: A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: July 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Steven L. Prins, Brian K. Kirkpatrick, Amitabh Jain
  • Publication number: 20120164817
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Application
    Filed: March 5, 2012
    Publication date: June 28, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takeshi SHICHI, Junichi KOEZUKA, Hideto OHNUMA, Shunpei YAMAZAKI
  • Publication number: 20120153358
    Abstract: The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Ravi Shankar, Olivier Le Neel
  • Publication number: 20120021609
    Abstract: Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: NITIN H. PARBHOO, Spyridon Skordas
  • Publication number: 20120009798
    Abstract: An apparatus and method are provided which allow the low cost patterned deposition of material onto a workpiece. A stencil mask, having chamfered edges is applied to the surface of the workpiece. The material is then deposited onto the workpiece, such as by PECVD. Because of the chamfered edges, the material thickness is much more uniform than is possible with traditional stencil masks. Stencil masks having a variety of cross sectional patterns are disclosed which improve deposition uniformity.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Helen Maynard, George D. Papasouliotis
  • Patent number: 8084368
    Abstract: A barrier film made of a ZrB2 film is formed by use of a coating apparatus provided with plasma generation means including a coaxial resonant cavity and a microwave supply circuit for exciting the coaxial resonant cavity, the coaxial resonant cavity including spaced apart conductors provided around the periphery of a nonmetallic pipe for reactive gas introduction, the coaxial resonant cavity having an inner height equal to an integer multiple of one-half of the exciting wavelength, the plasma generation means being constructed such that a gas injected from one end of the nonmetallic pipe is excited into a plasma state by a microwave when the gas is in a region of the nonmetallic pipe which is not covered with the conductors and such that the gas in the plasma state is discharged from the other end of the nonmetallic pipe.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: December 27, 2011
    Assignee: Ulvac, Inc.
    Inventors: Masanobu Hatanaka, Michio Ishikawa, Kanako Tsumagari
  • Publication number: 20110279979
    Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Inventors: Nik Mirin, Tsai-Yu Huang, Vishwanath Bhat, Chris Carlson, Vassil Antonov
  • Patent number: 8058159
    Abstract: A method for fabricating a component is disclosed. The method includes: providing a member having an effective work function of an initial value, disposing a sacrificial layer on a surface of the member, disposing a first agent within the member to obtain a predetermined concentration of the agent at said surface of the member, annealing the member, and removing the sacrificial layer to expose said surface of the member, wherein said surface has a post-process effective work function that is different from the initial value.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: November 15, 2011
    Assignee: General Electric Company
    Inventors: Vance Robinson, Stanton Earl Weaver, Joseph Darryl Michael
  • Patent number: 8053335
    Abstract: A method includes forming a first layer containing silicon oxide on a first substrate, partially removing the first layer to form an exposure portion on the first substrate, depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion, evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate, forming an epitaxial layer of the semiconductor on the first substrate, and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: November 8, 2011
    Inventor: Takao Yonehara
  • Patent number: 8048774
    Abstract: A formation in a first surface of a substrate is machined by an ultraviolet or visible radiation laser, to a predetermined depth that is less than a full depth of the substrate; and material is removed from a second surface of the substrate opposed to the first surface to the predetermined depth from the first surface to communicate with the formation. Material may be removed by, for example, lapping and polishing, chemical etching, plasma etching or laser ablation. The invention has application in, for example, dicing semiconductor wafers to forming metallised vias in wafers.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: November 1, 2011
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Adrian A. Boyle, Oonagh Meignan
  • Patent number: 8030192
    Abstract: A process for manufacturing a MOS device and the MOS device manufactured thereby are disclosed. The process includes in a semiconductor layer forming a gate structure above the semiconductor layer; forming a first doped region within a first surface portion of the semiconductor layer; and irradiating the first doped region with electromagnetic radiation, to carry out annealing thereof. Prior to the irradiating step, a dielectric mirror is formed above a second surface portion of the semiconductor layer. The dielectric mirror, which may be of the Bragg-reflector type, reflects at least in part the electromagnetic radiation, and protects underlying regions from the electromagnetic radiation.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: October 4, 2011
    Assignees: STMicroelectronics S.R.L., Consiglio Nazionale Delle Ricerche
    Inventors: Dario Salinas, Guglielmo Fortunato, Angelo Magri′, Luigi Mariucci, Massimo Cuscuna′, Cateno Marco Camalleri
  • Patent number: 7998835
    Abstract: Methods (and semiconductor substrates produced therefrom) of fabricating (n?1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n?1 SDOI substrates.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: August 16, 2011
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Lee Wee Teo, Chung Foong Tan, Shyue Seng Tan, Elgin Quek
  • Publication number: 20110186228
    Abstract: A showerhead is disclosed in this invention. The showerhead includes a bottom portion, at least one plate, and a top portion. The bottom portion includes a plurality of gas tubes which are integratedly formed on the bottom portion. The gas tubes include at least one first gas tube. The at least one plate includes a first plate. The first plate includes a plurality of first openings, wherein the gas tubes pass through the first openings. The top portion is coupled to the bottom portion for forming at least one inner space.
    Type: Application
    Filed: April 9, 2010
    Publication date: August 4, 2011
    Applicant: HERMES-EPITEK CORPORATION
    Inventors: Chien-Ping Huang, Tsan-Hua Huang
  • Patent number: 7972963
    Abstract: A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 ?m or less. A process for producing the semiconductor wafer, comprises at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant. The shielding extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 ?m long.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: July 5, 2011
    Assignee: Siltronic AG
    Inventors: Thomas Teuschler, Guenter Schwab, Maximilian Stadler
  • Publication number: 20110159666
    Abstract: Systems, methods, and products made by a deposition process are shown and described. A work piece is supported in a main deposition chamber so that the work piece is positioned above each container of deposition material as the container is moved into and out of the deposition chamber. One or more containers are sequentially moved from each of a plurality of auxiliary chambers into and out of the deposition chamber so as to deposit material from each of the containers onto the work piece in a sequential manner.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventor: John P. O'Connor
  • Publication number: 20110146764
    Abstract: This invention relates to compounds and compositions used to prepare semiconductor and optoelectronic materials and devices. This invention provides a range of compounds, compositions, materials and methods directed ultimately toward photovoltaic applications, as well as devices and systems for energy conversion, including solar cells. In particular, this invention relates to molecular precursor compounds, precursor materials and methods for preparing photovoltaic layers.
    Type: Application
    Filed: September 17, 2010
    Publication date: June 23, 2011
    Applicant: PRECURSOR ENERGETICS, INC.
    Inventors: Kyle L. Fujdala, Wayne A. Chomitz, Zhongliang Zhu, Matthew C. Kuchta
  • Patent number: 7943488
    Abstract: A method includes placing a first bonding layer on at least one of a first functional region bonded on a release layer with a light releasable adhesive layer on a first substrate, and a transfer region on a second substrate; bonding the first functional region to the second substrate by the first bonding layer; irradiating the release layer with light with a light blocking member being provided to separate the first substrate from the first functional region at the release layer; placing a second bonding layer on at least one of a second functional region on the first substrate, and a transfer region on the release layer or a transfer region on a third substrate; bonding the second functional region to the second substrate or the third substrate by the second bonding layer; and separating the first substrate from the second functional region at the release layer.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: May 17, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Publication number: 20110111574
    Abstract: A nitride-based semiconductor crystal and a second substrate are bonded together. In this state, impact is applied externally to separate the low-dislocation density region of the nitride-based semiconductor crystal along the hydrogen ion-implanted layer, thereby transferring (peeling off) the surface layer part of the low-dislocation density region onto the second substrate. At this time, the lower layer part of the low-dislocation density region stays on the first substrate without being transferred onto the second substrate. The second substrate onto which the surface layer part of the low-dislocation density region has been transferred is defined as a semiconductor substrate available by the manufacturing method of the present invention, and the first substrate on which the lower layer part of the low-dislocation density region stays is reused as a substrate for epitaxial growth.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 12, 2011
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji AKIYAMA, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Yuuji Tobisaka, Koichi Tanaka
  • Publication number: 20110108815
    Abstract: A method for forming a thin film electrode for an organic thin film transistor of the invention provides a multi-layer mask on a substrate with an electrode area opening in a top layer of the mask that is undercut by openings in other layers of the mask. A thin film of metal is deposited in the electrode area on the substrate. Removing the multi-layer mask leaves a well-formed thin film electrode with naturally tapered edges. A preferred embodiment of the invention is a method for forming a thin film electrode for an organic thin film transistor. The method includes depositing a first layer of photoresist on a substrate. The photoresist of the first layer has a first etching rate. A second layer of photoresist is deposited on the first layer of photoresist. The photoresist of the second layer has a second etching rate that is lower than the first etching rate. The first and second layer of photoresist are patterned by exposure.
    Type: Application
    Filed: April 21, 2009
    Publication date: May 12, 2011
    Applicant: THE REGENTS OF UNIVERSITY OF CALIFORNIA
    Inventors: Andrew C. Kummell, Jeongwin Park
  • Publication number: 20110101298
    Abstract: Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Publication number: 20110097901
    Abstract: Embodiments of dual mode inductively coupled plasma reactors and methods of use of same are provided herein. In some embodiments, a dual mode inductively coupled plasma processing system may include a process chamber having a dielectric lid and a plasma source assembly disposed above the dielectric lid. The plasma source assembly includes a plurality of coils configured to inductively couple RF energy into the process chamber to form and maintain a plasma therein, a phase controller for adjusting the relative phase of the RF current applied to each coil in the plurality of coils, and an RF generator coupled to the phase controller and the plurality of coils.
    Type: Application
    Filed: June 23, 2010
    Publication date: April 28, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: SAMER BANNA, VALENTIN N. TODOROW, KENNETH S. COLLINS, ANDREW NGUYEN, MARTIN JEFF SALINAS, ZHIGANG CHEN, ANKUR AGARWAL, ANNIRUDDHA PAL, TSE-CHIANG WANG, SHAHID RAUF
  • Patent number: 7932163
    Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Dae-Lok Bae, Seong-Kyu Yun, Suk-Hun Choi
  • Publication number: 20110091811
    Abstract: A patternable adhesive film is formed in a double-layered structure of an adhesive layer having patternability and an adhesive layer having both adhesion and developability. Thus, the double-layered patternable adhesive film can effectively have both patternability and adhesion.
    Type: Application
    Filed: April 9, 2010
    Publication date: April 21, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Jin SONG, Chul Ho JEONG, Yong Seok HAN, Yi Yeol LYU
  • Publication number: 20110092075
    Abstract: A semiconductor device manufacturing apparatus includes a chamber in which a wafer is loaded; a first gas supply unit for supplying a process gas into the chamber; a gas exhaust unit for exhausting a gas from the chamber; a wafer support member on which the wafer is placed; a ring on which the wafer support member is placed; a rotation drive control unit connected to the ring to rotate the wafer; a heater disposed in the ring and comprising a heater element for heating the wafer to a predetermined temperature and including an SiC layer on at least a surface, and a heater electrode portion molded integrally with a heater element and including an SiC layer on at least a surface; and a second gas supply unit for supplying an SiC source gas into the ring.
    Type: Application
    Filed: October 13, 2010
    Publication date: April 21, 2011
    Inventors: Kunihiko Suzuki, Shinichi Mitani
  • Patent number: 7923378
    Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: April 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa
  • Publication number: 20110048326
    Abstract: A film formation apparatus for a semiconductor process for forming a thin film on a target object by use of first and second reactive gases includes a vacuum container, an exhaust system, a rotary table configured to place the target object thereon, a rotating mechanism configured to rotate the rotary table, and a temperature adjusting mechanism configured to set the target object to a temperature at which the first reactive gas is condensed. Inside the vacuum container, a first reactive gas supply section configured to adsorb a condensed substance of the first reactive gas onto the target object, a vaporizing section configured to partly vaporize the condensed substance, and a second reactive gas supply section configured to cause the second reactive gas to react with the condensed substance are disposed in this order in a rotational direction of the rotary table.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 3, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hitoshi KATO, Kohichi Orito
  • Publication number: 20110053342
    Abstract: The invention relates to a method for preparing a surface of a semiconductor substrate by oxidizing the surface of the semiconductor substrate to thereby transform the natural oxide into an artificial oxide and then removing the artificial oxide, in particular to obtain an oxide-free substrate surface.
    Type: Application
    Filed: January 23, 2009
    Publication date: March 3, 2011
    Inventor: Radouane Khalid
  • Publication number: 20110045653
    Abstract: [Object] To facilitate bonding of articles at a low temperature without degrading electrical contact between the articles. [Means to Realize Object] An oxide film reducing treatment with hydrogen radicals is carried out for surfaces of lead-out electrodes (5) and bump electrodes (6) on the lead-out electrodes (5) of a semiconductor chip (2) and surfaces of lead-out electrodes (8) of an intermediate substrate (3), and, after that, the bump electrodes (6) of the semiconductor chip (2) and the lead-out electrodes (8) of the intermediate substrate (3) are aligned with each other. After that, a pressure is applied to bond the bump electrodes (6) and the lead-out electrodes (8).
    Type: Application
    Filed: April 30, 2009
    Publication date: February 24, 2011
    Applicants: SHINKO SEIKI COMPANY, LIMITED
    Inventors: Yasuhide Ohno, Keisuke Taniguchi, Tatsuya Takeuchi, Taizo Hagihara
  • Publication number: 20110039417
    Abstract: A dielectric board (20) is arranged on a ceiling surface, which is of a processing container (2) and faces a susceptor (3), a slot antenna (30) having a plurality of slots (33) which pass through microwaves is arranged on an upper surface of the dielectric board (20), and a protruding member (21), which is composed of a member different from the dielectric board (20) and eliminates abnormal discharge, is provided on a lower peripheral section of the dielectric board (20). A field strength at the peripheral section of the dielectric board (20) is controlled by adjusting a space between an outer circumference surface (22) of a cylindrical section of the protruding member (21) and a side wall inner circumference surface (5a) of the processing container (2) or adjusting the thickness of the cylindrical section of the protruding member (21).
    Type: Application
    Filed: February 6, 2009
    Publication date: February 17, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Naoki Matsumoto, Kazuyuki Kato, Masafumi Shikata, Masaru Sasaki
  • Publication number: 20110034034
    Abstract: A method and apparatus for heating a substrate in a chamber are provided. an apparatus for positioning a substrate in a processing chamber. In one embodiment, the apparatus comprises a substrate support assembly having a support surface adapted to receive the substrate and a plurality of centering members for supporting the substrate at a distance parallel to the support surface and for centering the substrate relative to a reference axis substantially perpendicular to the support surface. The plurality of the centering members are movably disposed along a periphery of the support surface, and each of the plurality of centering members comprises a first end portion for either contacting or supporting a peripheral edge of the substrate.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 10, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Dale R. Du Bois, Juan Carlos Rocha-Alvarez, Sanjeev Baluja, Ganesh Balasubramanian, Lipyeow Yap, Jianhua Zhou, Thomas Nowak
  • Publication number: 20110028001
    Abstract: Disclosed is a substrate processing apparatus and method. The substrate processing apparatus includes a process chamber (10) providing an internal space, in which a process is carried out onto a substrate; a support member (30) installed in the process chamber (10) to support the substrate; and a shower head (20) located above the support member (30) to supply a source gas toward the support member (30), wherein the shower head (20) includes a first injection surface (24) located at a position separated from the upper surface of the substrate by a first distance, and provided with outlets of first injection holes (24a) to inject the source gas; and a second injection surface (26) located at a position separated from the upper surface of the substrate by a second distance being different from the first distance, and provided with outlets of second injection holes (26a) to inject the source gas.
    Type: Application
    Filed: March 27, 2009
    Publication date: February 3, 2011
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Sung-Tae Je, Il-Kwang Yang, Chan-Yong Park
  • Publication number: 20110021033
    Abstract: A batch CVD method repeats a cycle including adsorption and reaction steps along with a step of removing residual gas. The adsorption step is preformed while supplying the source gas into the process container by first setting the source gas valve open for a first period and then setting the source gas valve closed, without supplying the reactive gas into the process container by keeping the reactive gas valve closed, and without exhausting gas from inside the process container by keeping the exhaust valve closed. The reaction step is performed without supplying the source gas into the process container by keeping the source gas valve closed, while supplying the reactive gas into the process container by setting the reactive gas valve open, and exhausting gas from inside the process container by setting the exhaust valve to gradually decrease its valve opening degree from a predetermined open state.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 27, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshiyuki Ikeuchi, Masayuki Hasegawa, Toshihiko Takahashi, Keisuke Suzuki
  • Publication number: 20110021034
    Abstract: Disclosed is a substrate processing apparatus and method. The substrate processing apparatus includes a chamber (10) providing an internal space, in which a process is carried out onto a substrate; a gas supply unit (40) supplying a source gas to the internal space; a coil (16) generating an electric field in the internal space to generate plasma from the source gas; and an adjustment ring (50) disposed on a flow path of the plasma toward a support member to adjust the flow of the plasma. The chamber (10) includes a process chamber (12), in which the support member is provided and the process is carried out by the plasma; and a generation chamber (14), in which the plasma is generated by the coil (16), provided on the upper surface of the process chamber (12), and the adjustment ring (50) is installed at the lower end of the generation chamber (14).
    Type: Application
    Filed: March 23, 2009
    Publication date: January 27, 2011
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventor: Il-Kwang Yang
  • Publication number: 20100326355
    Abstract: Holes in semiconductor processing reactor parts are sized to facilitate deposition of protective coatings, such as by chemical vapor deposition at atmospheric pressure. In some embodiments, the holes each have a flow constriction that narrows the holes in one part and that also divides the holes into one or more other portions. In some embodiments, the aspect ratios of the one or more other portions are about 15:1 or less, or about 7:1 or less, and have a cylindrical or conical cross-sectional shape. The holes are coated with a protective coating, such as a silicon carbide coating, by chemical vapor deposition, including chemical vapor deposition at atmospheric pressure.
    Type: Application
    Filed: September 14, 2010
    Publication date: December 30, 2010
    Applicant: ASM International N.V.
    Inventor: Vladimir Kuznetsov
  • Publication number: 20100327085
    Abstract: A plasma processing system for plasma processing of substrates such as semiconductor wafers. The system includes a plasma processing chamber, a substrate support for supporting a substrate within the processing chamber, a dielectric member having an interior surface facing the substrate support, the dielectric member forming a wall of the processing chamber, a gas injector fixed to, part of or removably mounted in an opening in the dielectric window, the gas injector including a plurality of gas outlets supplying process gas into the chamber, and an RF energy source such as a planar or non-planar spiral coil which inductively couples RF energy through the dielectric member and into the chamber to energize the process gas into a plasma state. The arrangement permits modification of gas delivery arrangements to meet the needs of a particular processing regime. In addition, compared to consumable showerhead arrangements, the use of a removably mounted gas injector can be replaced more easily and economically.
    Type: Application
    Filed: August 20, 2010
    Publication date: December 30, 2010
    Applicant: Lam Research Corporation,
    Inventors: Tuqiang NI, Alex DEMOS
  • Publication number: 20100330776
    Abstract: A bonding apparatus and method holds first and second bodies peripherally, one above the other, on respective shelves. A lower heat-transfer body is configured to lift the first body from below and press the first and second bodies against an upper heat-transfer body to enable bonding between the first and second bodies.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Steven M. Zuniga, Robert D. Tolles, Derek G. Aqui, Andrew J. Nagengast, Anthony J. Senn, Keenan Leon Guerrero