Insulative Mounting Semiconductor Device On Support (epo) Patents (Class 257/E21.505)
  • Patent number: 10438926
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 8, 2019
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Patent number: 10327336
    Abstract: In an example, a dry film solder mask (DFSM) composite laminate material is disclosed. The DFSM composite laminate material includes a printed circuit board (PCB) laminate material, a cyclic compound chemically bonded to the PCB laminate material, and a DFSM material. The DFSM material is reversibly bonded to the PCB laminate material via the cyclic compound.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sarah K. Czaplewski, Joseph Kuczynski, Jason T. Wertz, Jing Zhang
  • Patent number: 10269767
    Abstract: A package may include a first chip having a first surface and a second surface opposite the first surface; a first redistribution line (RDL) coupled to the first surface of the first chip; a second chip having a first surface and a second surface opposite the first surface, the first surface of the second chip facing the first chip; a second RDL disposed between the first chip and the second chip and coupled to the first surface of the second chip; a conductive via laterally adjacent to the second chip, the conductive via coupled to the second RDL; and a molding compound disposed between the second chip and the conductive via.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 10243098
    Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate. In some cases, embodiments include a substrate including a plurality of wells each having a sidewall where a through hole via extends from a bottom of at least one of the plurality of wells; and a post enhanced diode including a post extending from a top surface of a diode structure.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: March 26, 2019
    Assignee: eLux Inc.
    Inventors: David Robert Heine, Sean Mathew Garner, Avinash Tukaram Shinde
  • Patent number: 10203256
    Abstract: A transducer baseplate includes a base, a protrusion extending from the base along a longitudinal axis, a pair of opposed transducer receptacles defined within the protrusion, and respective pressure plena. The pressure plena are separated by a plenum wall, each plenum being in fluid connection with an area external to the protrusion through a respective pressure line. The pressure lines provide a direct fluid path to their respective receptacles.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: February 12, 2019
    Assignee: Rosemount Aerospace Inc.
    Inventors: Saeed Fahimi, Odd H. Eriksen, Charles Little
  • Patent number: 10192797
    Abstract: A purpose of the present invention is to provide a semiconductor device that can restrain occurrence of partial discharge in evaluation of electric characteristics and can carry out failure analysis from the upper side of a measurement object. A semiconductor device according to the present invention includes: at least one electrode; a protective layer having at least one opening part provided such that a portion of the electrode is exposed at the opening part, and being formed to cover the other portion of the electrode excluding the portion of the electrode exposed at the opening part, the protective layer being insulative; and a conductive layer formed so as to cover the protective layer and the opening part and be directly connected to the electrode at the opening part.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 29, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hajime Akiyama, Akira Okada, Kinya Yamashita
  • Patent number: 10147702
    Abstract: The present application provides methods, systems and devices for simultaneously bonding multiple semiconductor chips of different height profiles on a flexible substrate.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 4, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Brent S. Krusor, Ping Mei
  • Patent number: 10092396
    Abstract: An electronic device can comprise a first electronic module; a second electronic module; and a hermetic electric interconnect to hermetically couple them. The hermetic electric interconnect can comprise a bottom metal layer; a bottom insulating layer, deposited on the bottom metal layer to insulate the bottom metal layer; an interconnect metal layer, deposited on the bottom insulating layer, and deposited to form a bottom sealing ring; and patterned to form electrical connections between contact pads, and to form a middle sealing ring; a patterned top insulating layer, deposited on the interconnect metal layer to insulate the interconnect metal layer; and patterned to form feedthrough holes; and a top metal layer, deposited on the top insulating layer to start forming contacts by filling the feedthrough holes; and patterned to complete forming contacts through the feedthrough holes, to form a separate barrier layer, and to complete forming the top sealing ring.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 9, 2018
    Assignee: Novartis AG
    Inventors: Michael F. Mattes, Mark A. Zielke
  • Patent number: 10032725
    Abstract: A semiconductor structure includes a plurality of devices, each of the plurality of devices includes a first surface disposed with an active component; and a molding disposed between the plurality of devices and including a first surface, wherein one of the plurality of devices has substantially different height from another one of the plurality of devices, and the first surface of the molding includes a recessed portion recessed from one of the first surfaces of the plurality of devices.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Jui-Pin Hung
  • Patent number: 10014277
    Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Vijay Nair
  • Patent number: 10008463
    Abstract: A semiconductor package includes a first semiconductor die surrounded by a molding compound. The semiconductor package further includes a first conductive pad on the first semiconductor die, wherein the first conductive pad is at a top metal level of the first semiconductor die. The semiconductor package further includes redistribution lines (RDLs) formed over the first conductive pad, wherein at least one RDL of the RDLs extends beyond the boundaries of the semiconductor die, and a portion of the at least one RDL contacts the first conductive pad, wherein a surface of the first conductive pad contacting the portion of the at least one RDL is at a different level than a surface of the molding compound under the at least one RDL extended beyond the boundaries of the first semiconductor die.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung
  • Patent number: 9883592
    Abstract: A wiring board includes a substrate which has multiple opening portions and one or more boundary portions separating the opening portions, multiple electronic devices positioned in the opening portions of the substrate, respectively, a conductive pattern formed on a surface of the boundary portion, and an insulation layer formed on the substrate and the conductive pattern on the boundary portion of the substrate such that the insulation layer covers the electronic devices in the opening portions of the substrate. The boundary portion has a width which is in a range of approximately 0.05 to approximately 2.0 mm.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 30, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Toshiki Furutani, Yukinobu Mikado, Toyotaka Shimabe, Shinobu Kato
  • Patent number: 9871015
    Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: January 16, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, David Razu
  • Patent number: 9865481
    Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9861313
    Abstract: A method includes forming one or more trenches in a first substrate, forming one or more vias in a second substrate, aligning at least a first trench in the first substrate with at least a first via in the second substrate, and sealing the first substrate to the second substrate by filling the first via and the first trench with solder material using injection molded soldering.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Shriya Kumar, Jae-Woong Nah
  • Patent number: 9831157
    Abstract: In a method for producing an electronic part mounting substrate wherein an electronic part 14 is mounted on one major surface (a surface to which the electronic part 14 is to be bonded) of the metal plate 10 of copper, or aluminum or the aluminum alloy (when a plating film 20 of copper is formed on the surface), the one major surface of the metal plate 10 (or the surface of the plating film 20 of copper) is surface-machined to be coarsened so as to have a surface roughness of not less than 0.4 ?m, and then, a silver paste is applied on the surface-machined major surface (or the surface-machined surface of the plating film 20 of copper) to arrange the electronic part 14 thereon to sinter silver in the silver paste to form a silver bonding layer 12 to bond the electronic part 14 to the one major surface of the metal plate 10 (or the surface of the plating film 20 of copper) with the silver bonding layer 12.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 28, 2017
    Assignee: Dowa Metaltech Co., Ltd.
    Inventors: Naoya Sunachi, Hideyo Osanai, Satoru Kurita
  • Patent number: 9780070
    Abstract: A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: October 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Yoshiaki Oikawa, Chiho Kawanabe
  • Patent number: 9773751
    Abstract: A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Shriya Kumar, Jae-Woong Nah
  • Patent number: 9773740
    Abstract: A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 26, 2017
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Karine Saxod, Marika Sorrieul
  • Patent number: 9768140
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: September 19, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yan-Heng Chen, Mu-Hsuan Chan, Chieh-Yuan Chi
  • Patent number: 9752065
    Abstract: A sealant composition includes a curable sealing resin, and a plurality of microcapsules dispersed in the sealing resin. Each of the plurality of microcapsules includes a self-curable healing agent and a capsule coating film encapsulating the healing agent.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: September 5, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Byung-Wook Ahn
  • Patent number: 9716027
    Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 25, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takamitsu Yoshihara, Takahiro Kainuma, Hiroi Oka
  • Patent number: 9698160
    Abstract: A method for transferring micro devices is provided. The method includes the following operations: providing a carrier substrate and forming micro devices on the carrier substrate; forming a fixing layer on the carrier substrate, in which the fixing layer is at least in contact with bottom parts of the micro devices; patterning the fixing layer to selectively expose a portion of the micro devices; providing a transfer device correspondingly located on the carrier substrate, and picking up the exposed micro devices by the transfer device; and providing a receiving substrate and transferring the exposed micro devices to the receiving substrate.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: July 4, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Tsung-Tien Wu, Kang-Hung Liu, Tsung-Yi Lin
  • Patent number: 9691726
    Abstract: A method includes forming a first composite wafer including molding a plurality of device dies and a plurality of through-vias in a first molding material, and forming redistribution lines on opposite sides of the first molding material. The redistribution lines are inter-coupled through the plurality of through-vias. The method further includes forming a second composite wafer including stacking a plurality of dies to form a plurality of die stacks, and molding the plurality of die stacks in a second molding material. The second molding material fills gaps between the plurality of die stacks. The first composite wafer is bonded to the second composite wafer to form a third composite wafer.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Hsien-Wei Chen, Cheng-Lin Huang, Meng-Tse Chen, Chung-Shi Liu
  • Patent number: 9676968
    Abstract: A heat resistant adhesive sheet is provided that does not easily develop deformation of an adhesive sheet due to heating. Such an adhesive sheet made by laminating an adhesive layer to a substrate is provided, characterized in that the substrate is heat shrinkable and the adhesive layer contains a (meth)acrylate copolymer, a photopolymerizable compound, a polyfunctional isocyanate curing agent, and a photopolymerization initiator and does not substantially contain a tackifying resin. This adhesive sheet is not deformed even when heated. Since the adhesive does not substantially contain a tackifying resin, softening of the adhesive layer does not occur even when the sheet is heated.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: June 13, 2017
    Assignee: DENKA COMPANY LIMITED
    Inventors: Gosuke Nakajima, Masanobu Kutsumi
  • Patent number: 9679867
    Abstract: A semiconductor device includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: June 13, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Ashidate, Kazumasa Tanida
  • Patent number: 9666376
    Abstract: A solid electrolytic capacitor that includes a valve action metal base, an insulating layer, a solid electrolyte layer, a carbon layer and an electrode layer sequentially formed in one of two parts of the valve action metal base. The electrode layer is formed from a conductive paste that includes at least a conductive filler, a thermosetting resin containing a phenoxy resin, and a curing agent.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: May 30, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koutarou Mishima, Akihiro Nomura
  • Patent number: 9536805
    Abstract: A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: January 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Siamak Fazelpour, Jiantao Zheng, Mario Francisco Velez, Sun Yun, Rajneesh Kumar, Houssam Wafic Jomaa
  • Patent number: 9458283
    Abstract: Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 4, 2016
    Assignee: INTEL CORPORATION
    Inventors: Dingying Xu, Nisha Ananthakrishnan, Hong Dong, Rahul N. Manepalli, Nachiket R. Raravikar, Gregory S. Constable
  • Patent number: 9419156
    Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Jui Hsieh Lai, Tien-Yu Huang, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 9389362
    Abstract: Embodiments include a method for interconnecting components of an optical circuit. The method includes arranging the components on a support layer and embedding them within a material, such that portions of the material that is between the components contact the support layer. The obtained components are positioned with a certain inaccuracy with respect to ideal nominal positions thereof. Next, the support layer is removed to reveal one side of the components, on which side the components are level with said portions of said material. Positions of the components are identified and a set of optical polymer waveguides are adaptively fabricated, on the one side, so as for each of the fabricated polymer waveguides to optically connect subsets of two or more of the components, according to the identified positions of the components. The present invention is further directed to related optical circuits or electro-optical circuits of interconnected components.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: July 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Brunschwiler, Antonio La Porta, Bert J. Offrein, Jonas R. Weiss
  • Patent number: 9373569
    Abstract: A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad and exposed back sides of the terminals. Partial sawing in saw lanes begins from the back side through the terminals terminating within the plastic encapsulation to provide exposed side walls of the terminals and of the plastic encapsulation. The exposed thermal pad and exposed back side of the terminals are all shorted together to form exposed electrically interconnected metal surfaces (interconnected surfaces). The interconnected surfaces are electroplated with a solder wetable metal or metal alloy plating layer. The interconnected surfaces are decoupled. A second sawing in the saw lanes finishes sawing through the plastic encapsulation to provide singulation, forming a plurality of packaged semiconductor devices.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: June 21, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATION
    Inventors: Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran
  • Patent number: 9362247
    Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: June 7, 2016
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Robert N. Chylak, Dominick A. DeAngelis
  • Patent number: 9360623
    Abstract: A method of fabricating a heterogeneous semiconductor wafer includes depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate. The first wafer is then bonded to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer. The semiconductor substrate associated with the first wafer is removed to expose the III-V type semiconductor epitaxial layer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 7, 2016
    Assignee: The Regents of the University of California
    Inventors: John E. Bowers, Jock Bovington
  • Patent number: 9300222
    Abstract: A power converter sub-assembly/module includes a power switching assemblage defining a cavity within which can be mounted a driver IC. The power switching assemblage includes a load inductor component stack attached to a power transistor block and an interconnect spacer block, defining a cavity between the two blocks. The power transistor block includes a high and low side FETs attached side-by-side to a switch-node metal carrier that includes an attach-surface opposite the FETs. The power switching assemblage is mountable to an interconnect surface that includes connection pads VIN, VOUT, GND, HG (high-side gate) and LG low-side gate). For a module configuration, the power switching assemblage is combined with a driver IC that provides high (HG) and low (LG) gate driveā€”the power switching assemblage and the driver IC are mounted to a module interconnect substrate, with the driver IC mounted within the cavity of the power switching assemblage.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: James Ignatius Moss
  • Patent number: 9029928
    Abstract: A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Laurent Marechal, Yvon Imbs, Romain Coffy
  • Patent number: 8994162
    Abstract: A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventor: Marcos Karnezos
  • Patent number: 8980689
    Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Soo Kwak, Cha-Jea Jo, Tae-Je Cho, Sang-Uk Han
  • Patent number: 8975734
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8970049
    Abstract: A module having multiple die includes a first die on a first substrate and an inverted second package stacked over the first die, with, where necessary, provision is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 3, 2015
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 8963323
    Abstract: An apparatus 100 comprising a first substrate 130 having a first surface 125, a second substrate 132 having a second surface 127 facing the first surface and an array 170 of metallic raised features 170 being located on the first surface, each raised feature being in contact with the first surface to the second surface, a portion of the raised features being deformed via a compressive force 305.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: February 24, 2015
    Assignee: Alcatel Lucent
    Inventors: Roger Scott Kempers, Shankar Krishnan, Alan Michael Lyons, Todd Richard Salamon
  • Patent number: 8946885
    Abstract: A semiconductor arrangement includes a ceramic mount and at least one semiconductor component fixed-to the ceramic mount. The ceramic mount includes a first section, and the first section is electrically conductive.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: February 3, 2015
    Assignee: Robert Bosch GmbH
    Inventor: Andreas Krauss
  • Patent number: 8940586
    Abstract: The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chris Kuo, Lee-Chuan Tseng
  • Patent number: 8936966
    Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 8927344
    Abstract: Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: January 6, 2015
    Assignee: ATI Technologies ULC
    Inventors: Roden Topacio, Adam Zbrzezny
  • Patent number: 8921824
    Abstract: A three-dimensional graphene structure, and methods of manufacturing and transferring the same including forming at least one layer of graphene having a periodically repeated three-dimensional shape. The three-dimensional graphene structure is formed by forming a pattern having a three-dimensional shape on a surface of a substrate, and forming the three-dimensional graphene structure having the three-dimensional shape of the pattern by growing graphene on the substrate on which the pattern is formed. The three-dimensional graphene structure is transferred by injecting a gas between the three-dimensional graphene structure and the substrate, separating the three-dimensional graphene structure from the substrate by bonding the three-dimensional graphene structure to an adhesive support, combining the three-dimensional graphene structure with an insulating substrate, and removing the adhesive support.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-jin Shin, Jae-young Choi, Ji-hoon Park, Joung-real Ahn
  • Patent number: 8912646
    Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 16, 2014
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Michael A. Stuber, Stuart B. Molin, Mark Drucker, Peter Fowler
  • Patent number: 8906740
    Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through via; attaching a conductive support over the substrate with the conductive support adjacent to the integrated circuit; providing a pre-formed interposer, having an interposer through via and a pre-attached interconnect, with the pre-attached interconnect attached to the interposer through via; mounting the pre-formed interposer over the integrated circuit and the conductive support with the pre-attached interconnect over the device through via; and forming an encapsulation over the substrate covering the integrated circuit, the conductive support, and partially covering the pre-formed interposer.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: December 9, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Chan Hoon Ko, Soo-San Park, YoungChul Kim
  • Patent number: 8872333
    Abstract: A millimeter wave integrated waveguide interface package device may comprise: (1) a package comprising a printed wiring board (PWB) and a monolithic microwave integrate circuit (MMIC), wherein the MMIC is in communication with the PWB; and (2) a waveguide interface integrated with the package. The package may be adapted to operate at high frequency and high power, where high frequency includes frequencies greater than about 5 GHz, and high power includes power greater than about 0.5 W.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: October 28, 2014
    Assignee: ViaSat, Inc.
    Inventors: Noel A Lopez, Michael R Lyons, Dave Laidig, Kenneth V Buer
  • Patent number: RE47651
    Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 15, 2019
    Assignee: General Electric Company
    Inventors: James Sabatini, Christopher James Kapusta, Glenn Forman