Abstract: An LED light source (10) comprises a ceramic substrate (20) with first and second opposed surfaces (30, 40). Pockets (50) are formed in the first surface (30) and each of the pockets includes a bottom (60) and a sidewall or sidewalls (70). A final electrical contact (105) comprised of a first electrically conductive material (57) with a coating of a second electrically conductive material (100) thereover is positioned in each of the pockets (50). An LED (110) is positioned in each of the pockets (50) and affixed to the electrical contact (105) and electrical connections (120), preferably in form of wire bonds, join the LEDs, the electrical connections (120) extending from a first LED (110) to an adjacent electrical contact (105). The ceramic substrate (20) is formed by injection molding a ceramic material and binder to form a green substrate (12) and subsequently sintering the green substrate to form the substrate (20).

Abstract: Methods are disclosed related to attaching a die to a leadframe. One such method includes initially bonding a carrier pad which is pre-coated with a thermosetting first adhesive to the leadframe. The first adhesive can be raised to its thermosetting cure temperature by heating the leadframe to a temperature just above the thermosetting cure temperature of the first adhesive. A thermosetting second adhesive which is liquid at room temperature can be applied to a second major surface of the carrier pad, and the die can be placed on the second adhesive and aligned with the leadframe. The second adhesive can be raised to its thermosetting cure temperature to bond the die to the carrier pad, and in turn form a bonded assembly.

Abstract: The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased.

Abstract: A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Abstract: A device comprising a first component (5) having a first surface (6), a second component (8) having a second surface (9) and a connection layer (7) between the first surface (6) of the first component (5) and the second surface (9) of the second component (8), wherein the connection layer (7) comprises an electrically insulating adhesive and there is an electrically conductive contact between the first surface (6) of the first component (5) and the second surface (9) of the second component (8).

Abstract: A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.

Abstract: A method for fabricating an encapsulant cavity integrated circuit package system includes: providing an interposer; forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and the interposer; and attaching a component on the interposer in the encapsulant cavity.

Abstract: According to one embodiment, a semiconductor memory card that includes a printed substrate in which an electronic component is mounted on one surface, and an external terminal is installed on the other surface, and that is molded in a card form. The printed substrate is a laminated body in which a metallic interconnection for connecting the electronic component to the terminal and a solder resist are sequentially laminated on both surfaces of a core material. The semiconductor memory card includes an ink layer on the solder resist of the other surface, and a mark is engraved by a laser on the ink layer.

Abstract: When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided.

Abstract: In one embodiment, a method for assembling a ball grid array (BGA) package is provided. The method includes providing a stiffener that has opposing first and second surfaces, wherein the first surface is capable of mounting an integrated circuit (IC) die in a central area and forming a pattern in at least a portion of the first surface to enhance the adhesiveness of an encapsulant material to the first surface.

Abstract: A semiconductor chip package includes a substrate, a first layer disposed on the substrate and a second layer substantially similar to and disposed on the first layer. The first layer has a first input/output (I/O) circuit, a first through-via connected to the first input/output (I/O) circuit and a second through-via that is not connected to the first I/O circuit. The second layer has a second I/O circuit, a third through-via connected to the second I/O circuit and a fourth through-via that is not connected to the second I/O circuit. The first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. The package maybe fabricated by stacking the layers, and changing the orientation of the second layer relative to the first to ensure that the first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via.

Abstract: The invention relates to a method of manufacturing a semiconductor device (1), the method comprising: i) providing a substrate (10); ii) providing a photoresist layer (15) on the substrate (10), the photoresist layer (15) comprising an opening (16) having pre-shaped sidewalls (18); iii) filling the opening (16) with an electrically conductive material (20) for defining a contact pad (22) having further sidewalls (23, 26) corresponding with the pre-shaped sidewalls (18).

Abstract: A semiconductor chip includes: a device layer having a first surface and a second surface facing away from the first surface, and possessing conductive patterns, which are formed in the first surface such that at least portions of the conductive patterns are exposed on the first surface, and bonding pads, which are formed on the second surface, are electrically connected. An insulation layer pattern, formed on the first surface of the device layer, has via holes which expose the conductive patterns, and through electrodes are formed in the via holes to be electrically connected with the exposed conductive patterns.

Abstract: A semiconductor device has a substrate having a first plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice is disposed on the substrate. Each die of the plurality of dice has a first plurality of die bonding pads arranged along at least one first edge thereof. A plurality of bonding pillars extends substantially vertically from the substrate bonding pads. Each bonding pillar electrically connects one of the first plurality of substrate bonding pads to a corresponding one of the first plurality of die bonding pads. A method of assembling a semiconductor device is also described.

Abstract: Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.

Abstract: The present disclosure relates to fabricating substrates for use in microelectronic device packages. In at least one embodiment, two substrate cores may be attached together during build-up layer formation on each substrate core to increase substrate fabrication throughput. The embodiments of the present disclosure may allow the processing of relatively thin substrates.

Abstract: An integrated circuit package system includes providing die; forming leads adjacent the die; forming a die paddle adjacent the leads with the die thereover; and forming a cavity for isolating one of the die and a die attach segment of the die paddle.

Abstract: A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives, first and second conductive layers and a dielectric base, wherein the first post extends from the dielectric base in a first vertical direction into a first opening in the first adhesive and is aligned with a first aperture in the first conductive layer, the second post extends from the dielectric base in a second vertical direction into a second opening in the second adhesive and is aligned with a second aperture in the second conductive layer and the dielectric base is sandwiched between and extends laterally from the posts, then flowing the first adhesive in the first vertical direction and the second adhesive in the second vertical direction, solidifying the adhesives, then providing a conductive trace that includes a pad, a terminal and selected portions of the conductive layers, wherein the pad extends beyond the dielectric base in the first vertical direction and the terminal extends

Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; a step of forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; a step of depositing a plating catalyst on a surface of the wiring gutter; a step of removing the resin coating; and a step of forming an electroless plating coating only at a site where the plating catalyst remains.

Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.

Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.

Abstract: An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises: a polymer component (A) having a weight average molecular weight of 100,000 or more including functional groups; an epoxy resin (B); a phenolic epoxy resin curing agent (C); a photoreactive monomer (D), wherein the Tg of the cured material obtained by ultraviolet light irradiation is 250° C. or more; and a photoinitiator (E) which generates a base and a radical by irradiation with ultraviolet light of wavelength 200-450 nm.

Abstract: A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension.

Abstract: A MEMS microphone package having improved acoustic properties, and to a packaging method, which involve adding a vent path in the packaging process to improve equilibrium between internal and external air pressure. The MEMS microphone package includes a MEMS microphone chip, in which a back plate and a diaphragm structure are formed in a body by using MEMS process techniques; a substrate for mounting the MEMS microphone chip thereon; a vent path which is formed between the MEMS microphone chip and the substrate by applying an adhesive only to a portion of the substrate and adhering the MEMS microphone chip to the substrate; and a case which is adhered to the substrate and forms a space for accommodating the MEMS microphone chip, wherein acoustic properties of the MEMS microphone package are improved as air pressure inside the MEMS microphone chip and air pressure outside the MEMS microphone chip form air equilibrium via the vent path.

Abstract: An IC package includes: a multi-layered PCB having a plurality of insulating layers and a plurality of conductive pattern layers stacked in sequence and a plurality of via-holes formed through the plurality of the insulating layers for an electrical connection between the layers; and an IC chip disposed in a core insulating layer of the plurality of the insulating layers to be embedded in the multi-layered PCB and including a plurality of input/output pads on their surface. The input/output pads disposed at an outermost area of the IC chip are coupled to outer terminals by connection members without passing through said via-hole, the remaining input/output pads except for the input/output pads disposed at the outermost area of the IC chip are coupled to the outer terminals through the via-hole.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: An integrated circuit package system includes: providing a connection array; attaching a base integrated circuit adjacent the connection array; attaching a package integrated circuit over the base integrated circuit; attaching a package die connector to the package integrated circuit and the connection array; and applying a wire-in-film insulator over the package integrated circuit, the package die connector, the base integrated circuit, and the connection array, wherein the connection array is partially exposed.

Abstract: A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. In one embodiment, in which semiconductor devices are to be stacked over and secured to the substrate in a flip-chip type arrangement, the contact areas correspond to bond pads of an upper, second semiconductor device, while other contact areas located within the first region correspond to bond pads of a lower, first semiconductor device. In another embodiment, the contact areas correspond to bond pads of the first semiconductor device, which are electrically connected thereto by way of laterally extending discrete conductive elements, while other contact areas that are located external to the second region correspond to bond pads of the upper, second semiconductor device.

Abstract: An object is to provide a semiconductor device which is not easily broken even if stressed externally and a method for manufacturing such a semiconductor device. A semiconductor device includes an element layer including a transistor in which a channel is formed in a semiconductor layer and insulating layers which are formed as an upper layer and a lower layer of the transistor respectively, and a plurality of projecting members provided at intervals of from 2 to 200 ?m on a surface of the element layer. The longitudinal elastic modulus of the material for forming the plurality of projecting members is lower than that of the materials of the insulating layers.

Abstract: A wiring substrate is provided, including an insulating resin layer which is provided on both surfaces of a sheet-like fibrous body and with which the sheet-like fibrous body is impregnated, and a through wiring provided in a region surrounded by the insulating resin layer. The through wiring is formed using a conductive material, the conductive material is exposed on both surfaces of the insulating resin layer, the sheet-like fibrous body is positioned in the conductive material, and the sheet-like fibrous body is impregnated with the conductive material. A manufacturing method of the wiring substrate is also provided.

Abstract: A semiconductor die package includes a substrate, a semiconductor die mounted on the substrates a molding covering the semiconductor die and which is formed on the substrate and a conductive layer laminated on the molding.

Abstract: A semiconductor memory module having a reverse mounted chip resistor, and a method of fabricating the same are provided. By reverse mounting the chip resistor on the semiconductor memory module, the resistive material is protected, thereby preventing open circuits caused by damage to the resistive material. Also, a chip-resistor connection pad of a module substrate is formed to extend higher from the module substrate than other connection pads connected to other elements. Thus, the resistive material of the chip resistor does not contact the module substrate, thereby preventing poor alignment and defective connections.

Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.

Abstract: A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads.

Abstract: Decoupling capacitors are frequently used in computer systems in order to control noise. In general, decoupling capacitors are placed as close as possible to the devices they protect in order to minimize the amount of line inductance and series resistance between the devices and the capacitors. An integrated circuit package includes a substrate (110, 210) having a first surface (111, 211) and an opposing second surface (112, 212), and a die platform (130, 230) adjacent to the first surface of the substrate. The substrate has a recess (120, 220) therein. The integrated circuit package further includes a capacitor (140, 240) in the recess of the substrate. The presence of a recess in the substrate provides an opportunity to reduce the separation distance between a die supported by the die platform and the decoupling capacitors. A further advantage of embodiments of the invention lies in its ability to maintain socket compatibility.

Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.

Abstract: A lead frame having a die thereon connects a high current conductive area on the die to a lead frame contact using a copper clip that includes a structure portion that is received with a recess-like “tub” formed in the lead frame contact. In the preferred embodiment, a lead frame structure fabricated by etching includes at least one contact that is a half-etch recess or “tub” that receives one end of the clip structure and is retained in the tub by solder paste or an adhesive. The end of the clip that is received in the tub is held in place during subsequent handling until the clip and leadframe undergo solder reflow to effect an electrical connection sufficient to handle the current load and a also effect a reliable mechanical connection.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.

Abstract: A method of manufacturing a semiconductor device includes: supplying a supercritical fluid mixed with an under-fill material to a stacked unit, which has a plurality of stacked semiconductor chips; and filling the under-fill material in the space between the plurality of the semiconductor chips, by heating the stacked unit placed in the inside of the high-pressure vessel and curing the under-fill material flowing in the space between the plurality of the semiconductor chips by a polymerization reaction, while the supercritical fluid is being supplied.

Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts and a die attach area. Dice are mounted onto each device area and electrically connected to the array of contacts. The entire surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including die attach pads, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: A semiconductor apparatus includes a semiconductor device, a cooler of a forced cooling type, and a heat mass. Heat generated in the semiconductor device is conducted to the cooler. The heat mass comes into junction with the semiconductor device with solder so as to be thermally combined with the semiconductor device. The heat mass functions also as an electrode.

Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).

Abstract: Provided is a semiconductor sensor device which is manufactured by an MEMS technology wherein machining technology and/or material technology is combined with semiconductor technology for detecting and measuring various physical quantities. In the semiconductor sensor device, cracks which generate in a cap chip and a molding resin are eliminated and air-tightness between a semiconductor sensor chip and the cap chip is ensured. The cracks due to vibration applied when being cut can be eliminated by having the circumference side surface of the cap chip as a wet-etched surface. Furthermore, insulation is ensured by coating the cap chip side surface with an insulating protection film.

Abstract: A method for fabricating an encapsulant cavity integrated circuit package system includes: forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

Abstract: A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible through the opening and coupling a first surface of a second substrate to the IC die via a bump interconnect. The second surface of the second substrate has an array of contact pads capable of coupling to a board.

Abstract: The invention provides a semiconductor device comprising a semiconductor element and an adherend, thermocompression bonded via a patterned photosensitive film adhesive, wherein the water content of the patterned photosensitive film adhesive just before thermocompression bonding is no greater than 1.0 wt %, with the aim of providing a semiconductor device exhibiting excellent heat resistance.

Abstract: A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor chip with the leads, and a molded body in which the semiconductor chip is resin molded. By further stepwise shortening the chip-side tip end portions of the leads as the first edge or side of the principal surface of the semiconductor chip goes away from the middle portion toward the both end portions thereof, and shortening the tip end portions of those of first leads corresponding to the middle portion of the first edge or side of the principal surface which are adjacent to second leads located closer to the both end portions of the first edge or side, the distances between second wires connected to the second leads and the tip end portions of the first leads adjacent to the second leads can be increased.