Formation Of Contacts To Semiconductor By Use Of Metal Layers Separated By Insulating Layers, E.g., Self-aligned Contacts To Source/drain Or Emitter/base (epo) Patents (Class 257/E21.507)
  • Patent number: 11367663
    Abstract: Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11362098
    Abstract: A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: June 14, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Che-Fu Chuang, Jian-Ting Chen, Yu-Kai Liao, Hsiu-Han Liao
  • Patent number: 11361994
    Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ping Chen, Shau-Lin Shue, Min Cao
  • Patent number: 11362032
    Abstract: A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: June 14, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byounggon Kang, Changbeom Kim, Dalhee Lee, Eun-Hee Choi
  • Patent number: 11355607
    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Larsen, David A. Daycock, Kunal Shrotri
  • Patent number: 11328949
    Abstract: A semiconductor device includes a substrate, a first fin, and a second fin. The first and second fins are spaced apart from each other in a first direction on the substrate and extend in a second direction intersecting the first direction. The semiconductor device further includes a first shallow trench formed between the first and second fins, and a field insulating film which fills at least a part of the first shallow trench. The field insulating film includes a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion and adjacent to a side wall of the first shallow trench. The first portion includes a central portion of an upper surface of the field insulating film in the first direction. The upper surface of the field insulating film is in a shape of a brace recessed toward the substrate.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chae Ho Na, Sung Soo Kim, Gyu Hwan Ahn, Dong Hyun Roh
  • Patent number: 11257716
    Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Belyansky, Marc Bergendahl, Victor W. C. Chan, Jeffrey C. Shearer
  • Patent number: 11222820
    Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Belyansky, Marc Bergendahl, Victor W. C. Chan, Jeffrey C. Shearer
  • Patent number: 11139385
    Abstract: A method of providing contact surfaces that includes forming a first mask having an opening to a perimeter of a gate electrode, the first mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces; and recessing exposed portions of metal semiconductor alloy and the gate electrode with an etch. In a following step, the method continues with filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Veeraraghavan S. Basker, Huiming Bu
  • Patent number: 11069610
    Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Stephen W. Russell, Fabio Pellizzer, Lorenzo Fratin
  • Patent number: 11018141
    Abstract: A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 25, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 11004795
    Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10998359
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a photodetector region arranged within a semiconductor substrate. One or more dielectric materials are disposed within a trench defined by one or more interior surfaces of the semiconductor substrate. A doped epitaxial material is arranged within the trench and is laterally between the one or more dielectric materials and the photodetector region. A dielectric protection layer is arranged over the one or more dielectric materials within the trench. The dielectric protection layer laterally contacts a sidewall of the doped epitaxial material.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yueh-Chuan Lee, Chia-Chan Chen
  • Patent number: 10998228
    Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chan Yen, Ching-Feng Fu, Chia-Ying Lee
  • Patent number: 10998229
    Abstract: Systems, methods, and devices facilitating a transistor with an improved self-aligned contact are provided. In one example, a method comprises depositing a dielectric layer onto a first gate region and a second gate region of a semiconductor device, wherein the first gate region and the second gate region are separated by a substrate contact region, and wherein the dielectric layer has a first etch sensitivity to an inter-layer dielectric; and depositing a sacrificial layer onto the dielectric layer, wherein the sacrificial layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Zhenxing Bi, Juntao Li, Dexin Kong
  • Patent number: 10998360
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by selectively etching a substrate to define a trench. One or more dielectric materials are formed within the trench. A part of the one or more dielectric materials are removed from within the trench to expose a sidewall of the substrate defining the trench. A doped epitaxial material is formed along the sidewall of the substrate.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yueh-Chuan Lee, Chia-Chan Chen
  • Patent number: 10991572
    Abstract: The present disclosure discloses a manufacturing method for a semiconductor apparatus, and relates to the field of semiconductor technologies. Forms of the method include: providing a semiconductor structure, where the semiconductor structure includes: a substrate and an interlayer dielectric layer on the substrate, where the interlayer dielectric layer has an opening for forming a gate; depositing a gate metal layer on the semiconductor structure to fill the opening, where the gate metal layer contains impurity; forming an impurity adsorption layer on the gate metal layer; performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer; and removing the impurity adsorption layer after the first annealing treatment is performed.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Jin E Liang, Le Lv
  • Patent number: 10978459
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having an upper surface; a plurality of first bit line contacts contacting the upper surface of the substrate and a plurality of second bit line contacts contacting the upper surface of the substrate, wherein the plurality of first bit line contacts and the plurality of second bit line contacts are positioned at different levels along a first direction; an air gap disposed between the first bit line contact and the second bit line contact; a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts; and a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 10930648
    Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 23, 2021
    Inventors: Moon Gi Cho, Hyeonuk Kim, Jongchan Shin, Eryung Hwang, Jaeseok Yang, Jinwoo Jeong
  • Patent number: 10910386
    Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: February 2, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
  • Patent number: 10770388
    Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Youngtag Woo, Mahender Kumar, Guillaume Bouche
  • Patent number: 10756198
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 10658366
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Liang Liao, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Wang Zhan
  • Patent number: 10643947
    Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10629483
    Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
  • Patent number: 10614948
    Abstract: A method for forming an inductor structure is provided. The method includes forming a first metal layer over a substrate and forming an oxide layer over the first metal layer. The method also includes forming a magnetic material in and over the oxide layer, and the magnetic material includes a first portion and a second portion, the first portion is directly over the oxide layer, and the second portion is in the oxide layer. The method further includes removing the first portion and a portion of the second portion of the magnetic material to form a magnetic layer, such that a recession is between the magnetic layer and the oxide layer. The method further includes forming a dielectric layer over the magnetic layer, wherein the recession is filled with the dielectric layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yuan-Tai Tseng, Ming-Chyi Liu, Chung-Yen Chou, Chia-Shiung Tsai
  • Patent number: 10600687
    Abstract: Process integration techniques are disclosed that use a carbon fill layer during formation of self-aligned structures. A carbon layer may be placed over an etch stop layer. A cap layer may be provided over the carbon layer. The carbon layer may fill a high aspect ratio structure formed on the substrate. The carbon layer may be removed from a substrate in a highly selective removal technique in a manner that does not damage underlying layers. The carbon layer may fill a self-aligned contact region that is provided for a self-aligned contact process flow. A tone inversion mask may be used to protect multiple self-aligned contact regions. With the blocking mask in place, the carbon layer may be removed from regions that are not the self-aligned contact region. After removal of the blocking mask, the carbon layer which fills the self-aligned contacts may then be removed.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 24, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Aelan Mosden, Kaushik Kumar
  • Patent number: 10580857
    Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Yanzhen Wang, Xinyuan Dou, Hongliang Shen, Sipeng Gu
  • Patent number: 10553693
    Abstract: A semiconductor device includes a substrate having first and second active regions with a field insulating layer therebetween that contacts the first and second active regions, and a gate electrode on the substrate and traversing the first active region, the second active region, and the field insulating layer. The gate electrode includes a first portion over the first active region, a second portion over the second active region, and a third portion in contact with the first and second portions. The gate electrode includes an upper gate electrode having first through third thicknesses in the first through third portions, respectively, where the third thickness is greater than the first thickness, and smaller than the second thickness.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se Ki Hong, Ju Youn Kim, Jin-Wook Kim, Tae Eung Yoon, Tae Won Ha, Jung Hoon Seo, Seul Gi Yun
  • Patent number: 10529552
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed. A surface grafting layer is formed on the underlying structure. A photo resist layer is formed on the surface grafting layer. The surface grafting layer includes a coating material including a backbone polymer, a surface grafting unit coupled to the backbone polymer and an adhesion unit coupled to the backbone polymer.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ling Chang Chien, Chien-Chih Chen, Chin-Hsiang Lin, Ching-Yu Chang, Yahru Cheng
  • Patent number: 10522413
    Abstract: Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Patent number: 10468293
    Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 5, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10460950
    Abstract: There is provided a substrate processing system including an etching apparatus configured to supply a gas containing fluorocarbon to generate plasma so as to perform an etching process on a film including silicon formed on a substrate, wherein the etching process is performed by using plasma through a mask formed on the film including silicon, a film forming apparatus configured to supply a gas containing carbon so as to form a film including carbon on the etched film including silicon.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: October 29, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Akinobu Kakimoto, Yoshinobu Hayakawa, Satoshi Mizunaga, Yasuhiro Hamada, Mitsuhiro Okada
  • Patent number: 10373957
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10373874
    Abstract: A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Balasubramanian Pranatharthiharan
  • Patent number: 10325848
    Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 18, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Andrew M. Greene, Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie
  • Patent number: 10283403
    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Patent number: 10269963
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10242982
    Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Katsunori Onishi, Tek Po Rinus Lee
  • Patent number: 10236253
    Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie
  • Patent number: 10211341
    Abstract: A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Pouya Hashemi, Alexander Reznicek, Joshua M. Rubin, Robin M. Schulz
  • Patent number: 10204825
    Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Ryul Lee, Joong Chan Shin, Dong Jun Lee, Ho Ouk Lee, Ji Min Choi, Ji Young Kim, Chan Sic Yoon, Chang Hyun Cho
  • Patent number: 10192746
    Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 29, 2019
    Assignee: Globalfoundries Inc.
    Inventors: Ashish Kumar Jha, Hui Zhan, Hong Yu, Zhenyu Hu, Haiting Wang, Edward Reis, Charles Vanleuvan
  • Patent number: 10134606
    Abstract: A method of forming patterns may use an organic reflection-preventing film including a polymer having an acid-liable group. A photoresist film is formed on the organic reflection-preventing film. A first area selected from the photoresist film is exposed to generate an acid in the first area. Hydrophilicity of a first surface of the organic reflection-preventing film facing the first area of the photoresist film may be increased. The photoresist film including the exposed first area is developed to remove a non-exposed area of the photoresist film. The organic reflection-preventing film and a target layer are anisotropically etched by using the first area of the photoresist film as an etch mask.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-yoon Woo, Hyun-woo Kim, Ju-hyung An, Jin-young Yoon
  • Patent number: 10134739
    Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti, Rinus Tek Po Lee
  • Patent number: 10115797
    Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yeol Song, Wan-don Kim, Sang-Jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung
  • Patent number: 10109503
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: October 23, 2018
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Jimmy Hwee-Seng Chew, Oviso Dominador Jr Fortaleza, Kian-Hock Lim, Shoa-Siong Lim
  • Patent number: 10109526
    Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Nicholas V. LiCausi, J. Jay McMahon, Ryan S. Smith, Errol Todd Ryan, Shao Beng Law
  • Patent number: 10008577
    Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure above an active region and an isolation region, wherein the gate structure comprises a gate, a first gate cap layer and a first sidewall spacer, removing portions of the first gate cap layer and the first sidewall spacer that are positioned above the active region, while leaving portions of the first gate cap layer and the first sidewall spacer positioned above the isolation region in place, wherein a plurality of spacer cavities are defined adjacent the gate, and forming a replacement air-gap spacer in each of the spacer cavities adjacent the gate and a replacement gate cap layer above the gate, wherein the replacement air-gap spacer comprises an air gap.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Hoon Kim
  • Patent number: 9997412
    Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Ho Bae, Jaeseok Kim, Hoyoung Kim, Boun Yoon, KyungTae Lee, Kwansung Kim, Eunji Park