Formation Of Contacts To Semiconductor By Use Of Metal Layers Separated By Insulating Layers, E.g., Self-aligned Contacts To Source/drain Or Emitter/base (epo) Patents (Class 257/E21.507)
  • Patent number: 10373957
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10373874
    Abstract: A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Balasubramanian Pranatharthiharan
  • Patent number: 10325848
    Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 18, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Andrew M. Greene, Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie
  • Patent number: 10283403
    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Patent number: 10269963
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10242982
    Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Katsunori Onishi, Tek Po Rinus Lee
  • Patent number: 10236253
    Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie
  • Patent number: 10211341
    Abstract: A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Pouya Hashemi, Alexander Reznicek, Joshua M. Rubin, Robin M. Schulz
  • Patent number: 10204825
    Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Ryul Lee, Joong Chan Shin, Dong Jun Lee, Ho Ouk Lee, Ji Min Choi, Ji Young Kim, Chan Sic Yoon, Chang Hyun Cho
  • Patent number: 10192746
    Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 29, 2019
    Assignee: Globalfoundries Inc.
    Inventors: Ashish Kumar Jha, Hui Zhan, Hong Yu, Zhenyu Hu, Haiting Wang, Edward Reis, Charles Vanleuvan
  • Patent number: 10134739
    Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti, Rinus Tek Po Lee
  • Patent number: 10134606
    Abstract: A method of forming patterns may use an organic reflection-preventing film including a polymer having an acid-liable group. A photoresist film is formed on the organic reflection-preventing film. A first area selected from the photoresist film is exposed to generate an acid in the first area. Hydrophilicity of a first surface of the organic reflection-preventing film facing the first area of the photoresist film may be increased. The photoresist film including the exposed first area is developed to remove a non-exposed area of the photoresist film. The organic reflection-preventing film and a target layer are anisotropically etched by using the first area of the photoresist film as an etch mask.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-yoon Woo, Hyun-woo Kim, Ju-hyung An, Jin-young Yoon
  • Patent number: 10115797
    Abstract: In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yeol Song, Wan-don Kim, Sang-Jin Hyun, Jin-wook Lee, Kee-sang Kwon, Ki-hyung Ko, Sung-woo Myung
  • Patent number: 10109503
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: October 23, 2018
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Jimmy Hwee-Seng Chew, Oviso Dominador Jr Fortaleza, Kian-Hock Lim, Shoa-Siong Lim
  • Patent number: 10109526
    Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Nicholas V. LiCausi, J. Jay McMahon, Ryan S. Smith, Errol Todd Ryan, Shao Beng Law
  • Patent number: 10008577
    Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure above an active region and an isolation region, wherein the gate structure comprises a gate, a first gate cap layer and a first sidewall spacer, removing portions of the first gate cap layer and the first sidewall spacer that are positioned above the active region, while leaving portions of the first gate cap layer and the first sidewall spacer positioned above the isolation region in place, wherein a plurality of spacer cavities are defined adjacent the gate, and forming a replacement air-gap spacer in each of the spacer cavities adjacent the gate and a replacement gate cap layer above the gate, wherein the replacement air-gap spacer comprises an air gap.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Hoon Kim
  • Patent number: 9997412
    Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Ho Bae, Jaeseok Kim, Hoyoung Kim, Boun Yoon, KyungTae Lee, Kwansung Kim, Eunji Park
  • Patent number: 9953985
    Abstract: A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-gi Kim, Sang-moo Jeong, Seon-ju Kim, Hye-won Kim
  • Patent number: 9935047
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kio-Chio Liu
  • Patent number: 9899224
    Abstract: A method is provided for forming an ultra-shallow boron doping region in a semiconductor device. The method includes depositing a diffusion filter layer on a substrate, the diffusion filter containing a boron nitride layer, a boron oxynitride layer, a silicon nitride layer, or a silicon oxynitride layer, and depositing a boron dopant layer on the diffusion filter layer, the boron dopant layer containing boron oxide, boron oxynitride, or a combination thereof, with the proviso that the diffusion filter layer and the boron dopant layer do not contain the same material. The method further includes heat-treating the substrate to form the ultra-shallow boron dopant region in the substrate by controlled diffusion of boron from the boron dopant layer through the diffusion filter layer and into the substrate.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 20, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Steven P. Consiglio, Robert D. Clark, David L. O'Meara
  • Patent number: 9899322
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9870951
    Abstract: A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: January 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9836356
    Abstract: The present invention relates to a reliable method and device for backup of data from a first network to a second network. The method and device of the present invention can for example be used for a backup of voluminous data from the first to the second network via a link with a relatively small bandwidth.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: December 5, 2017
    Assignee: Thomson Licensing
    Inventors: Serge De France, Nicolas Le Scouarnec, Gilles Straub
  • Patent number: 9837313
    Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Byron Neville Burgess, John K. Zahurak
  • Patent number: 9831343
    Abstract: A semiconductor device having n-type field-effect-transistor (NFET) structure and a method of fabricating the same are provided. The NFET structure of the semiconductor device includes a silicon substrate, at least one source/drain portion and a cap layer. The source/drain portion can be disposed within the silicon substrate, and the source/drain portion comprises at least one n-type dopant-containing portion. The cap layer overlies and covers the source/drain portion, and the cap layer includes silicon carbide (SiC) or silicon germanium (SiGe) with relatively low germanium concentration, thereby preventing n-type dopants in the at least one n-type dopant-containing portion of the source/drain portion from being degraded after sequent thermal and cleaning processes.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chii-Horng Li, Chien-I Kuo, Lilly Su, Chien-Chang Su, Yi-Kai Tseng, Ying-Wei Li
  • Patent number: 9799567
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Patent number: 9793156
    Abstract: Methods are provided for fabricating self-aligned, low resistance metal interconnect structures, as well as semiconductor devices comprising such metal interconnect structures. A first metal line is formed in a first insulating layer. An etch stop layer is formed by selectively depositing dielectric material on the first insulating layer. A second insulating layer is formed over the etch stop layer and the first metal line, and an opening is etched in the second insulating layer selective to the etch stop layer to prevent etching of the first insulating layer. The opening is filled with a metallic material to form a second metal line in contact with the first metal line. The first and second metal lines are formed with aspect ratios that are less than 2.5 to minimize resistivity of the metal lines. The first and second metal lines collectively form a single metal line of an interconnect structure.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 17, 2017
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 9728419
    Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9728454
    Abstract: The present invention provides a semiconductor structure, includes a substrate, a dielectric layer disposed on the substrate, a first gate structure and a second gate structure disposed in the dielectric layer, a hard mask disposed in the dielectric layer, where the hard mask covers a sidewall of the first gate structure, and covers the second gate structure, and a contact structure disposed in the dielectric layer. The contact structure at least crosses over the hard mask. The contact structure includes a first contact portion and a second contact portion. The first contact portion contacts the first gate structure directly, the second contact portion contacts the substrate directly, and the hard mask is disposed between the first contact portion and the second contact portion.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 8, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen, Xing Hua Zhang
  • Patent number: 9711402
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a source/drain feature over a substrate, forming a dielectric layer over the source/drain feature, forming a contact trench through the dielectric layer to expose the source/drain feature, depositing a titanium nitride (TiN) layer by a first atomic layer deposition (ALD) process in the contact trench and depositing a cobalt layer over the TiN layer in the contact trench.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Patent number: 9698101
    Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 4, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Andrew M. Greene, Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie
  • Patent number: 9640482
    Abstract: The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: May 2, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Min-Chuan Tsai, Chun-Chieh Chiu, Li-Han Chen, Yen-Tsai Yi, Wei-Chuan Tsai, Kuo-Chin Hung, Hsin-Fu Huang, Chi-Mao Hsu
  • Patent number: 9633853
    Abstract: A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 25, 2017
    Assignee: IMEC VZW
    Inventors: Antony Premkumar Peter, Marc Schaekers
  • Patent number: 9595477
    Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: March 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 9570353
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming of an interlayer insulating film on a semiconductor substrate; etching the interlayer insulating film to form a contact hole and an alignment hole wider than the contact hole; depositing a first metal layer having a thickness thicker than a half of the width of the contact hole and thinner than a half of the width of the alignment hole; etching the first metal layer so that a bottom surface of the alignment hole are exposed and the first metal layer remains covering a bottom surface of the contact hole; treating the semiconductor substrate based on the position of the alignment hole; and cutting a part of the semiconductor substrate including the alignment hole to divide a semiconductor device having the contact hole from the semiconductor substrate.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: February 14, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoru Kameyama, Shinya Iwasaki, Yuki Yakushigawa
  • Patent number: 9570536
    Abstract: The methods for forming an inductor structure are provided. The method includes forming an oxide layer over a substrate, and the layer includes an opening. The method includes forming a magnetic material over the oxide layer and in the opening and forming a patterned photoresist layer over the magnetic material, wherein the patterned photoresist layer overlaps the opening. The method further includes performing an etching process on the magnetic material using the patterned photoresist as a mask.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yuan-Tai Tseng, Ming-Chyi Liu, Chung-Yen Chou, Chia-Shiung Tsai
  • Patent number: 9559060
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 9484254
    Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 9466521
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9443929
    Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Shreesh Narasimha
  • Patent number: 9396962
    Abstract: An etching method can etch a region formed of silicon oxide. The etching method includes an exposing process (process (a)) of exposing a target object including the region formed of the silicon oxide to plasma of a processing gas containing a fluorocarbon gas, etching the region, and forming a deposit containing fluorocarbon on the region; and an etching process (process (b)) of etching the region with a radical of the fluorocarbon contained in the deposit. Further, in the method, the process (a) and the process (b) are alternately repeated.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 19, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Keiji Kitagaito, Takayuki Katsunuma, Masanobu Honda
  • Patent number: 9379118
    Abstract: Semiconductor devices and methods of fabricating the same are disclosed. The methods include forming a first interlayer insulating layer and a conductive contact plug that penetrates the first interlayer insulating layer, forming a second interlayer insulating layer and a first interlayer wiring on the first interlayer insulating layer. The first interlayer wiring penetrates the second interlayer insulating layer and overlaps the first metal contact plug. The second interlayer insulating layer is etched using the first interlayer wiring as a mask until the first metal contact plug is exposed, and an exposed portion of the conductive contact plug is etched using the first interlayer wiring as the mask.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Min Park
  • Patent number: 9324650
    Abstract: A method of forming a fully aligned via connecting two metal lines on different Mx levels by forming a recessed opening above a first metal line in a first ILD; forming a cap on the first ILD and in the recessed openings; forming a second ILD on the cap; forming a metal trench hardmask above the second ILD, forming a metal trench pattern in the metal trench hardmask; forming a via pattern that is self aligned to the metal trench pattern and above a portion of the first metal line; forming a via opening exposing the first metal line by transferring the via pattern and metal trench pattern to lower levels, the via pattern is self-aligned to the recessed opening; and forming a via and a third metal line in the via opening and the transferred metal trench pattern, respectively.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Nicholas C. Fuller, Elbert E. Huang, Satyanarayana V. Nitta, David L. Rath
  • Patent number: 9324652
    Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Hui Jae Yoo, Yan A. Borodovsky, Florian Gstrein, David N. Shykind, Kevin L. Lin
  • Patent number: 9324711
    Abstract: A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 26, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Kazushi Fujita
  • Patent number: 9312170
    Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 12, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Walter Blatchford, Scott William Jessen
  • Patent number: 9287273
    Abstract: The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: March 15, 2016
    Assignee: IMEC VZW
    Inventors: Lars-Ake Ragnarsson, Tom Schram, Hendrik F. W. Dekkers, Soon Aik Chew
  • Patent number: 8993392
    Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: March 31, 2015
    Assignee: Broadcom Corporation
    Inventors: Wei Xia, Xiangdong Chen
  • Patent number: 8969201
    Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Ding-Kang Shih, Chin-Hsiang Lin, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8970018
    Abstract: A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Jay M. Gambetta