Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

Abstract: In a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming patterned second ILD layers and first wiring patterns, after the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layers and the first wiring patterns.

Abstract: A method of making an integrated circuit includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.

Abstract: A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

Abstract: A method of manufacturing semiconductor devices, such as QFN/BGA flip-chip type packages, arranging on a leadframe one or more semiconductor chips or dice having a first side facing towards the leadframe and electrically coupled therewith and a second side facing away from the leadframe. The method also includes molding an encapsulation on the semiconductor chip(s) arranged on the leadframe, where the encapsulation has an outer surface opposite the leadframe and comprises laser direct structuring (LDS) material. Laser direct structuring processing is applied to the LDS material of the encapsulation to provide metal vias between the outer surface of the encapsulation and the second side of the semiconductor chip(s) and as well as a metal pad at the outer surface of the encapsulation.

Abstract: A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.

Abstract: Embodiments of the present invention provide a semiconductor device capable of improving both the thermal stability and contact resistance and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device may comprise: a contact plug over a substrate, wherein the contact plug includes: a silicide layer having a varying carbon content in a film, and a metal material layer over the silicide layer.

Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate, performing a deposition process to form a nitride layer to cover the substrate and the gate structure, performing an in-situ annealing process to the nitride layer, and performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on a sidewall of the gate structure.

Abstract: A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, a metal containing layer disposed on the first conductive feature, and a second conductive feature disposed on and through the metal containing layer and in physical contact with the first conductive feature. The metal containing layer includes an M-O—X group, M representing a metal atom, O representing an oxygen atom, and X representing an element other than hydrogen.

Abstract: An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base, in which a plurality of bit lines extending in a first direction and a groove located between two adjacent ones of the bit lines are provided on the base; forming an initial contact layer and an initial protection layer filling the groove, in which the initial contact layer is in contact with the base, the initial protection layer is located on the initial contact layer; patterning the initial contact layer and the initial protection layer to form contact layers that are discrete from each other and protection layers that are discrete from each other; and forming a dielectric layer between two adjacent ones of the contact layers, in which the dielectric layer is further located between two adjacent ones of the protection layers, a material of the dielectric layer is different from a material of the protection layer.

Abstract: A method for manufacturing a wiring substrate includes forming a second resin insulating layer on a first resin insulating layer such that the second resin insulating layer is in contact with a surface of the first resin insulating layer, irradiating laser upon the second resin insulating layer such that a recess penetrating through the second resin insulating layer and exposing the first resin insulating layer is formed, and forming a conductor layer including conductor material filled in the recess formed through the second resin insulating layer such that the conductor layer is embedded in the second resin insulating layer. The second resin insulating layer are formed on the surface of the first resin insulating layer such that the first resin insulating layer and the second resin insulating layer have different processability with respect to the laser.

Abstract: A device design file and material properties are inputted into a neural network module configured to operate a generative adversarial network. A process parameter is determined based on a device design file and material properties inputs using the generative adversarial network. This can be used to provide process parameters during semiconductor device design or manufacturing.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate and a plurality of discrete bit line structures located on the substrate, the bit line structure having a metal layer therein, a top surface of the metal layer being lower than a top surface of the bit line structure; forming a first isolation film filled between the adjacent bit line structures, a top surface of the first isolation film being higher than the top surface of the metal layer and lower than the top surface of the bit line structure; forming a first dielectric film on the top and sidewalls of the bit line structure and on the top surface of the first isolation film; and etching to remove the first dielectric film on the top of the bit line structures and the top surface of the first isolation film to form a first dielectric layer, and etching to remove the first isolation film exposed by the first dielectric layer to form a first isolation layer exactly below the first dielectric layer.

Abstract: A display device includes a substrate, an active pattern disposed on the substrate, a gate electrode overlapping the active pattern, an inorganic insulation layer covering the active pattern, a source metal pattern and an etch-delaying pattern. The source metal pattern includes a first portion that is disposed on the inorganic insulation layer, and a second portion that passes through the inorganic insulation layer and electrically contacts the active pattern. The etch-delaying pattern is disposed between the active pattern and the first portion of the source metal pattern, contacts the second portion of the source metal pattern, and includes a different material from the inorganic insulation layer.

Abstract: An integrated circuit device includes a substrate, a peripheral circuit structure disposed on the substrate, the peripheral circuit structure including a peripheral circuit and a lower wiring connected to the peripheral circuit, a conductive plate covering a portion of the peripheral circuit structure, a cell array structure disposed on the peripheral circuit structure with the conductive plate therebetween, the cell array structure including a memory cell array and an insulation layer surrounding the memory cell array, a through hole via passing through the insulation layer in a direction vertical to a top surface of the substrate to be connected to the lower wiring, and an etch guide member disposed in the insulation layer at the same level as the conductive plate to contact a portion of the through hole via.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; and a first gate stack positioned on the substrate and including: a first gate dielectric layer positioned on the substrate; a first gate protection layer positioned on the first gate dielectric layer and including titanium silicon nitride; a first work function layer positioned on the first gate protection layer; and a first gate filler layer positioned on the first work function layer.

Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

Abstract: A system on wafer assembly structure and an assembly method thereof. The system on wafer assembly structure comprises: a wafer layer, a dielectric layer and a circuit board layer sequentially stacked, and each provided with a bonding region, a testing region and an alignment region, respectively, a first assembly, and a second assembly, wherein the first assembly is arranged on one side of the wafer layer far away from the dielectric layer, and comprises a bearing portion and at least one latch portion connected with each other, and the bearing portion is detachably connected with the wafer layer. The second assembly is at least partially arranged around the first assembly. The second assembly has a hole portion for accommodating a latch portion, and the inner diameter of the hole portion is larger than the outer diameter of the latch portion.

Abstract: Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure with first material layers and second material layers that are alternately stacked with each other, forming a first opening that passes through the stacked structure, forming second openings between the first material layers, forming first sacrificial layers in the second openings, forming first isolation layers that protrude into the first opening by oxidizing the first sacrificial layers, forming mold patterns on the first material layers between the protruding portions of the first isolation layers, forming third openings by etching portions of the first isolation layers that are exposed between the mold patterns, forming second sacrificial layers in the third openings, and forming second isolation layers that protrude farther toward the center of the first opening than the mold patterns by oxidizing the second sacrificial layers.

Abstract: A semiconductor structure includes: a first base having a first face, a second base having a second face and a welded structure. The first base is provided with an electrical connection column protruding from the first face. A conductive column is provided in the second base, and a first groove and a second groove are further provided at the second face. The first groove is located above the conductive column, and the second groove exposes at least part of a side surface of the conductive column. The protruding portion of the electrical connection column is located in the second groove, and part of a side surface of the electrical connection column and part of the side surface of the conductive column overlap in staggered way in a direction perpendicular to the first face or the second surface. At least part of the welded structure is filled in the first groove.

Abstract: A semiconductor structure, a method for forming a semiconductor structure, a stacked structure, and a wafer stacking method are provided. The semiconductor structure includes: a semiconductor substrate; a first dielectric layer on a surface of a semiconductor substrate; a top metal layer, in which the top metal layer is located in the first dielectric layer, and the top metal layer penetrates through the first dielectric layer; and a buffer layer located between the top metal layer and the first dielectric layer.

Abstract: The present application provides methods for manufacturing BiCMOS device and the heterojunction bipolar transistor (HBT) contained therein. In formation of a raised extrinsic base region of the heterojunction bipolar transistor, the epitaxial silicon is doped with carbon (C) and boron (B) in situ and is doped with a metal catalyst simultaneously, then, the plasma treatment and the laser annealing are conducted to the carbon, and a graphene region is formed in the Si epitaxial layer. Because of high conductivity of graphene, the base resistance of the SiGe HBT can be reduced to enhance its radiation performance. The above method can be applied to conventional BiCMOS device process by performing plasma treatment and laser annealing to the doped carbon to form the graphene region in the extrinsic base region. The method is easily controlled and integrated into conventional BiCMOS device process.

Abstract: Systems and methods for lighting system lens heating are described. The systems and methods include a substantially clear thermoplastic substrate; and a conductive ink or film circuit on the thermoplastic substrate.

Abstract: A semiconductor structure and a forming method thereof are provided, and the forming method includes: providing a base; forming, on the base, a plurality of conductive function layers extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer located on the base between the conductive function layers, and a blocking structure located in the conductive function layer, the blocking structure segmenting the conductive function layers located on two sides of the blocking structure in the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive function layers, and the blocking structure; etching the top dielectric layer located above a junction of the blocking structure and the conductive function layer and a part of the blocking structure located at a side wall of the conductive function layer, to form a via running through the top dielectric layer and exposing a part of a top and a part of a side wall of the conductive fu

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a first etch stop layer, a second etch stop layer, and an interlayer insulation layer that are stacked on the gate structure, and a contact plug penetrating the interlayer insulation layer, the second etch stop layer, and the first etch stop layer and contacting a sidewall of the gate structure. The contact plug includes a lower portion having a first width and an upper portion having a second width. A lower surface of the contact plug has a stepped shape.

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.

Abstract: A method for cleaning contacts on a substrate incorporates ion control to selectively remove oxides. The method includes exposing the substrate to ions of an inert gas, supplying a first RF frequency of a first bias power supply to a substrate support, supplying a second RF frequency of a second bias power supply to a substrate support, and adjusting a first power level of the first RF frequency and a second power level of the second RF frequency to selectively remove oxide from at least one contact on the substrate while inhibiting sputtering of polymer material wherein the oxide removal is selective over removal of polymer material surrounding the at least one contact.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Abstract: A semiconductor memory device and a manufacturing method of a semiconductor memory device are described. The semiconductor memory device includes a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked, a first channel structure penetrating the gate stack structure, a first contact structure connected to the first channel structure, the first contact structure extending onto the gate stack structure, a bit line disposed on the first contact structure and being in contact with the first contact structure, a tunnel insulating layer disposed between the first channel structure and the gate stack structure, a data storage layer disposed between the tunnel insulating layer and the gate stack structure, and a blocking insulating layer disposed between the data storage layer and the gate stack structure, the blocking insulating layer extending between the first contact structure and the gate stack structure.

Abstract: A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.

Abstract: The present invention relates to a method for manufacturing composite solder balls that are metallized on the surface and calibrated, these balls comprising a core consisting of a spherical support particle of diameter D0 made of expanded polystyrene and having an intergranular porosity of at least 50%, and a shell covering said support particle and formed by a plurality of metallic surface layers. The present invention also relates to balls that can be obtained by the method according to the invention, as well as to the use thereof for the assembly of electronic boards.

Abstract: A method includes a gate structure, gate spacers, a gate helmet, a metal cap, and a gate contact. The gate structure is over a substrate. The gate spacers are on either side of the gate structure. The gate helmet is over the gate structure and the gate spacers. The metal cap is in the gate helmet over the gate structure. The gate contact is over the metal cap. The gate contact forms an interface with the metal cap at a different level height than top segments of the gate spacers.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate including an element isolation film and an active region defined by the element isolation film; a word line crossing the active region in a first direction; and a bit line structure on the substrate and connected to the active region, the bit line structure extending in a second direction crossing the first direction, wherein the bit line structure includes a first cell interconnection film including an amorphous material or ruthenium, a second cell interconnection film on and extending along the first cell interconnection film and including ruthenium, and a cell capping film on and extending along the second cell interconnection film.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.

Abstract: A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on upper interconnection balls of the stackable package to force upper portions of the upper interconnection balls into the mold. However, lower portions of the upper interconnection balls are exposed within a space between the compliant surface and a substrate of the stackable package. The space is filled with a dielectric material to form a package body. The package body is formed while at the same time exposing the upper portions of upper interconnection balls from the package body in a single encapsulation operation. By avoiding selective removal of the package body to expose the upper interconnection balls, the number of operations as well as cost to manufacture the stackable package is minimized.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain region positioned in the substrate; a common source region positioned in the substrate and opposing to the drain region; a bit line structure including a bit line conductive layer positioned on the substrate and electrically coupled to the common source region; a cell contact positioned on the substrate, adjacent to the bit line structure, and electrically connected to the drain region; a landing pad positioned above the bit line conductive layer and electrically connected to the cell contact; and an air gap positioned between the landing pad and the bit line conductive layer.

Abstract: A semiconductor structure and a method of fabricating therefor are disclosed. A second contact pad (500) is arranged lateral to a first contact pad (420) in an interconnect structure (400). As a result, during fabrication of the interconnect structure (400), the first contact pad (420) will not be present alone in a large bland area, due to the presence of the second contact pad (500). Thus, a pattern feature for the first contact pad (420) will not be over-resolved, increasing formation accuracy of the first contact pad (420) and thus guaranteeing good electrical transmission performance of the resulting interconnect structure (400).

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

Abstract: Embodiments of multi-zone showerheads are provided herein. In some embodiments, a multi-zone showerhead includes: a body having an outer surface and including a plurality of fluidly independent plenums; and a plurality of gas distribution plugs extending through the body, wherein at least one gas distribution plug includes a first internal gas passageway coupling a first plenum of the plurality of fluidly independent plenums to the outer surface and a second internal gas passageway coupling a second plenum of the plurality of fluidly independent plenums to the outer surface. In some embodiments, the body can include: a top plate; a bottom plate; and one or more intermediate plates disposed between the top plate and the bottom plate, wherein individual plenums of the plurality of fluidly independent plenums are respectively defined between adjacent plates of the top plate, the bottom plate, and the one or more intermediate plates.

Abstract: A method for passivating sidewalls of patterned semiconductor wafer including ridge(s). The method includes: depositing first layer of first dielectric material on pattern surface of said wafer; etching portion of first layer to obtain tapered portions of first dielectric material along sidewall(s) of ridge(s); depositing second layer of second dielectric material on tapered portions and said wafer; depositing photo-sensitive material on second layer; aligning mask with photo-sensitive material, wherein portion(s) of photo-sensitive material corresponding to top surface of ridge(s) is/are unmasked, and remaining portion is masked; applying developing solution and exposing photo-sensitive material to remove portion(s) of photo-sensitive material; etching portion(s) of second layer that is/are deposited on top surface of ridge(s); and removing photo-sensitive material.