Abstract: A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. The I/O terminal count of the semiconductor die is increased by forming solder bumps in the non-active area of the wafer. An encapsulant is formed over the solder bumps. The encapsulant provides structural support for the solder bumps formed in the non-active area of the semiconductor wafer. The semiconductor wafer undergoes grinding after forming the encapsulant to expose the solder bumps. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a package substrate with solder paste or socket.

Abstract: A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

Abstract: A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing the connection terminals of the first plate body 101. The connection terminals of the first and second plate bodies are connection terminals formed as projections on the surfaces of the first and second plate bodies. A conductive substance 108 is accumulated to cover at least a part of each side face of the connection terminals opposed to each other of the first and second plate bodies, and the connection terminals thus opposed are connected to each other via the conductive substance. The package thus formed is ready for a high-pin-count, narrow-pitch configuration of a next-generation semiconductor chip, and exhibits excellent productivity and reliability.

Abstract: A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and having a plurality of wiring units, wherein each of the wiring units has a conductive pad, a conductive via and a conductive trace connecting the conductive pad and the conductive via, the conductive trace having at least a first through opening for exposing a portion of the first passivation layer; and a second passivation layer disposed on the first passivation layer and the redistribution layer, the second passivation layer being filled in the first through opening such that the first and second passivation layers are bonded to each other with the conductive trace sandwiched therebetween, thereby preventing delamination of the conductive trace from the second passivation layer.

Abstract: Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof.

Abstract: In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

Abstract: An integrated circuit (IC) device is provided. The IC device includes a substrate, an IC die coupled to the substrate, and a first wirelessly enabled functional block formed on the IC die. The first wirelessly enabled functional block is configured to wirelessly communicate with a second wirelessly enabled functional block formed on the substrate.

Abstract: A process for replacing a semiconductor chip of such a flip-chip module and a suitable flip-chip module and an apparatus for implementing the method are disclosed. The flip-chip module comprises at least one semiconductor chip and a substrate. The semiconductor chip comprises contact posts on a surface that are disposed at right angles to the surface. With these contact posts it is connected with contact points of the substrate via a soldered connection. The contact posts completely cover the contact points with their end faces. Due to this it is possible to completely press the solder between the contact posts and contact points out of the intermediate area between the contact points and the contact posts after a renewed heating. This permits a renewed attachment of a further semiconductor chip.

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling the recessed contact pad partially with solder; and forming an under-bump metal having a base surface in electrical contact with the conductive pillar, and having sides that extend away from the face surface of the substrate and further extend beyond the base surface.

Abstract: Device and method for an electronic device package is disclosed. The electronic device package includes a first pad, a second pad and an encapsulation surrounding the first and second pad, wherein the encapsulation includes a first opening underneath the first pad and a second opening underneath the second pad. A first bump is arranged in the first opening and a second bump is arranged in the second opening, wherein the encapsulation mechanically locks the first bump to the first pad and the second bump to the second pad.

Abstract: A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.

Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.

Abstract: A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 ?m aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 ?m. Another possibility is provide an extra 0.6 ?m aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 ?m aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 ?m and another barrier layer of 60 nm.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate; forming a rounded interconnect in the vertical insertion cavity, the rounded interconnect nonconformal to the vertical insertion cavity; and mounting an integrated circuit device on the component connector.

Abstract: A semiconductor device has a conductive via formed through in a first side of the substrate. A first interconnect structure is formed over the first side of the substrate. A semiconductor die or component is mounted to the first interconnect structure. An encapsulant is deposited over the first interconnect structure and semiconductor die or component. A portion of a second side of the substrate is removed to reduce its thickness and expose the TSV. A second interconnect structure is formed over the second side of the substrate. The encapsulant provides structural support while removing the portion of the second side of the substrate. The second interconnect structure is electrically connected to the conductive via. The second interconnect structure can include a redistribution layer to extend the conductivity of the conductive via. The semiconductor device is mounted to a printed circuit board through the second interconnect structure.

Abstract: A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer.

Abstract: A substrate including therein a plurality of conductor layers laminated via insulating layers, the substrate mounting at least one semiconductor integrated circuit, wherein the substrate includes a first electrode terminal connected to the semiconductor integrated circuit, a second electrode terminal connected to a terminal on an upper substrate arranged in a layer over the substrate, and on at least part of the perimeter of the first and second electrode terminals, a third electrode terminal located outside the outer edge of the upper substrate.

Abstract: A die level integrated interconnect decal manufacturing method and apparatus for implementing the method. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

Abstract: A semiconductor device is made by providing a semiconductor wafer having an active surface, forming an under bump metallization layer on the active surface of the semiconductor wafer, forming a first photosensitive layer on the active surface of the semiconductor wafer, exposing a selected portion of the first photosensitive layer over the under bump metallization layer to light, removing a portion of a backside of the semiconductor wafer, opposite to the active surface, prior to developing the exposed portion of the first photosensitive layer, developing the exposed portion of the first photosensitive layer after removing the portion of the backside of the semiconductor wafer, and depositing solder material over the under bump metallization layer to form solder bumps. The remaining portion of the first photosensitive layer is then removed. A second photosensitive layer or metal stencil can be formed over the first photosensitive layer.

Abstract: An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area.

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved by forming different height first and second conductive layer above a substrate. A first patterned photoresist layer is formed over the substrate. A first conductive layer is formed in the first patterned photoresist layer. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed over the substrate. A second conductive layer is formed in the second patterned photoresist layer. The height of the second conductive layer, for example 25 micrometers, is greater than the height of the first conductive layer which is 5 micrometers. The first and second conductive layers are interposed between each other close together to minimize pitch and increase I/O count while maintaining sufficient spacing to avoid electrical shorting after bump formation. An interconnect structure is formed over the first and second conductive layers.

Abstract: An electrical interconnect within a semiconductor device consists of a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, first barrier layer, adhesion layer, and seed layer are formed over the substrate. An inner core pillar including a hollow interior is centered over and formed within a footprint of the contact pad. A second barrier layer and a wetting layer are formed over the single cylindrical inner core pillar and hollow interior. A spherical bump is formed around the second barrier layer, wetting layer, and single cylindrical inner core pillar. A footprint of the spherical bump encompasses the footprint of the contact pad. The spherical bump is electrically connected to the contact pad.

Abstract: Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.

Abstract: A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.

Abstract: A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. An encapsulating body encapsulates the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. At least one of the second conducting element, third conducting element, and fourth conducting element extend over the semiconductor chip and the encapsulating body.

Abstract: Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer.

Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer.

Abstract: A contact structure having both a compliant bump and a testing area and a manufacturing method for the same is introduced. The compliant bump is formed on a conductive contact of the silicon wafer or a printed circuit board. The core of the bump is made of polymeric material, and coated with a conductive material. In particular, the compliant bump is disposed on the one side of the conductive contact structure that includes both the bump and the testing area, wherein the testing area allows the area to be functionality tested, so as to prevent damage of the coated conductive material over the compliant bump during a probe testing.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract: A method of manufacturing semiconductor devices is provided, in which a resin sealing structure includes an interconnection substrate board, semiconductor chips, a heat radiation plate, and sealing resin. The method is achieved by cutting the heat radiation plate by a plate cutting blade in a first direction along a first heat radiation plate cutting line; by cutting the heat radiation plate by the plate cutting blade in a second direction along a second heat radiation plate cutting line, after cutting in the first direction by the plate cutting blade; and by cutting the interconnection substrate board and the sealing resin along first and second interconnection substrate board cutting lines by a substrate board cutting blade in the first direction and the second direction, respectively. The second heat radiation plate cutting line and the second interconnection substrate board cutting line correspond to each other in position in a third direction orthogonal to the first direction and the second direction.

Abstract: An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon.

Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Abstract: To prevent formation of entrapped underfill material between solder balls and bonding bumps, fast temperature ramping is employed during a chi assembly after application of an underfill material prior to bonding. Voids formed within the underfill material are subsequently removed by curing the underfill material in a pressurized environment. Temperature cycling on the underfill material is limited during the bonding process in order to maintain viscosity of the underfill material prior to the cure process in the pressurized environment. Further, the underfill material is subjected to the pressurized environment until the cure process is complete to prevent re-formation of voids. The cure process can be a constant temperature or a multi-temperature process including temperature ramping. Further, the cure process can be a constant pressure process or a pressure cycling process that accelerates removal of the voids.

Abstract: A description is given of a device, including a semiconductor chip, a first metal layer laterally extending over the semiconductor chip, the first metal layer having a first thickness. A dielectric layer laterally extends over the first metal layer, and a second metal layer laterally extends over the dielectric layer, the second metal layer having a second thickness that is at least four times larger than the first thickness.

Abstract: An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

Abstract: Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.

Abstract: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The method is carried out by forming solder pads on a substrate by wet etching, flipping a semiconductor chip having a plurality of connection bumps formed on an active surface of the semiconductor chip for the connection bumps to be mounted by compression on the solder pads of the substrate correspondingly, at a temperature of the compression between the connection bumps and the solder pads lower than the melting points of the solder pads and the connection bumps, so as to allow the semiconductor chip to be engaged with and electrically connected to the substrate through the connection bumps and the solder pads, thereby enhancing the bonding strength of the solder pads and the connection bumps and increasing the fabrication reliability.

Abstract: A single-layer board on chip package substrate and a method of manufacturing the same are disclosed. The single-layer board on chip package substrate in accordance with an embodiment of the present invention includes an insulator, which has a window perforated therethrough, a wiring pattern, a wire bonding pad and a solder ball pad, which are embedded in one surface of the insulator, and a solder resist layer, which is formed on the one surface of the insulator such that the solder resist layer covers the wiring pattern but at least portions of the wire bonding pad and the solder ball pad are exposed.

Abstract: A method of manufacturing a ball grid array, BGA, integrated circuit package, comprising forming a double sided printed circuit board, PCB, with blind vias interconnecting electrically the circuits on the opposed surfaces of the PCB, with at least one through-hole to allow fluid or gas to pass through the PCB, and an integrated circuit connected to the printed circuit on one side of the PCB; soldering a lid onto the said one side of the PCB to enclose the integrated circuit, whilst allowing thermally expanding gas or fluid to escape through the or each through-hole, whereby to form a package which is hermetically sealed except for the or each through-hole, and which has a cavity between the integrated circuit and the lid; applying a BGA to the side of the PCB opposed to the said one side, whereby to solder the balls of the BGA to respective portions of the printed circuit and to align one of the balls axially with each through-hole; and soldering the ball or balls into the through-hole, or into each respectiv

Abstract: A method of attaching a solder ball to a bonding pad includes disposing flux on the bonding pad, attaching a conductive metal ring to the pad using the flux, and placing the solder ball in the ring. A reflow operation is performed that secures the ring to the pad and melts the solder ball into and around the ring. A solder joint is formed between solder ball and the pad, with the ring secured within the ball. Use of the ring allows for higher stand-off height to be achieved with similar solder ball size, without having to use bigger ball size as in the conventional method, which causes solder ball bridging. With higher stand-off height, better board level reliability performance can be obtained.

Abstract: A manufacturing method for a bonded structure, in which a semiconductor device is bonded to an electrode by a bonding portion, the method including: first mounting a solder ball, in which a surface of a Bi ball is coated with Ni plating, on the electrode that is heated to a temperature equal to or more than a melting point of Bi; second pressing the solder ball against the heated electrode, cracking the Ni plating, spreading molten Bi on a surface of the heated electrode, and forming a bonding material containing Bi-based intermetallic compound of Bi and Ni; and third mounting the semiconductor device on the bonding material.

Abstract: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.