Mounting On Semiconductor Conductive Member (epo) Patents (Class 257/E21.513)
  • Patent number: 9865550
    Abstract: A pattern generator includes and upper chip and one or more lower chips. The upper chip includes an upper substrate and a plurality of conductive plates on the upper substrate. The plurality of conductive plates is arranged as an array. The one or more lower chips include one or more lower substrates and a plurality of driving circuits each on one of the one or more lower substrates and electrically coupled with a corresponding one of the plurality of conductive plates. The upper chip and the one or more lower chips are stacked one over another.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hao-Chieh Chan
  • Patent number: 9853013
    Abstract: According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, wherein these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, and includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: December 26, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaru Koyanagi
  • Patent number: 8969135
    Abstract: A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the down bond area from die attach material, which may occur during a die attach process.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peng Liu, Qingchun He, Zhaobin Qi, Liqiang Xu, Tong Zhao
  • Patent number: 8936966
    Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 8912088
    Abstract: The present invention provides a transfer substrate for transferring a metal wiring material to a transfer-receiving object, the transfer substrate comprising a substrate, at least one metal wiring material formed on the substrate and an underlying metal film formed between the substrate and the metal wiring material, wherein the metal wiring material is a molded article prepared by sintering, e.g., gold powder having a purity of 99.9% by weight or more and an average particle size of 0.01 ?m to 1.0 ?m and the underlying metal film is composed of a metal such as gold or an alloy. The transfer substrate is capable of transferring a metal wiring material to the transfer-receiving object even at a temperature for heating the transfer-receiving object of 80 to 300° C.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 16, 2014
    Assignee: Tanaka Kikinzoku Kogyo K.K.
    Inventors: Toshinori Ogashiwa, Masaaki Kurita, Takashi Nishimori, Yukio Kanehira
  • Patent number: 8664749
    Abstract: A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang, Jung-Chih Hu, Wen-Chih Chiou
  • Patent number: 8153473
    Abstract: A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: April 10, 2012
    Assignee: Empirion, Inc.
    Inventors: Ashraf W. Lotfi, Douglas Dean Lopata, John David Weld, Mathew A. Wilkowski
  • Patent number: 8110434
    Abstract: A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring network is provided in a region except the terminal region on the first main surface. A second wiring network is provided on the second main surface. Distance from the side including the curved portion to the first wiring network is larger than distance from at least one of the other sides to the first wiring networks, and distance from the side including the curved portion to the second wiring network is larger than distance from at least one of the other sides to the second wiring networks.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Okada, Kiyokazu Okada, Akinori Ono, Taku Nishiyama
  • Patent number: 8088647
    Abstract: Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: January 3, 2012
    Assignee: Broadcom Corporation
    Inventors: Kunzhong (Kevin) Hu, Edward Law
  • Patent number: 8080445
    Abstract: A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: December 20, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 8076184
    Abstract: A semiconductor device has a base carrier with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base carrier. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base carrier and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base carrier. A portion of the second surface of the base carrier is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: December 13, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Emmanuel A. Espiritu, Henry D. Bathan, Dioscoro A. Merilo
  • Patent number: 8072062
    Abstract: A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: December 6, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George R. Leal, Jie-Hua Zhao, Edward R. Prack, Robert J. Wenzel, Brian D. Sawyer, David G. Wontor, Marc Alan Mangrum
  • Patent number: 8048776
    Abstract: A semiconductor device is made by providing a semiconductor wafer having an active surface, forming an under bump metallization layer on the active surface of the semiconductor wafer, forming a first photosensitive layer on the active surface of the semiconductor wafer, exposing a selected portion of the first photosensitive layer over the under bump metallization layer to light, removing a portion of a backside of the semiconductor wafer, opposite to the active surface, prior to developing the exposed portion of the first photosensitive layer, developing the exposed portion of the first photosensitive layer after removing the portion of the backside of the semiconductor wafer, and depositing solder material over the under bump metallization layer to form solder bumps. The remaining portion of the first photosensitive layer is then removed. A second photosensitive layer or metal stencil can be formed over the first photosensitive layer.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: November 1, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Yaojian Lin, Rui Huang
  • Patent number: 7998768
    Abstract: A method for forming a light emitting diode includes: (a) growing epitaxially an epitaxial film over an epitaxial substrate; (b) roughening an upper surface of the epitaxial film; (c) forming a top electrode on the roughened upper surface of the epitaxial film; (d) detachably attaching a temporary substrate over the roughened upper surface of the epitaxial film; (e) roughening the lower surface of the epitaxial film; (f) disposing the roughened lower surface of the epitaxial film on a reflective top surface of an electrically conductive permanent substrate; (g) filling an optical adhesive in a gap between the roughened lower surface of the epitaxial film and the reflective top surface of the permanent substrate; and (h) after the step (g), removing the temporary substrate from the epitaxial film.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: August 16, 2011
    Inventors: Ray-Hua Horng, Dong-Sing Wuu
  • Patent number: 7993972
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C., forming a metal pillar over the wafer in electrical contact with the first interconnect structure, connecting a semiconductor component to the first interconnect structure, and forming encapsulant over the semiconductor component. The encapsulant is etched to expose a portion of the metal pillar. A buffer layer is optionally formed over the encapsulant. The method includes forming a second interconnect structure over the encapsulant in electrical contact with the metal pillar with temperatures below 200° C., and removing a portion of a backside of the wafer opposite the top surface of the wafer.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 9, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao
  • Patent number: 7989267
    Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: August 2, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Junpei Kusukawa, Yoshitaka Takezawa
  • Publication number: 20110114989
    Abstract: A method of manufacturing a light-emitting device includes a hole forming process for forming a through-hole that continues from a front surface to a back surface of a mounting substrate, a pattern forming process for continuously forming a circuit pattern on an inner surface of the through-hole in the mounting substrate, from an end portion of the through-hole on the front surface of the mounting substrate to a mounting portion of a light-emitting element, and on a periphery of the through-hole on the back surface of the mounting substrate, a mounting process for mounting the light-emitting element on the mounting portion, and a hot pressing process in that an inorganic material softened by heating is placed on the surface of the mounting substrate and is advanced into the through-hole while sealing the light-emitting element by pressing and bonding the inorganic material to the surface of the mounting substrate.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 19, 2011
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Yoshinobu Suehiro, Seiji Yamaguchi, Katsunori Arakane, Koji Tasumi
  • Patent number: 7943439
    Abstract: A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: May 17, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 7906363
    Abstract: A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 15, 2011
    Assignee: ZyCube Co., Ltd.
    Inventor: Mitsumasa Koyanagi
  • Patent number: 7902650
    Abstract: A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: March 8, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia Chien Hu, Chao Cheng Liu, Chien Liu, Chih Ming Chung
  • Patent number: 7901955
    Abstract: In constructing a multi-die semiconductor device, a plurality of semiconductor die are provided. Each die is probe tested when it is part of a wafer. Flat contacts are connected to each die when it is part of a wafer. After wafer sawing, each die is tested in a test socket, using the contacts connected thereto. The die are then packaged in stacked relation to form the multi-die semiconductor device.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: March 8, 2011
    Assignee: Spansion LLC
    Inventor: Melissa Grupen-Shemansky
  • Patent number: 7843049
    Abstract: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: November 30, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiko Shimanuki, Yoshihiro Suzuki, Koji Tsuchiya
  • Patent number: 7799611
    Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, in contrast with the conventional fully etched stencil-like lead frames, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: September 21, 2010
    Assignee: Unisem (Mauritius) Holdings Limited
    Inventors: Mary Jean Ramos, Romarico Santos San Antonio, Anang Subagio
  • Patent number: 7790484
    Abstract: A method for manufacturing a laser device includes fixing a laser chip to a holder via a metal having a low melting point by melting the metal at a temperature higher than the melting point, heating the holder to which the laser chip is fixed at a heat treatment temperature that is lower than the melting point and, thereafter, sealing the laser chip by covering the holder to which the laser chip is fixed with a cap. The heating step may be performed in an atmosphere in which ozone is generated or an atmosphere in which oxygen plasma is generated. Furthermore, the holder to which the laser chip is fixed is covered with a cap to make a hermetically sealed package in dry air or an inert gas, and then an ultraviolet ray is irradiated into the package while it is heated.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: September 7, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaya Ishida, Atsushi Ogawa, Daisuke Hanaoka
  • Patent number: 7772026
    Abstract: A micro electro-mechanical system (MEMS) device package and a method of manufacturing the same are provided.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: August 10, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-seok Kim, Yun-kwon Park, Kuang-woo Nam, Seok-chul Yun, In-sang Song
  • Patent number: 7750469
    Abstract: A semiconductor chip and manufacturing method thereof, the semiconductor chip including a plurality of bumps connected to a driving circuit integrated on a semiconductor substrate and an organic insulating layer disposed on the driving circuit. The organic insulating layer extends from the semiconductor substrate less than the plurality of bumps such that a lower edge of the plurality of bumps protrudes further than a lower edge of the organic insulating layer.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Gu Cho, Ho Min Kang
  • Publication number: 20100164097
    Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.
    Type: Application
    Filed: December 8, 2009
    Publication date: July 1, 2010
    Applicant: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 7691671
    Abstract: Methods and systems for attaching a chip to a next level package by directing radiant energy at the chip back side while substantially preventing irradiation of the next level package are described.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventor: Kristopher J. Frutschy
  • Patent number: 7662661
    Abstract: A method of manufacturing a substrate structure includes the steps of: (1) providing a metal substrate having a metal portion; (2) chemically etching a plurality of trenches in the metal substrate; (3) applying a polymer composite material into the trenches to form a substrate having a polymer composite portion abutted to the metal portion; (4) polishing a surface of the substrate to make a height of the polymer composite portion equal to that of the metal portion; (5) forming a covering material on the surface of the substrate; and (6) cutting the substrate via the polymer composite portion for decreasing cutting bur produced on the metal portion. Furthermore, the method is provided for combining the metal substrate and the polymer composite material, thereby to increase cutting precision and strength of the substrate structure.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: February 16, 2010
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Jonnie Chuang, Hui-Yen Huang
  • Patent number: 7659192
    Abstract: Methods of forming a microelectronic device and associated structures are described. Those methods may comprise forming a die-side conductive interconnect on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 9, 2010
    Assignee: Intel Corporation
    Inventors: Andrew Yeohi, Guotao Wang, Sairam Agraharam, Sudarshan Rangaraj
  • Patent number: 7652368
    Abstract: A semiconductor device having a first semiconductor chip with an SDRAM and a second semiconductor chip with a an MPU controlling the SDRAM. The contour size of the semiconductor device is reduced to a smaller size without impairing the testability of the first semiconductor chip. The two semiconductor chips are stacked over the top surface of an interconnect substrate and sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate. Plural second electrodes electrically connected with interconnects, which electrically connect the two chips, are mounted as terminals for testing of the SDRAM. The second electrodes are located more inwardly than the innermost row of the first external electrodes on the bottom surface of the interconnect substrate.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: January 26, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinari Hayashi, Toshikazu Ishikawa, Takayuki Hoshino
  • Patent number: 7635910
    Abstract: A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The semiconductor chip has an active surface with a plurality of chip contact pads on each of which an electrically conductive bump is disposed. The inner portions of the leadfingers protrude into the chip position and are electrically connected to the chip contact pads by electrically conductive bumps.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: December 22, 2009
    Assignee: Infineon Technologies AG
    Inventors: Richard Mangapul Sinaga, Najib Khan Surattee, Mohamad Yazid
  • Patent number: 7572659
    Abstract: A semiconductor sensor includes an adhesive film for suppressing thermal stress transfer to a semiconductor sensor chip. More specifically, the adhesive film includes a first layer and a second layer. An elasticity modulus of the first layer is lower than that of the second layer, and the second layer has a water absorption smaller than that of the first layer. One surface of a semiconductor wafer is in contact with the first layer. Once the semiconductor wafer and the adhesive film are diced into a plurality of sensor chips, the sensor chip with the adhesive film is mounted on a sensor package via the second layer interposed therebetween.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: August 11, 2009
    Assignee: DENSO CORPORATION
    Inventors: Koichi Tsubaki, Yasuo Souki
  • Patent number: 7566584
    Abstract: A method of manufacture of an electronic substrate, having a process of embedding electronic components in a substrate, and a process of ejecting liquid droplets containing a conductive material, to form a wiring pattern connected to the external connection electrodes of the electronic components embedded in the substrate.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: July 28, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Haruki Ito
  • Patent number: 7544529
    Abstract: An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: June 9, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Shou-Lung Chen, Fang-Jun Leu, Shan-Pu Yu
  • Patent number: 7507637
    Abstract: To manufacture a wafer level stack package, first and second wafers having first and second via patterns are prepared. The second wafer is attached to the first wafer such that the front sides of the first and second wafers face each other and the first and second via patterns are connected to each other. The back side of the second wafer is ground and etched such that the lower ends of the second via patterns are exposed and projected. The back side of the first wafer is ground and etched such that the lower ends of the first via patterns are exposed and projected. A chip level stack structure is formed by sawing a wafer level stack structure having the stacked wafers into a chip level. The chip level stack structure is attached to a substrate having electrode terminals.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 24, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min Suk Suh, Sung Min Kim
  • Patent number: 7494846
    Abstract: A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: February 24, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Shun Hsu, Louis Liu, Clinton Chao, Mark Shane Peng
  • Patent number: 7488623
    Abstract: An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side. The chip includes integrated circuit devices formed on the active circuit side. The active circuit side of the chip is on the first package side. The die pad has at least one runner member extending therefrom, which may be bent toward the first package side. The active circuit side of the chip is attached to the die pad. The die pad is on the first package side relative to the chip. The package mold compound is formed over the die pad, at least part of the chip, and at least part of the runner member(s). At least part of the substrate side of the chip and/or at least part of the runner member(s) may not be covered by the package mold compound.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: February 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Steven A Kummerl, Anthony L Coyle, Bernhard Lange
  • Patent number: 7479412
    Abstract: An adhesive film for semiconductor, which comprises at least one resin layer, and, after bonded to a lead frame, has at 25° C. a 90°-peel strength of at least 5 N/m between the resin layer and the lead frame, and, after a lead frame is bonded to the adhesive film for semiconductor and sealed with a sealing material, has at least at one point of temperatures ranging from 0 to 250° C. a 90°-peel strength of at most 1000 N/m between the resin layer and each of the lead frame and the sealing material; a lead frame and a semiconductor device using the adhesive film for semiconductor; and a method of producing a semiconductor device.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: January 20, 2009
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Toshiyasu Kawai, Hidekazu Matsuura
  • Publication number: 20080296690
    Abstract: Provided herein is an exemplary embodiment of a semiconductor chip for directly connecting to a carrier. The chip includes a metal layer applied to a top surface of the chip; a passivation layer applied over the metal layer such that portions of the passivation layer is selectively removed to create one or more openings (“bond pads”) exposing portions of the metal layer and one or more solderable metal contact regions formed on each of the one or more openings. The solderable metal contact regions electrically connect to the carrier when the chip is positioned face down on the carrier, supplied with a thin layer of solder and heated.
    Type: Application
    Filed: December 11, 2004
    Publication date: December 4, 2008
    Applicant: Great Wall Semiconductor Corporation
    Inventors: Samuel S. Anderson, Zheng Shen, David N. Okada
  • Patent number: 7452750
    Abstract: A method of attaching a capacitor (112) to a substrate (100) includes applying a flux (108) to respective capacitor pads (104, 106) on the substrate (100). The capacitor (112) is placed on the fluxed capacitor pads (104, 106) and a reflow operation is performed on the capacitor (112) and the substrate (100) such that intermetallic interconnects (128) are formed between the capacitor (112) and the substrate (100).
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: November 18, 2008
    Assignee: Freescale Semiconductor, Inc
    Inventors: Wai Yew Lo, Chee Seng Foong
  • Patent number: 7449367
    Abstract: An adhesive film for semiconductor use of the present invention is used in a method in which, after the adhesive film for semiconductor use is laminated to one side of a metal sheet, the metal sheet is processed to give a wiring circuit, a semiconductor die is mounted and molded, and the adhesive film is then peeled off. The adhesive film includes a resin layer A formed on one side or both sides of a support film, the 90 degree peel strength between the resin layer A and the metal sheet prior to the processing of the metal sheet laminated with the adhesive film for semiconductor use to give the wiring circuit is 20 N/m or greater at 25° C., and the 90 degree peel strengths, after molding with a molding compound the wiring circuit laminated with the adhesive film for semiconductor use, between the resin layer A and the wiring circuit and between the resin layer A and the molding compound are both 1000 N/m or less at at least one point in the temperature range of 0° C. to 250° C.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: November 11, 2008
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Hidekazu Matsuura, Toshiyasu Kawai
  • Publication number: 20080258274
    Abstract: A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The semiconductor chip has an active surface with a plurality of chip contact pads on each of which an electrically conductive bump is disposed. The inner portions of the leadfingers protrude into the chip position and are electrically connected to the chip contact pads by electrically conductive bumps.
    Type: Application
    Filed: January 20, 2005
    Publication date: October 23, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Richard Mangapul Sinaga, Najib Khan Surattee, Mohamad Yazid
  • Publication number: 20080220565
    Abstract: A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 11, 2008
    Inventors: Chao-Shun Hsu, Louis Liu, Clinton Chao, Mark Shane Peng
  • Publication number: 20080153204
    Abstract: An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein and which extend from an active surface to a back surface of the semiconductor substrate. The redistribution lines are patterned on the back surface of the semiconductor substrate, extending from the conductive material in the vias to predetermined locations on the back surface of the semiconductor substrate that correspond with an interconnect pattern of another substrate for interconnection thereto.
    Type: Application
    Filed: January 2, 2008
    Publication date: June 26, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Timothy L. Jackson, Tim E. Murphy
  • Publication number: 20080116544
    Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 22, 2008
    Applicant: Tessera, Inc.
    Inventors: Andrey Grinman, David Ovrutsky, Charles Rosenstein, Vage Oganesian
  • Patent number: 7374973
    Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: May 20, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Junpei Kusukawa, Yoshitaka Takezawa
  • Patent number: 7361987
    Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive or electrically non-conductive.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: April 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George R. Leal, Jie-Hua Zhao, Edward R. Prack, Robert J. Wenzel, Brian D. Sawyer, David G. Wontor, Marc Alan Mangrum
  • Patent number: 7259032
    Abstract: A method for manufacturing an electronic device includes the steps of forming a first resist pattern on a primary surface of a SAW element, the first resist pattern having openings at positions corresponding to those at which bumps and a sealing frame are to be formed, sequentially forming metals over the first resist pattern, the metals being formed into adhesion layers, barrier metal layers, and solder layers, removing the first resist pattern on the SAW element such that the bumps and the sealing frame are simultaneously formed. When the bumps and the sealing frame of the SAW element are bonded to bond electrodes of the bond substrate, the solder layers are melted and alloyed by heating.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: August 21, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Murata, Takashi Iwamoto, Hiroki Horiguchi, Ryuichi Kubo, Hidetoshi Fujii, Naoko Aizawa
  • Patent number: 7186588
    Abstract: A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder connectors are applied. The lead-frame is then singulated to produce a plurality of lead-frame based micro-array packages. The process thus allows lead-frame based manufacturing methods to be employed in the production of BGA-type packages, allowing such packages to be produced faster and more efficiently.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: March 6, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Jaime A. Bayan, Santhiran S/O Nadarajah, Chan Chee Ling, Ashok S. Prabhu, Hasfiza Ramley, Chan Peng Yeen