Involving Soldering Or Alloying Process, E.g., Soldering Wires (epo) Patents (Class 257/E21.509)
  • Patent number: 10327334
    Abstract: A layout structure of flexible circuit board includes a flexible substrate and leads formed on a surface of the flexible substrate. Each of the leads has a bump connection end and a curved part. The bump connection end of each of the leads is located on a chip disposition area of the surface and electrically connected to a chip. The curved part has a first connection point and a second connection point, and the length of the curved part is longer than a straight-line distance between the first and second connection points.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: June 18, 2019
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventor: Chin-Tang Hsieh
  • Patent number: 10064292
    Abstract: A PCB has multiple stacked layers laminated together, the laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure having a low adhesion to an underlying conductive layer, such as an LPI mixture. The LPI mixture defines cavity dimensions and enables the use of regular flow prepreg in the laminated stack.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: August 28, 2018
    Assignee: Multek Technologies Limited
    Inventor: Kwan Pen
  • Patent number: 9865526
    Abstract: A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: January 9, 2018
    Assignee: XINTEC INC.
    Inventor: Yu-Lung Huang
  • Patent number: 9784786
    Abstract: A simultaneous electrical testing device for TSV interconnection elements passing through a substrate and including one end connected to an integrated testing circuit and another end to a removable connection mechanism assembled to the substrate through an anisotropic conductive glue.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: October 10, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Haykel Ben Jamaa
  • Patent number: 9773713
    Abstract: To provide an electronic component in which the bonding position and bonding strength of a lead terminal can be maintained even if re-heated, a crystal oscillator as an electronic component includes: a first substrate having a connection terminal; and a lead terminal having a connection pad connected to the connection terminal of the first substrate via an electrically conductive bonding member. The electrically conductive bonding member has a part overlapping with the connection terminal and the connection pad, and a part arranged on the outside of the connection pad, as viewed in a plan view. The connection pad is provided with a first area overlapping with the connection terminal and a second area extending from the first area. The second area is connected to the first substrate via an insulative bonding member.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: September 26, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Manabu Kondo
  • Patent number: 9728497
    Abstract: A substrate structure may include a base substrate, a plurality of unit substrate regions arranged on the base substrate in one or more rows and one or more columns and spaced apart from one another, and dummy substrate regions between the unit substrate regions. In a row direction or a column direction, a first pitch between central points of two adjacent unit substrate regions among the unit substrate regions and a second pitch between central points of two adjacent second unit substrate regions among the unit substrate regions are different from each other.
    Type: Grant
    Filed: June 12, 2016
    Date of Patent: August 8, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yu-duk Kim, Kyong-soon Cho, Shle-ge Lee, Da-hee Park
  • Patent number: 9601403
    Abstract: An electronic package is provided, which includes: a first circuit structure; at least first electronic element disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; a first encapsulant encapsulating the first electronic element and the first conductive element; and a second circuit structure formed on the first encapsulant and electrically connected to the first conductive element. By directly disposing the electronic element having high I/O functionality on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package. The invention further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: March 21, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Guang-Hwa Ma, Shih-Ching Chen, Chang-Lun Lu
  • Patent number: 9603247
    Abstract: This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Sairam Agraharam, Amruthavalli Pallavi Alur, Ram Viswanath, Wei-Lun Kane Jen
  • Patent number: 9329147
    Abstract: An apparatus for providing security for an integrated circuit (IC) chip is disclosed. The apparatus may include the IC chip, attached to a surface of a printed circuit board (PCB). The PCB may include a first, electrically insulative, conformal coating layer attached to the PCB surface and to exposed IC chip surfaces. The PCB may also include a Wheatstone bridge circuit to indicate changes to a second, X-ray opaque, optically opaque and electrically resistive, conformal coating layer. The circuit may include four resistors, formed from second conformal coating layer regions, four sets of electrically conductive pads on the PCB, each set electrically connected to a resistor of the four resistors. The circuit may also include a voltage source, connected to two conductive pads and a monitoring device, connected to another two conductive pads and configured to detect a change of resistance of the Wheatstone bridge.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 3, 2016
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Doyle, Joseph Kuczynski, Kevin A. Splittstoesser, Timothy J. Tofil
  • Patent number: 9196567
    Abstract: A pad structure including a plurality of staircase structures is provided. The staircase structures are disposed on the substrate. Each of the staircase structures includes a plurality of conductor layers and a plurality of dielectric layers that are alternately stacked. Two adjacent staircase structures are connected with each other by sharing the conductor layers and the dielectric layers and are arranged in parallel along a first direction. One of the two adjacent staircase structures includes at least one staircase portion that gradually decreases in height along a second direction, and the other of the two adjacent staircase structures includes at least one staircase portion that gradually decreases in height along a direction opposite to the second direction.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 24, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Yao-Fu Chan
  • Patent number: 8987922
    Abstract: A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Wen-Hsiung Lu, Hung-Jen Lin
  • Patent number: 8987879
    Abstract: A semiconductor device includes a leadframe with a die pad and a first lead, a semiconductor chip with a first electrode, and a contact clip with a first contact area and a second contact area. The semiconductor chip is placed over the die pad. The first contact area is placed over the first lead and the second contact area is placed over the first electrode of the semiconductor chip. A plurality of protrusions extends from each of the first and second contact areas and each of the protrusions has a height of at least 5 ?m.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: March 24, 2015
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 8975117
    Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Fong Lim, Abdul Rahman Mohamed, Chooi Mei Chong, Ida Fischbach, Xaver Schloegel, Juergen Schredl, Josef Hoeglauer
  • Patent number: 8975734
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8955212
    Abstract: A micro-electro-mechanical microphone and manufacturing method thereof are provided. The micro-electro-mechanical microphone includes a diaphragm, which is formed on a surface of one side of a semiconductor substrate, exposed to the outside surroundings, and can vibrate freely under the pressure generated by sound waves; an electrode plate with air holes, which is under the diaphragm; an isolation structure for fixing the diaphragm and the electrode plate; an air gap cavity between the diaphragm and the electrode plate, and a back cavity under the electrode plate and in the semiconductor substrate; and a second cavity formed on the surface of the same side of the semiconductor substrate and in an open manner The air gap cavity is connected with the back cavity through the air holes of the electrode plate The back cavity is connected with the second cavity through an air groove formed in the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 17, 2015
    Assignee: Lexvu Opto Microelectronics Technology (Shanghai) Ltd
    Inventors: Jianhong Mao, Deming Tang
  • Patent number: 8951847
    Abstract: Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 10, 2015
    Assignee: Intersil Americas LLC
    Inventors: Nikhil Vishwanath Kelkar, Kai Liu
  • Patent number: 8951445
    Abstract: A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Javier V. Goicochea, Cyrill Kuemin, Walter H. Riess, Heiko Wolf
  • Patent number: 8927341
    Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 6, 2015
    Assignee: Nichia Corporation
    Inventors: Masafumi Kuramoto, Satoru Ogawa, Miki Niwa
  • Patent number: 8912659
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyeong Seok Choi
  • Patent number: 8906798
    Abstract: A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Wang, Tzu-Wei Chiu, Shin-Puu Jeng
  • Patent number: 8907481
    Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Patent number: 8901949
    Abstract: There is provided a probe card comprising a plurality of probe tips, each being ball-shaped or pillar-shaped and having a top end in contact with each of target chip pads to be tested; a first space converting unit; a second space converting unit; a frame configured to support the second space converting unit; an interposer unit; and a circuit board.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: December 2, 2014
    Assignee: Gigalane, Co., Ltd.
    Inventors: Duk Kyu Kwon, Kyu Han Lee, Yong Goo Lee
  • Patent number: 8884343
    Abstract: A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Bernhard Lange, Juergen Neuhaeusler
  • Patent number: 8884407
    Abstract: A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Michael Sternad, Rainer Pelzer
  • Patent number: 8846519
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: September 30, 2014
    Assignee: Advanpack Solutions Pte Ltd.
    Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong
  • Patent number: 8829675
    Abstract: A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Holm Geisler, Dirk Breuer
  • Patent number: 8829691
    Abstract: A light-emitting device package includes: a package body on which a mount portion and a terminal portion are disposed; a light-emitting device chip that is mounted on the mount portion; and a bonding wire that electrically connects an electrode of the light-emitting device chip and the terminal portion. The bonding wire includes a rising portion that rises from the light-emitting device chip to a loop peak, and an extended portion that connects the loop peak and the terminal portion. A first kink portion, which is bent in a direction intersecting a direction in which the rising portion rises, is disposed on the rising portion.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yun Lim, Kook-jin Oh, Joon-gil Lee
  • Patent number: 8809181
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Patent number: 8803305
    Abstract: A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: August 12, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Ratibor Radojcic, Arvind Chandrasekaran, Ryan Lane
  • Patent number: 8796833
    Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Jing-Cheng Lin
  • Patent number: 8778740
    Abstract: To avoid shorts between adjacent die pads in mounting a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package. A process for fabricating the package includes a partial etch that defines the bottom surface of the embedded die pad and may include a through-etch that leaves one or more of the contacts or leads integrally connected to the embedded die pad.
    Type: Grant
    Filed: May 19, 2013
    Date of Patent: July 15, 2014
    Assignees: Advanced Analogic Technologies Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Keng Hung Lin
  • Patent number: 8742571
    Abstract: A diode arrangement includes a diode and two electrodes. Each electrode is connected to the diode in an electrically conductive manner via a soldered connection on one of two oppositely arranged contact surfaces of the diode. The contact surfaces of the diode are formed substantially by the surfaces of a lower side and an upper side of the diode and are contacted with the contact extensions of the electrodes via the soldered connection. The contact extensions forming counter contact surfaces are substantially congruent with the contact surfaces of the diode.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 3, 2014
    Assignee: Pac Tech—Packaging Technologies GmbH
    Inventors: Elke Zakel, Thorsten Teutsch, Ghassem Azdasht, Siavash Tabrizi
  • Patent number: 8741765
    Abstract: The uniformity of the composition of plated solder bumps from one batch of wafers to another is improved by controlling the rotational speed of the wafers based on the particular solder bump pattern. Embodiments include sequentially horizontal fountain electroplating a pattern of solder bumps, e.g., SnAg solder bumps, on a plurality batches of wafers and controlling the rotational speed of each batch of wafers during electroplating based on a calibration plot of the concentration of a solder bump component, e.g., Ag, as a function of rotational speed for each solder bump pattern, such that the uniformity of the Ag concentration in the patterns of solder bumps is greater than 95%, e.g., greater than 98%. Embodiments further include electroplating in the same plater sequential batches of wafers having both different patterns and different solder bump compositions at the same high throughput.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: June 3, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Christian Schroiff
  • Patent number: 8735274
    Abstract: Electrodes formed in a partial surface area of a semiconductor substrate and distal ends of conductive nanotubes bristled on a surface of a growth substrate, are bombarded with rare gas plasma. The distal ends of the conductive nanotubes bombarded with the rare gas plasma are brought into contact with the electrodes bombarded with the rare gas plasma to fix the conductive nanotubes to the electrodes. The growth substrate is separated from the semiconductor substrate in such a manner that the conductive nanotubes fixed to the electrodes remain on the electrodes formed on the semiconductor substrate.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Taisuke Iwai
  • Patent number: 8735180
    Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: May 27, 2014
    Assignee: Nikon Corporation
    Inventor: Kazuya Okamoto
  • Patent number: 8723318
    Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 13, 2014
    Assignee: Tessera, Inc.
    Inventor: Belgacem Haba
  • Publication number: 20140117554
    Abstract: A package substrate has a die mounted on a first side. One or more inner solder pads are on an inner portion of a second side. A perimeter of the inner portion is aligned with a perimeter of the die. The one or more inner solder pads are the only solder pads on the inner portion. The one or more inner solder pads number no more than five. A plurality of outer solder pads are on an outer portion of the second side. An average of areas of the one or more inner solder pads is at least five times an average of areas of the one or more inner solder pads. The plurality of outer solder ball pads are for receiving solder ball balls. The outer portion is spaced from the perimeter of the inner portion. The outer portion and the inner portion are coplanar.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Inventors: Trent S. Uehling, Brett P. Wilkerson
  • Patent number: 8710666
    Abstract: A semiconductor device which can prevent a deterioration in the electrical properties by preventing sputters generated by laser welding from adhering to a circuit pattern or a semiconductor chip and a method for fabricating such a semiconductor device are provided. A connection conductor is bonded to a copper foil formed over a ceramic by a solder and resin is injected to a level lower than a top of the connection conductor. Laser welding is then performed. After that, resin is injected. This prevents sputters generated by the laser welding from adhering to a circuit pattern or a semiconductor chip. As a result, a deterioration in the electrical properties can be prevented.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: April 29, 2014
    Assignees: Aisin AW Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Junji Tsuruoka, Kazuo Aoki, Masaki Ono, Katsuhiko Yoshihara
  • Patent number: 8709866
    Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Setho Sing Fee, Lim Thiam Chye, Tongbi Jiang
  • Patent number: 8698291
    Abstract: A packaged leadless semiconductor device (20) includes a heat sink flange (24) to which semiconductor dies (26) are coupled using a high temperature die attach process. The semiconductor device (20) further includes a frame structure (28) pre-formed with bent terminal pads (44). The frame structure (28) is combined with the flange (24) so that a lower surface (36) of the flange (24) and a lower section (54) of each terminal pad (44) are in coplanar alignment, and so that an upper section (52) of each terminal pad (44) overlies the flange (24). Interconnects (30) interconnect the die (26) with the upper section (52) of the terminal pad (44). An encapsulant (32) encases the frame structure (28), flange (24), die (26), and interconnects (30) with the lower section (54) of each terminal pad (44) and the lower surface (36) of the flange (24) remaining exposed from the encapsulant (32).
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: April 15, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Audel A. Sanchez, Fernando A. Santos, Lakshminarayan Viswanathan
  • Publication number: 20140097524
    Abstract: An approach for a coplanar waveguide structure in stacked multi-chip systems is provided. A method of manufacturing a semiconductor structure includes forming a first coplanar waveguide in a first chip. The method also includes forming a second coplanar waveguide in a second chip. The method further includes directly connecting the first coplanar waveguide to the second coplanar waveguide using a plurality of chip-to-chip connections.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy H. DAUBENSPECK, Hanyi DING, Wolfgang SAUTER, Guoan WANG, Wayne H. WOODS, JR.
  • Patent number: 8679898
    Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: March 25, 2014
    Assignee: Nichia Corporation
    Inventors: Masafumi Kuramoto, Satoru Ogawa, Miki Niwa
  • Patent number: 8679591
    Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu
  • Patent number: 8673684
    Abstract: A disclosed semiconductor device includes a wiring board, a semiconductor element mounted on a principal surface of the wiring board with flip chip mounting, a first conductive pattern formed on the principal surface along at least an edge portion of the semiconductor element, a second conductive pattern formed on the principal surface along the first conductive pattern and away from the first conductive pattern, a passive element bridging between the first conductive pattern and the second conductive pattern on the principal surface of the wiring board, and a resin layer filling a space between the wiring board and the semiconductor chip, wherein the resin layer extends between the semiconductor element and the first conductive pattern on the principal surface of the wiring board.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takumi Ihara
  • Publication number: 20140054020
    Abstract: A method for fabricating a heat sink may include: providing a carbon fiber fabric having carbon fibers and openings, the openings leading from a first side to a second side of the fabric; and electroplating the fabric with metal, wherein metal is deposited with a higher rate at the first side than at the second side of the fabric. Another method for fabricating a heat sink may include: providing a carbon metal composite having metal-coated carbon fibers and openings, the openings leading from a first side to a second side of the carbon metal composite; disposing the composite over a semiconductor element such that the first side of the composite faces the semiconductor element; and bonding the composite to the semiconductor element by means of an electroplating process, wherein metal electrolyte is supplied to an interface between the carbon metal composite and the semiconductor element via the openings.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 27, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Friedrich Kroener
  • Patent number: 8659113
    Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 25, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 8653668
    Abstract: A bonding structure and a copper bonding wire for semiconductor device include a ball-bonded portion formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: February 18, 2014
    Assignees: Nippon Steel & Sumikin Materials Co., Ltd., Nippon Micrometal Corporation
    Inventors: Tomohiro Uno, Takashi Yamada, Atsuo Ikeda
  • Publication number: 20140042630
    Abstract: Aspects of the present invention relate to a controlled collapse chip connection (C4) structures. Various embodiments include a method of forming a controlled collapse chip connection (C4) structure. The method can include: providing a precursor structure including: a substrate, a dielectric over the substrate, the dielectric including a plurality of trenches exposing a portion of the substrate, and a metal layer over the dielectric and the portion of the substrate in each of the plurality of trenches, forming a resist layer over the metal layer, forming a rigid liner over a surface of the resist layer and the metal layer, and forming solder over the rigid liner between portions of the resist layer.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen P. Ayotte, Timothy H. Daubenspeck, David J. Hill, Glen E. Richard, Timothy M. Sullivan
  • Patent number: 8637394
    Abstract: An integrated circuit package system includes: forming a flex bump over an integrated circuit device structure, the flex bump having both a base portion and an offset portion over the base portion; forming a first ball bond of a first internal interconnect over the offset portion; and encapsulating the integrated circuit device structure, the flex bump, and the first internal interconnect.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: January 28, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jairus Legaspi Pisigan, Henry Descalzo Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8629567
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua