Involving Application Of Pressure, E.g., Thermo-compression Bonding (epo) Patents (Class 257/E21.519)
  • Patent number: 10115688
    Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 30, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Kamil Karlovsky, Evelyn Napetschnig, Michael Ehmann, Mark Harrison, Anton Pugatschow
  • Patent number: 9881884
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess. The second surface is opposite to the first surface. The recess passes through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer over the second surface. The semiconductor device structure includes a first bonding pad in the recess and extending to the first wiring layer so as to be electrically connected to the first wiring layer. The semiconductor device structure includes a nickel layer over the first bonding pad. The semiconductor device structure includes a gold layer over the nickel layer.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsien Yang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Sin-Yao Huang
  • Patent number: 8921157
    Abstract: Solder bumps are formed on a plurality of electrode parts of a printed substrate and a semiconductor chip is loaded on the printed substrate via the plurality of solder bumps. In this case, a thermoplastic film is prepared as an underfill that covers a surface of the printed substrate on which the solder bumps are formed. In the film, parts corresponding to the solder bumps are removed and a peripheral edge of a part on which the semiconductor chip will be loaded has a protruded form. After the printed substrate has been covered with the film, the film is bonded onto the board and the semiconductor chip is loaded on the printed substrate and carried into a reflow furnace. In the reflow furnace, heat and pressure are applied to fuse the solder bumps.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 30, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Noriaki Mukai, Masaru Mitsumoto, Makoto Homma
  • Patent number: 8912088
    Abstract: The present invention provides a transfer substrate for transferring a metal wiring material to a transfer-receiving object, the transfer substrate comprising a substrate, at least one metal wiring material formed on the substrate and an underlying metal film formed between the substrate and the metal wiring material, wherein the metal wiring material is a molded article prepared by sintering, e.g., gold powder having a purity of 99.9% by weight or more and an average particle size of 0.01 ?m to 1.0 ?m and the underlying metal film is composed of a metal such as gold or an alloy. The transfer substrate is capable of transferring a metal wiring material to the transfer-receiving object even at a temperature for heating the transfer-receiving object of 80 to 300° C.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 16, 2014
    Assignee: Tanaka Kikinzoku Kogyo K.K.
    Inventors: Toshinori Ogashiwa, Masaaki Kurita, Takashi Nishimori, Yukio Kanehira
  • Patent number: 8907485
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8796826
    Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Xueren Zhang, Kim-Yong Goh, Wingshenq Wong
  • Patent number: 8786084
    Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Jean-François Sauty
  • Publication number: 20140061949
    Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: Ziptronix, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR.
  • Publication number: 20140054781
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8633060
    Abstract: A purpose of the application is to provide a semiconductor device production method capable of reducing complexity of production operations and keeping production costs low, and enhancing reliability, and a semiconductor device. One aspect of the invention provides a method of producing a semiconductor device, the method including a first bonding step of bonding a first electrode plate and a semiconductor device portion, and a second bonding step of bonding the semiconductor device portion and a second electrode plate. The method includes a sealing step of forming a sealed composite body by covering target surfaces of a composite body formed by the first bonding step with resin, the target surfaces being surfaces other than a second surface of the first electrode plate and the second surface of the semiconductor device portion. The second bonding step is performed after the sealing step.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: January 21, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hirotaka Ohno
  • Patent number: 8604627
    Abstract: The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: December 10, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Hideki Hiromoto, Sadamasa Fujii, Tsunemori Yamaguchi
  • Patent number: 8575005
    Abstract: A method of manufacturing an electronic device on a plastic substrate includes: providing a carrier as a rigid support for the electronic device; providing a metallic layer on the carrier; forming the plastic substrate on the metallic layer, the metallic layer guaranteeing a temporary bonding of the plastic substrate to the carrier; forming the electronic device on the plastic substrate; and releasing the carrier from the plastic substrate. Releasing the carrier comprises immersing the electronic device bonded to the carrier in a oxygenated water solution that breaks the bonds between the plastic substrate and the metallic layer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Corrado Accardi, Stella Loverso, Sebastiano Ravesi, Noemi Graziana Sparta
  • Patent number: 8569850
    Abstract: A sensor for acoustic applications such as a silicone microphone is provided containing a backplate provided with apertures and a flexible diaphragm formed from a silicon on insulator (SOI) wafer which includes a layer of heavily doped silicon, a layer of silicon and an intermediate oxide layer that is connected to, and insulated from the backplate. The arrangement of the diaphragm in relation to the rest of the sensor and the sensor location, being mounted over the aperture in a PCB, reduces the acoustic signal pathway which allows the sensor to be both thinner and more importantly, enables there to be a greater back volume.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: October 29, 2013
    Assignee: Sensfab Pte Ltd
    Inventors: Kitt-Wai Kok, Kok Meng Ong, Kathirgamasundaram Sooriakumar, Bryan Keith Patmon
  • Patent number: 8497156
    Abstract: A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Susumu Moriya
  • Patent number: 8419888
    Abstract: An electronic component mounting apparatus is capable of significantly reducing a warpage amount of an electronic component warped in a case of thermocompression bonding using a non-conductive adhesive agent having a low minimum melt viscosity and having no conductive particle where a thin electronic component having a thickness smaller than or equal to 200 ?m is mounted on a wiring board. In the mounting apparatus, a non-conductive adhesive film having the minimum melt viscosity lower than or equal to 1.0×103 Pa·s is placed on a wiring board placed on a base, and an IC chip having a thickness smaller than or equal to 200 ?m is placed on the non-conductive adhesive film. In the mounting apparatus, the IC chip is pressurized by a thermocompression bonding head having a compression bonding portion made of elastomer having a rubber hardness lower than or equal to 60, so that the IC chip is bonded onto the wiring board by thermocompression.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: April 16, 2013
    Assignee: Dexerials Corporation
    Inventor: Kazunori Hamazaki
  • Patent number: 8299630
    Abstract: A microstructure has at least one bonding substrate and a reactive multilayer system. The reactive multilayer system has at least one surface layer of the bonding substrate with vertically oriented nanostructures spaced apart from one another. Regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures. A method for producing at least one bonding substrate and a reactive multilayer system, includes, for forming the reactive multilayer system, at least one surface layer of the bonding substrate is patterned or deposited in patterned fashion with the formation of vertically oriented nanostructures spaced apart from one another, and regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: October 30, 2012
    Assignees: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V., Technische Universitaet Chemnitz
    Inventors: Joerg Braeuer, Thomas Gessner, Lutz Hofmann, Joerg Froemel, Maik Wiemer, Holger Letsch, Mario Baum
  • Patent number: 8278143
    Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting at least one of the first metallic bond part and the second metallic bond part.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoichiro Kurita
  • Patent number: 8236666
    Abstract: Provided is a semiconductor device including: a base plate; a thermally conductive resin layer formed on an upper surface of the base plate; an integrated layer which is formed on an upper surface of the thermally conductive resin layer, and includes an electrode and an insulating resin layer covering all side surfaces of the electrode; and a semiconductor element formed on an upper surface of the electrode, in which the integrated layer is thermocompression bonded to the base plate through the thermally conductive resin layer. This semiconductor device excels in insulating properties and reliability.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: August 7, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiki Hiramatsu, Kei Yamamoto, Atsuko Fujino, Takashi Nishimura, Kenji Mimura, Hideki Takigawa, Hiroki Shiota, Nobutake Taniguchi, Hiroshi Yoshida
  • Patent number: 8193035
    Abstract: A semiconductor device is made by providing a semiconductor die having bond pads formed on a surface of the semiconductor die, forming a UBM over the bond pads of the semiconductor die, forming a fusible layer over the UBM, providing a substrate having bond pads formed on a surface of the substrate, and forming a plurality of stud bumps containing non-fusible material over the bond pads on the substrate. Each stud bump includes a wire having a first end attached to the bond pad of the substrate and second end of uniform height. The method further includes electrically connecting the second end of the wire for each stud bump to the bond pads of the semiconductor die by reflowing the fusible layer or applying thermal compression bonding, depositing an underfill material between the semiconductor die and substrate, and depositing an encapsulant over the semiconductor die and substrate.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: June 5, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 8174101
    Abstract: Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a microelectronic device that includes a microfeature workpiece having a side and an aperture in the side. The device can further include a workpiece contact having a surface. At least a portion of the surface of the workpiece contact can be accessible through the aperture and through a passageway extending between the aperture and the surface. Other aspects of the invention are directed toward a microelectronic support device that includes a support member having a side carrying a support contact that can be connectable to a workpiece contact of a microfeature workpiece. The device can further include recessed support contact means carried by the support member. The recessed support contact means can be connectable to a second workpiece contact of the microfeature workpiece.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, David Yih Ming Chai, Hong Wan Ng
  • Patent number: 8163598
    Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 24, 2012
    Assignee: Intel Corporation
    Inventors: George Kostiew, Raj Bahadur, James Mellody, George Vakanas, Leonel Arana
  • Patent number: 8143704
    Abstract: An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: March 27, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey A West
  • Patent number: 8105933
    Abstract: In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum (1002), the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum (1004); forming alloys of gold and the diffusion retardant material in regions containing the material (1006) and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material (1008); and forming a continuous electrically conducting path between the aluminum and the gold (1010). In some embodiments, a structure useful in a gold-aluminum interconnect is provided.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: January 31, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kevin J. Hess, Chu-Chung Lee
  • Publication number: 20120009736
    Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 12, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Seung Taek YANG, Min Suk SUH, Seung Hyun LEE, Jong Hoon KIM
  • Patent number: 8067823
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: November 29, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Cheonhee Lee
  • Patent number: 8063401
    Abstract: A probe electrode structure on a substrate is described, comprising a first probe electrode and a neighboring second probe electrode on a layer sequence that generally includes, in a direction from the substrate to the probe electrodes, an electrically conductive bottom layer, an electrically insulating center layer and a electrically conductive top layer. The probe-electrode structure of the invention provides a means to detect an undercutting of the first probe electrode in an etching step that aims at removing the top layer from regions outside the first probe electrode. An undercutting that exceeds an admissible distance from the first edge of the first electrode will remove the first top-layer probe section in the first probe opening, which causes a detectable change of the electrical resistance between the first and second probe electrodes.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: November 22, 2011
    Assignee: NXP B.V.
    Inventors: Rene P. Zingg, Sudha Gopalan Zingg, Herman E. Doornveld, Theodorus H. G. Martens
  • Patent number: 8034659
    Abstract: To provide a method of manufacturing semiconductor devices, the method being capable of efficiently obtaining a singulated semiconductor chip upon which an adhesive is adhered and also capable of excellently bonding a semiconductor chip to a wiring substrate, and provide an adhesive film. A layered product 60 in which a dicing tape 9, an adhesive layer 3, and a semiconductor wafer 6 are stacked in this order so that a circuit surface 6a of the semiconductor wafer 6 may face the dicing tape 9 side. A cutting position is recognized by recognizing a circuit pattern P in the circuit surface 6a from a rear surface 6b of the semiconductor wafer 6. At least the semiconductor wafer 6 and the adhesive layer 3 are cut in the thickness direction of the layered product 60. The dicing tape 9 is cured to peel off the dicing tape 9 and the adhesive layer 3. A projection electrode 4 of a semiconductor chip 26 is aligned with a wiring 12 of a wiring substrate 40.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: October 11, 2011
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Akira Nagai, Masaaki Yasuda, Keiichi Hatakeyama, Tetsuya Enomoto
  • Publication number: 20110233794
    Abstract: A method of manufacturing a semiconductor device at a good manufacturing efficiency and at a low cost while suppressing the occurrence of voids in the sealing region, the method including the steps of (A) bonding external connection terminals of a semiconductor chip to wirings of a film substrate by hot press bonding, and (B) resin sealing the periphery of the bonded portion of the semiconductor chip and the film substrate, in which the bonding step (A) is performed in a state of adsorbing a portion of the film substrate facing the semiconductor chip from the side opposite the bonding side of the semiconductor chip, and the resin sealing step (B) is performed in a state where the temperature of the semiconductor chip and the film substrate is lowered press is no thermal expansion of the film substrate.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: YASUAKI IWATA
  • Publication number: 20110227223
    Abstract: Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 22, 2011
    Inventors: Albert Wu, Scott Wu
  • Patent number: 8017446
    Abstract: Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is electrically insulating and conducts well thermally, having the following steps: manufacturing a one-piece lead frame; populating the lead frame with semiconductor devices, possible passive components, and bonding corresponding connections, inserting the thus populated lead frame into a compression mould so that accessibility of part areas of the lead frame is ensured, pressing a thermosetting compression moulding compound into the mould while enclosing the populated lead frame, coating the underside of the thus populated lead frame by thermal spraying in at least the electrically conducting areas and overlapping also the predominant areas of the spaces, filled with mold compound.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 13, 2011
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Mathias Kock, Teoman Senyildiz
  • Patent number: 8008164
    Abstract: A wafer bonding method includes providing a primary wafer and a plurality of secondary wafers, wherein the primary wafer is larger than the secondary wafers. An intermediate material layer is formed on at least one of a bonding surface of the primary wafer and bonding surfaces of the secondary wafers. The intermediate material layer has a thermal expansion coefficient greater than the thermal expansion coefficient of the primary wafer and the thermal expansion coefficient of the secondary wafers. The secondary wafers are bonded onto the primary wafer.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Joon Park
  • Publication number: 20110207262
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps of: forming a substrate having a package array, wherein the package array has a plurality of contact pads and a protection layer, and the plurality of contact pads are exposed to the outer side of the protection layer; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate, wherein each of the chips has an active surface, a plurality of chip pads and a plurality of composite bumps, the chip pads are formed on the active surface, and the composite bumps are formed on the chip pads so that the composite bumps electrically connect to each of the contact pads; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an encapsulant preformed
    Type: Application
    Filed: October 6, 2010
    Publication date: August 25, 2011
    Applicant: Chipmos Technologies Inc.
    Inventor: Geng-Shin Shen
  • Patent number: 8003441
    Abstract: A manufacturing method of a semiconductor device according to the present invention comprises: laminating a surface protective sheet to a circuit surface side of a wafer formed with grooves which divide each circuit wherein an adhesive film is adhered on the circuit surface of the wafer; reducing the thickness of the wafer and finally dividing the wafer into individual chips by grinding a back face of the wafer; picking up individual chips together with the adhesive film; die-bonding said individual chip to predetermined position of a chip mounting substrate via said adhesive film; fixing the chip to the chip mounting substrate by heating the die-bonded chip having the adhesive film; and applying a static pressure larger than an ambient pressure by 0.05 MPa or more to a stacked body including the adhesive film one or more times, at any point between adhering the wafer to the adhesive film and fixing the chip to the chip mounting substrate.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: August 23, 2011
    Assignee: LINTEC Corporation
    Inventors: Jun Maeda, Keiko Tanaka, Osamu Yamazaki
  • Patent number: 7977158
    Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yoichiro Kurita
  • Publication number: 20110151622
    Abstract: The present invention provides a method of manufacturing a semiconductor device in which a plurality of wires are connected to the same electrode on a semiconductor chip, the method making it possible to inhibit an increase in electrode area. First, ball bonding is performed to compressively bond a first ball to an electrode on a semiconductor chip to form a first connection portion. Wedge bonding is then performed on an inner lead. Subsequently, ball bonding is performed to compress a second ball against the first connection portion from immediately above to bond the second ball to form a second connection portion. Wedge bonding is then performed on the inner lead.
    Type: Application
    Filed: January 5, 2011
    Publication date: June 23, 2011
    Applicant: Panasonic Corporation
    Inventor: Akira Oga
  • Patent number: 7964493
    Abstract: A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal connecting terminal, and the metal layer is pressed to cause the metal layer in a corresponding portion to a wiring pattern to come in contact with the internal connecting terminal, and to then bond the metal layer in a portion provided in contact with the internal connecting terminal to the internal connecting terminal in a portion provided in contact with the metal layer.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: June 21, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Patent number: 7947602
    Abstract: The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern. The pitch of the conductive pattern corresponds to the pitch of electrodes on a semiconductor chip.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: May 24, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Chizuko Ito, Mutsumi Masumoto
  • Patent number: 7932590
    Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: April 26, 2011
    Assignee: Atmel Corporation
    Inventor: Ken M. Lam
  • Publication number: 20110079916
    Abstract: An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces.
    Type: Application
    Filed: October 2, 2009
    Publication date: April 7, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: JEFFREY A. WEST
  • Publication number: 20110059578
    Abstract: A method of making a semiconductor chip assembly includes providing a thermal post, a signal post and a base, mounting an adhesive on the base including inserting the thermal post into a first opening in the adhesive and the signal post into a second opening in the adhesive, mounting a conductive layer on the adhesive including aligning the thermal post with a first aperture in the conductive layer and the signal post with a second aperture in the conductive layer, then flowing the adhesive upward between the thermal post and the conductive layer and between the signal post and the conductive layer, solidifying the adhesive, providing a conductive trace that includes a pad, a terminal and the signal post, wherein the pad includes a selected portion of the conductive layer, mounting a semiconductor device on the thermal post, wherein a heat spreader includes the thermal post and the base and the semiconductor device extends into a cavity in the thermal post, electrically connecting the semiconductor device to
    Type: Application
    Filed: July 12, 2010
    Publication date: March 10, 2011
    Inventors: Charles W.C. Lin, Chia-Chung Wang, Sangwhoo Lim
  • Patent number: 7879690
    Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: February 1, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Emmanuel Augendre, Thomas Ernst, Marek Kostrzewa, Hubert Moriceau
  • Patent number: 7855103
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: December 21, 2010
    Assignee: Intel Corporation
    Inventors: Robert J. Gleixner, Donald Danielson, Patrick M. Paluda, Rajan Naik
  • Patent number: 7846777
    Abstract: A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounted on the substrate to have a space between one or more of the chips and an edge of the substrate, an insulating layer covering the chips, the insulating layer having via holes exposing portions of the at least two chips and a trench between the via holes, the insulating layer having at least two hole patterns within the space, and a metal layer filling the via holes and the trench.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 7, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Sang Chul Kim
  • Patent number: 7791200
    Abstract: At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows a Micro-Electro-Mechanical Systems device or semiconductor to be subjected to temperatures above 385° C. without risking gold diffusion. Removing the risk of gold diffusion allows further elevated temperature processing. Bonding a device substrate to a carrier substrate can be an elevated temperature process.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: September 7, 2010
    Assignee: Honeywell International Inc.
    Inventor: Richard A. Davis
  • Publication number: 20100219522
    Abstract: A first sealing resin seals a side surface of an electronic component and a side surface of a conductive member. A second sealing resin is provided on the first sealing resin, and seals an electrode pad and an electrode pad forming surface of the electronic component and a part of the conductive member. A multilayer wiring structure includes a plurality of stacked insulating layers and a wiring pattern and is provided on a surface of the second sealing resin from which a connecting surface of the electrode pad and a first connecting surface of the conductive member are exposed. The wiring pattern is connected to the connecting surface of the electrode pad and the first connecting surface of the conductive member.
    Type: Application
    Filed: March 1, 2010
    Publication date: September 2, 2010
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventor: Yuji Kunimoto
  • Patent number: 7776715
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: August 17, 2010
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Patent number: 7772032
    Abstract: A manufacturing method for manufacturing an electronic device includes a first electronic component and a second electronic component; and a bond part for the first electronic component joined to another bond part for the second electronic component. In a first process of this manufacturing method, the metallic bond part for the first electronic component is placed directly against the metallic bond part for the second electronic component, pressure is applied to the first electronic component and the second electronic component and, after metallically joining the above two bond parts, the pressure applied to the first electronic component and the second electronic component is released. In a second process in the manufacturing method, a clamping member affixes the relative positions of the joined first electronic component and second electronic component, and heats the first electronic component and the second electronic component to maintain a specified temperature.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: August 10, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoichiro Kurita
  • Publication number: 20100193884
    Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS device by using metal thermocompression bonding to assemble a reference wafer (100), a bulk MEMS active wafer (200), and a cap wafer (300) to provide a proof mass (200d) formed from the active wafer with bottom and top capacitive sensing electrodes (115, 315) which are hermetically sealed from the ambient environment by sealing ring structures (112/202/200a/212/312 and 116/206/200e/216/316).
    Type: Application
    Filed: February 2, 2009
    Publication date: August 5, 2010
    Inventors: Woo Tae Park, Heinz Loreck, Lisa Karlin
  • Publication number: 20100148367
    Abstract: A semiconductor device includes a die pad having a surface on which a first solder bonding layer is formed, and made of metal; and a semiconductor element fixed on the first solder bonding layer on the die pad by a solder material made mostly of bismuth. The first solder bonding layer is made of a softer material than the solder material, a recess is formed in a part of the first solder bonding layer by pressing the solder material against the first solder bonding layer, and the solder material partially fills the recess.
    Type: Application
    Filed: February 24, 2010
    Publication date: June 17, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Takahiro MATSUO, Akio Furusawa, Shigeaki Sakatani
  • Patent number: 7723839
    Abstract: A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: May 25, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuji Yano, Seiji Ishihara