Abstract: A method for patterning a substrate includes forming a material layer on the substrate; performing a first etching on the material layer to form a pattern; measuring the pattern of the material layer using an optical spectrum metrology tool; determining whether the measuring indicates that the etching step achieved a predefined result; and producing an etching recipe and performing a second etching of the material layer using the etching recipe if the predefined result was not achieved.

Abstract: A method for optimizing a solar cell manufacturing process is described. The method includes determining a reference finger spacing value and a reference bulk lifetime for the solar cell manufacturing process. The method also includes measuring an actual bulk lifetime of a wafer with an in-line measurement tool. The method further includes calculating an optimal finger spacing value with a computer coupled to the in-line measurement tool, the optimal finger spacing value being the product of the reference finger spacing value and a square root of the actual bulk lifetime divided by the square root of the reference bulk lifetime. The method further includes forming a junction on the wafer, and depositing a set of busbars and a set of fingers on the wafer with a metal deposition device, wherein a distance between a first finger and a second finger of the set of fingers is about the optimal finger spacing value.

Abstract: The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask layer (e.g., photoresist) is then formed above the adjustable film layer and is selectively patterned by a reticleless exposure system (e.g., DMD exposure system). The selective patterning subjects different regions of the etch mask layer to varying exposure times dependent upon the thickness of the underlying adjustable film. The more etching needed to provide the underlying film to a nominal thickness, the longer the exposure of the etch mask. Therefore, the resultant etch mask, after exposure, comprises a topology allowing for various degrees of selective etching of the underlying film resulting in a uniform film.

Abstract: A bonded silicon wafer is produced by a method comprising a step of implanting oxygen ions from one surface of a silicon wafer for active layer to form an oxygen ion implanted layer, a step of bonding the one surface of the silicon wafer for active layer to one surface of a silicon wafer for support layer and then conducting a heat treatment for strengthening the bonding to form a silicon wafer composite, a step of polishing a silicon portion at a side of the silicon wafer for active layer in the silicon wafer composite on a rotating platen having a polishing means and stopping the polishing at a time of detecting change of physical properties on the rotating platen resulting from the exposure of at least a part of the oxygen ion implanted layer and a step of removing the oxygen ion implanted layer.

Abstract: A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step.

Abstract: A method for fabricating a plurality of LED chips comprises providing a plurality of LEDs and forming a plurality of spacers each of which is on at least one of the LEDs. Coating the LEDs with a conversion material, each of the spacers reducing the amount of conversion material over its one of the LEDs. This reduction causes the plurality of LED chips to emit a wavelength of light in response to an electrical signal that is within a standard deviation of a target wavelength. LEDs, LED chips and LED chip wafers are fabricated using the method according to the present invention. One embodiment of an LED chip wafer according to the present invention comprises a plurality of LEDs on a wafer and a plurality of a spacers, each of which is on a respective one of the LEDs. A conversion material at least partially covers the LEDs and spacers, with at least some light from the LEDs passing through the conversion material and is converted.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: Methods are disclosed including heating an optical element. An optical material is applied to the heated optical element to provide a conformal layer that is cured via the thermal energy in the heated optical element.

Abstract: In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.

Abstract: A system for recycling includes a processing chamber, a reclamation reservoir and a mixing reservoir. The processing chamber is configured to receive a deposition gas deposited onto a semiconductor layer. The processing chamber has an exhaust to discharge an unused portion of the deposition gas as an effluent gas. The reclamation reservoir is in fluid communication with the processing chamber. The reclamation reservoir is configured to receive and store the effluent gas from the processing chamber. The mixing reservoir is in fluid communication with the reclamation reservoir and the processing chamber. The mixing reservoir is configured to mix the effluent gas with a virgin gas to form a recycled deposition gas. The mixing reservoir supplies the recycled deposition gas to the processing chamber to deposit an additional portion of the semiconductor layer.

Abstract: A semiconductor light emitting device can be configured to maintain high luminance and to suppress the possibility of the occurrence of wire breakage with high quality and reliability. A method for producing such a semiconductor light emitting device with a high process yield is also disclosed. The semiconductor light emitting device can include a sealing member into which a reflective filler can be mixed in such an amount (concentration) range that luminous flux with a predetermined amount can be maintained and the possibility of the occurrence of wire breakage can be lowered. Various sealing members containing a reflective filler with a plurality of concentrations within this range can be prepared in advance.

Abstract: The invention provides a method for recycling/reclaiming a monitor or test wafer and a method for testing an integrated circuit manufacturing process. After a monitor wafer has been used for testing one or more semiconductor wafer processing steps to determine adequacy for use with production wafers, deposited materials and other residues from the tested processing steps are removed, and the stripped wafer is subjected to a thermal anneal to repair defects in its surface and return it to a reusable condition.

Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.

Abstract: A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N?2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses.

Abstract: Provided is a substrate processing apparatus and a method of manufacturing a semiconductor device, which are hard to cause a defect in processing a substrate owing to that a pressure inside a process chamber is not kept constant, and which enable a better processing of a substrate.

Abstract: A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solution, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated.

Abstract: A semiconductor device of the present invention comprises: a substrate; a plurality of wiring layers formed over the substrate; a fuse formed in an uppermost one of the plurality of wiring layers; a first insulating film made up of a single film and formed on the uppermost wiring layer such that the first insulating film is in contact with a surface of the fuse; and a second insulating film formed on the first insulating film; wherein the second insulating film has an opening therein formed above a fuse region of the uppermost wiring layer such that only the first insulating film exists above the fuse region, the fuse region including the fuse and being irradiated with a laser beam when the fuse is blown.

Abstract: An electronic device substrate handling system. The system comprises an electronic device fabrication tool and a mechanical handling structure. The fabrication tool is configured to hold at least one substrate on a mounting body of the tool. The mechanical handling structure is configured to actuate the substrate such that the substrate is transferred to or from the mounting body. The system further comprises a vibration monitor coupled to at least one of the mechanical handling structure, or, the tool. The vibration monitor is configured to measure vibrations of the mechanical handling structure, or, the tool, while said mechanical handling structure is actuating said substrate. The vibration monitor is also configured to convert the measured vibrations into a time-dependent electrical signal.

Abstract: In order to uniformize a film thickness distribution of a layer (e.g., an SOI layer) having predetermined film thickness formed on a surface of a silicon wafer, a processing method includes an oxidation step of forming a natural oxide film on a surface of the SOI layer and an etching step of removing, with etching liquid, the natural oxide film formed in a local thick film portion of the SOI layer while leaving a part (e.g., 1 ? to 2 ?) of the thickness. Since a main surface of the SOI layer is converted into the natural oxide film, the natural oxide film can be easily etched with hydrofluoric acid and etching processing can be locally performed. Therefore, the film thickness distribution of the SOI layer can be accurately uniformized by subjecting the thick film portion of the SOI layer to the etching processing.

Abstract: A semiconductor package comprising a first semiconductor sub-package (40) having a connection face (44) with un-supported connectors (21) depending therefrom arranged to electrically connect a first semiconductor device contained therein to an external circuit, and at least one second semiconductor sub-package (42) also having a connection face (46) with un-supported connectors (25) depending therefrom arranged to electrically connect a second semiconductor device contained therein to an external circuit, the second semiconductor sub-package (42) also having an attachment face (48), on an opposite side thereof from the connection face (46); wherein the second semiconductor sub-package (42) is mounted on the first semiconductor sub-package (40) such that its attachment face (48) is coupled to the connection face (44) of the first semiconductor sub-package (40).

Abstract: A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map.

Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.

Abstract: An electric device having a plurality of nanowires, in which at least one of the nanowires is cut or changed in its electric characteristics so as to have a desired characteristic value of the electric device.

Abstract: A measuring device configured to measure a wave aberration of an optical system to be measured includes a reflection optical element for reflecting light, having passed through a mask and the optical system to be measured, into the optical system to be measured, and a detector for detecting an interference fringe of light having passed through pinholes and openings. The mask has at least three pinhole-opening pairs, each including one pinhole and one opening having a larger diameter than the pinhole that are arranged point-symmetrically, the three pinhole-opening pairs having the common center of symmetry. The light to be measured formed in two of the three pairs is made to interfere with the reference light formed in the remaining pair, or, the light to be measured formed in one of the three pairs is made to interfere with the reference light formed in the other two pairs.

Abstract: A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die.

Abstract: An expansion/contraction measuring apparatus includes a transport section which transports a flexible substrate along a surface of the substrate; a detecting section detecting first and second marks which are formed on the substrate while being separated from each other by a predetermined spacing distance in a transport direction of the substrate and which are moved, in accordance with the transport of the substrate, to first and second detection areas disposed on a transport route for the substrate respectively; a substrate length setting section which sets a length of the substrate along the transport route between the first and second detection areas to a reference length; and a deriving section which derives information about expansion/contraction of the substrate in relation to the transport direction based on a detection result of the first and second marks. Accordingly, the expansion/contraction state of an expandable/contractible substrate is measured highly accurately.

Abstract: A method for manufacturing an optical device, the method includes the steps of: forming a multilayer film, including forming a first mirror above a substrate, forming an active layer above the first mirror, forming a second mirror above the active layer, forming a semiconductor layer on the second mirror, and forming a sacrificial layer on the semiconductor layer; conducting a reflection coefficient examination on the multilayer film; patterning the multilayer film to form a surface-emitting laser section having the first mirror, the active layer and the second mirror, and a diode section having the semiconductor layer; and removing at least a portion of the sacrificial layer to expose at least a portion of an upper surface of the semiconductor layer, wherein an optical film thickness of the semiconductor layer is formed to be an odd multiple or an even multiple of ?/4, where ? is a design wavelength of light emitted by the surface-emitting laser section, and an optical film thickness of the sacrificial layer

Abstract: To enable change of a concentration of atmosphere in a process chamber and realize a plasma reaction process required for manufacturing a liquid crystal device and a semiconductor device with a high yield at a low cost. A new flow rate setting value given to a pressure control type flow rate adjusting device of each constituent gas is a value obtained by calculating back from the process gas concentration after an estimated change under the condition that the total flow rate value is identical before and after the concentration change. A pressure controller of an exhaust pipe is switched from a pressure setting mode to a valve open setting mode only for a predetermined small time from the modification start and receives a valve open setting value obtained experimentally so as to mitigate the pressure fluctuation immediately after the change.

Abstract: A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metallization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.

Abstract: A device and method for managing terahertz and/or microwave radiation are provided. The device can comprise one or more field effect transistors (FETs) that each include at least one channel contact to a central region of the device channel of the FET. The frequency of the radiation managed by the device can be tuned/adjusted by applying a bias voltage to the FET. The radiation can be impinged on the device, and can be detected by measuring a voltage that is induced by the radiation. Further, the device can generate terahertz and/or microwave radiation by, for example, inducing a voltage between two edge contacts on either side of the device channel and applying the voltage to the channel contact.

Abstract: This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer.

Abstract: A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.

Abstract: A method for manufacturing a capacitive semiconductor sensor includes: forming a plurality of circuit chips in a wafer, wherein each circuit chip includes a pad for testing a sensor chip; bonding the sensor chip on each circuit chip with a bump so that the sensor chip is electrically coupled with the circuit chip, wherein each sensor chip is made of semiconductor and has a capacitance changing portion, which is disposed on one side of the sensor chip and has a variable capacitance, wherein the circuit chip detects a capacitance change of the sensor chip, and wherein the one side of the sensor chip faces the circuit chip; testing each sensor chip through the pad; and cutting the wafer into individual circuit chips so that the circuit chip and the sensor chip provide the capacitive semiconductor sensor.

Abstract: A plasma processing apparatus includes a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate a plasma in the process chamber, and a monitoring system including an ion mobility spectrometer configured to monitor a condition of the plasma. A monitoring method including generating a plasma in a process chamber of a plasma processing apparatus, supporting a workpiece on a platen in the process chamber, and monitoring a condition of the plasma with an ion mobility spectrometer is also provided.

Abstract: A plasma ashing apparatus for removing organic matter from a substrate including a low k dielectric, comprising a first gas source; a plasma generating component in fluid communication with the first gas source; a process chamber in fluid communication with the plasma generating component; an exhaust conduit in fluid communication with the process chamber; wherein the exhaust conduit comprises an inlet for a second gas source and an afterburner assembly coupled to the exhaust conduit, wherein the inlet is disposed intermediate to the process chamber and an afterburner assembly, and wherein the afterburner assembly comprises means for generating a plasma within the exhaust conduit with or without introduction of a gas from the second gas source; and an optical emission spectroscopy device coupled to the exhaust conduit comprising collection optics focused within a plasma discharge region of the afterburner assembly.

Abstract: In inspecting for quality of underfill material dispensed in an IC package, a camera image is captured for the IC package having the underfill material dispensed between an IC die and a package substrate. A data processor analyzes the camera image to determine an occurrence of an unacceptable condition of the underfill material. Pre-heating and/or post-heating of the package substrate before and/or after dispensing the underfill material by a contact-less heater ensures uniform spreading of the underfill material.

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract: [Problems] To perform predetermined processing such as annealing and coating application of a semiconductor material with high accuracy on a number of semiconductor formation areas formed over a wide region on a surface of a substrate having elasticity such as a plastic substrate even when the substrate expands and contracts.

Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.

Abstract: The invention relates to a method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask).

Abstract: Light emitting diode (LED) structures are fabricated in wafer scale by mounting singulated LED dies on a carrier wafer or a stretch film, separating the LED dies to create spaces between the LED dies, applying a reflective coating over the LED dies and in the spaces between the LED dies, and separating or breaking the reflective coating in the spaces between the LED dies such that some reflective coating remains on the lateral sides of the LED die. Portions of the reflective coating on the lateral sides of the LED dies may help to control edge emission.

Abstract: Disclosed is a method involving repeatedly measuring a pressure within a flow of processing gas that is provided in a semiconductor processing apparatus for treatment of a semiconductor substrate, such as a semiconductor wafer. The flow of processing gas is made to extend between a surface of the substrate and a surface of a processing body. From the pressure measurements the occurrence of an event that is related to a variation in the position of the substrate's surface relative to the surface of the processing body is determined.

Abstract: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.

Abstract: Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy.

Abstract: A plasma processing method is provided. The method includes providing photon detection sensors for measuring an ultraviolet-light-induced current around circumferential portions of a wafer stage within a plasma chamber. The method also includes providing a semiconductor wafer on the wafer stage and performing plasma processing so as to form an insulating layer the semiconductor wafer or etch an insulating layer formed on the semiconductor wafer.

Abstract: A manufacturing method for a semiconductor device including: determining pattern dependency of a radiation factor of an element forming surface of one wafer having a predetermined pattern formed on the wafer; determining a heating surface of the wafer, based on the pattern dependency of the radiation factor; holding the one wafer having the determined heating surface and another wafer having a determined heating surface, spaced at a predetermined distance in such a manner that non-heating surfaces of the one wafer and the another wafer oppose to each other; and heating the each heating surface of the one wafer and the another wafer.

Abstract: An embodiment of a process of manufacturing an interconnection element for contacting electronic devices is proposed. The process starts with the step of forming a plurality of leads on a main surface of a first substrate; each lead has a first end and a second end. The second end of each lead is coupled with a second substrate. The second substrate and the first substrate are then spaced apart, so as to extend the leads between the first substrate and the second substrate. The process also includes the step of treating the main surface before forming the leads to control an adhesion of the leads on the main surface.

Abstract: A structure to be plated includes a body to be plated 11 on which plating is formed, and plated film thickness determining member 16 opposed to and electrically isolated from the body to be plated 11 through a slit portion 12. The plated film thickness determining member 16 has an islands-shape and is conductive. It is possible to instantly determine whether or not the plating formed on the body to be plated 11 has been formed to a thickness larger than the width W of the slit portion 12 on the spot by determining whether or not plating has grown from the surface of the body to be plated 11 to the plated film thickness determining member 16 through the slit portion 21.

Abstract: A distinguishing size for distinguishing a pseudo defect from a defect caused by a process trouble is stored in a first storage area. Defect data are stored in a second storage area. A processing unit detects a defect on a wafer surface, and stores the defect data in the second storage area. Before a defect detection process is completed for all areas of the wafer surface, a size of a defect detected in a partial area is compared with the distinguishing size stored in the first storage area. If the detected defect has a size equal to or larger than the distinguishing size, an alarm is output through an output unit, whereas if a defect having a size equal to or larger than the distinguishing size is not detected, the defect detection process is executed for the area still not subjected to the defect detection process.

Abstract: A method for correcting a mask pattern used for dry-etching an object with higher accuracy, and for manufacturing an acceleration sensor and an angular velocity sensor. The object is first etched by a dry-etching process using an uncorrected reference mask pattern. Then, distribution of the size of expansion of a tapered portion formed in a surface of the object is measured. Thereafter, the measured distribution is approximated by using a quadratic curve (Y=AX2+B) so as to determine A and B. Consequently, an amount t of correction for the tapered portion, which is expressed by the following equation (1) and related to a width of an opening of the mask pattern in a position at a distance r from a center of the object to be etched, can be set. In this way, the correction for the tapered portion can be carried out.