Abstract: A film thickness measurement method for measuring a change in film thickness of 0.3 ?m or less in a silicon wafer by FTIR, having an auxiliary film formation step for depositing an auxiliary film for measurement on a surface to be measured for the change in film thickness, an auxiliary film thickness measurement step for measuring the film thickness of the auxiliary film, a measurement step for measuring the film thickness of the auxiliary film after the change in film thickness, and a calculation step for calculating a change in film thickness of a back surface deposit from the result of the measurement step and the result of the auxiliary film thickness measurement step.

Abstract: A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

Abstract: A semiconductor laser device manufacturing method includes, sequentially, a first aging step S1, a first inspection step S2, a mounting step S3, a second aging step S4 and a second inspection step S5. Since the first aging step S1 on a semiconductor laser chip with a high-temperature direct current conduction is performed before the mounting step S3, threshold current and drive current of the semiconductor laser chip before mounting can be reduced.

Abstract: A method and a system of alignment of an integrated circuit chip pick-and-place equipment with an origin of a wafer supporting these circuits, comprising optically searching on the wafer at least one reference pattern formed, on manufacturing of the integrated circuits, in a reference chip, the reference pattern being different from optically-recognizable patterns of the other chips.

Abstract: A method of fabricating a light emitting device (LED) includes measuring emission characteristics for a plurality of LED chips configured to emit light of a first color. The plurality of LED chips are sorted based on the measured emission characteristics to provide a plurality of groups respectively including ones of the plurality of LED chips having similar measured emission characteristics. A respective light conversion material is selected for each of the plurality of groups based on the measured emission characteristics of the ones of the plurality of LED chips included therein and a desired color point. The selected light conversion material is configured to absorb at least some of the light of the first color and responsively emit light of a second color.

Abstract: A semiconductor device has a substrate, an insulating interlayer, an interconnect as one example of an electro-conductive pattern, a through-electrode, and a bump as one example of a connection terminal, wherein the insulating interlayer is positioned up above the surface of the substrate, the interconnect is positioned on the surface of the insulating interlayer, the through-electrode extends through the substrate and the insulating interlayer, from the back surface of the former to the surface of the latter, one end of which is connected to the interconnect, and the bump is provided on the back surface side of the substrate, and connected to the other end of the through-electrode.

Abstract: Embodiments of the invention provide a method of determining a storage lifetime of a wafer in a storage environment, the storage environment corresponding to an environment having a first value of temperature and a first value of relative humidity, the wafer having a pre-test value of a first contamination parameter, including the steps of: subjecting the wafer to a test environment for a test period, the test environment includes an environment having a second value of temperature and a second value of relative humidity; subsequently, inspecting the wafer thereby to determine a post-test value of a second contamination parameter, wherein the second value of relative humidity is greater than 30% and the second value of wafer temperature is greater than 30° C.

Abstract: In order to manufacture an epitaxial wafer having satisfactory flatness over its entire surface, epitaxial layers are experimentally grown upon actual wafer samples under various different layer formation conditions, the thickness profiles are measured over the entire surfaces of these wafers before and after growth of the layers, and, from the differences thereof, layer thickness profiles over the entire areas of the epitaxial layers under the various different layer formation conditions are ascertained and stored. Thereafter, the thickness profile of a substrate wafer is measured over its entire area, this is added to each of the layer thickness profiles under the various different layer formation conditions which have been stored, and the planarities of the manufactured wafers which would be manufactured under these various different layer formation conditions are predicted.

Abstract: A method for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs, typically on a wafer, and coating the LEDs with a conversion material so that at least some light from the LEDs passes through the conversion material and is converted. The light emission from the LED chips comprises light from the conversion material, typically in combination with LED light. The emission characteristics of at least some of the LED chips is measured and at least some of the conversion material over the LEDs is removed to alter the emission characteristics of the LED chips. The invention is particularly applicable to fabricating LED chips on a wafer where the LED chips have light emission characteristics that are within a range of target emission characteristics. This target range can fall within an emission region on a CIE curve to reduce the need for binning of the LEDs from the wafer.

Abstract: A plasma oxidation process is performed to form a silicon oxide film on the surface of a target object by use of plasma with an O(1D2) radical density of 1×1012 [cm?3] or more generated from a process gas containing oxygen inside a process chamber of a plasma processing apparatus. During the plasma oxidation process, the O(1D2) radical density in the plasma is measured by a VUV monochromator 63, and a correction is made to the plasma process conditions.

Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

Abstract: Embodiments of controlling a fabrication process using an iso-dense bias are generally described herein. Other embodiments may be described and claimed.

Abstract: A mark forming method includes forming a first mask layer on a semiconductor substrate; forming at least three first patterns having periodicity on the first mask layer; forming a second mask layer on the first mask layer having the first patterns formed thereon; and forming an opening in the second mask layer to cover at least two patterns on ends of the at least three first patterns, thereby forming a mark composed of exposed ones of the first patterns.

Abstract: An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A condition of a single crystal manufacturing step subjected to the Czochralski method applying an initial oxygen concentration, a dopant concentration or resistivity, and a heat treatment condition is determined simply and clearly on the basis of the conditions of a wafer manufacturing step and a device step so as to obtain a silicon wafer having a desired gettering capability. A manufacturing method of a silicon substrate which is manufactured from a silicon single crystal grown by the CZ method and provided for manufacturing a solid-state imaging device is provided. The internal state of the silicon substrate, which depends on the initial oxygen concentration, the carbon concentration, the resistivity, and the pulling condition of the silicon substrate, is determined by comparing a white spot condition representing upper and lower limits of the density of white spots as device characteristics with the measured density of white spots.

Abstract: Methods of packaging a semiconductor light emitting device include dispensing a first quantity of encapsulant material into a cavity including the light emitting device. The first quantity of encapsulant material in the cavity is treated to form a hardened upper surface thereof having a selected shape. A luminescent conversion element is provided on the upper surface of the treated first quantity of encapsulant material. The luminescent conversion element includes a wavelength conversion material and has a thickness at a middle region of the cavity greater than proximate a sidewall of the cavity.

Abstract: A method of manufacturing a semiconductor device involves the steps of: forming a plurality of product formation areas each having a circuit and a plurality of first electrode pads over a main surface of a semiconductor wafer; arranging a plurality of second electrode pads with larger pitches than the first electrode pads in each of the product formation areas; segmenting the semiconductor wafer to separate the plural product formation areas and provide a plurality of semiconductor devices each having the circuit, the plural first electrode pads and the plural second electrode pads on a first surface; and cleaning foreign matter off the first surface of the semiconductor device after the step of segmenting the semiconductor devices.

Abstract: A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step.

Abstract: The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer.

Abstract: A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer and a substrate. In one example, the conductive layer serves as programmable material, that in a low impedance state, electrically couples conductive structures. A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.

Abstract: A semiconductor device fabrication apparatus includes a load lock chamber, a loading assembly in the load lock chamber, and an ion implantation target chamber that is hermetically connected to the load lock chamber. The load lock chamber is configured to store a plurality of wafer plates. Each wafer plate respectively includes at least one semiconductor wafer thereon. The ion implantation target chamber is configured to implant an ion species into a semiconductor wafer on a currently loaded wafer plate. The loading assembly is also configured to load a next one of the plurality of wafer plates from the load lock chamber into the ion implantation target chamber. The loading assembly may be configured to load the next wafer plate from the load lock chamber into the ion implantation target chamber while substantially maintaining a current temperature within the ion implantation target chamber and/or without depressurizing the ion implantation target chamber. Related methods and devices are also discussed.

Abstract: A substrate processing method in a processing chamber, has: accommodating a substrate into a processing chamber; and processing the substrate in the processing chamber on the basis of a correlation of a preset temperature of a heating device, a flow rate of fluid supplied by a cooling device and a temperature deviation between the center side of the substrate accommodated in the processing chamber and the outer peripheral side of the substrate while the substrate accommodated in the processing chamber is optically heated from an outer periphery side of the substrate at a corrected preset temperature by the heating device and the fluid is supplied to the outside of the processing chamber at the flow rate based on the correlation concerned to cool the outer peripheral side of the substrate by the cooling device.

Abstract: A system and method for monitoring a manufacturing process are provided. A wafer is provided. Process parameters of a manufacturing machine are in-situ measured and recorded if the wafer is processed in the manufacturing machine. A wafer measured value of the wafer is measured after the wafer has been processed. The process parameters are transformed into a process summary value. A two dimensional orthogonal chart with a first axis representing the wafer measured value and a second axis representing the process summary value is provided. The two dimensional orthogonal chart includes a close-loop control limit. A visualized point representing the wafer measured value and the process summary value is displayed on the two dimensional orthogonal chart.

Abstract: A plasma doping method and a plasma doping apparatus, having a superior in-plane uniformity of an amorphous layer formed on a sample surface, are provided. In the plasma doping method by which plasma is generated within a vacuum chamber, and impurity ions contained in the plasma are caused to collide with the surface of the sample so as to quality-change the surface of the sample into an amorphous state thereof, a plasma irradiation time is adjusted in order to improve an in-plane uniformity. If the plasma irradiation time becomes excessively short, then a fluctuation of the plasma is transferred to depths of an amorphous layer formed on a silicon substrate, so that the in-plane uniformity is deteriorated. On the other hand, if the irradiation time becomes excessively long, then an effect for sputtering the surface of the silicon substrate by using the plasma becomes dominant, then the in-plane uniformity is deteriorated.

Abstract: A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top surface of the through-wafer via are substantially coplanar. The through-wafer via is at least adjacent to the plurality of conductive patterns. The semiconductor chip further includes a plurality of bonding pads on a surface of the semiconductor chip, each being connected to one of the plurality of conductive patterns.

Abstract: A template for forming solder bumps includes a transparent substrate on which a plurality of cavities is formed at an upper surface portion thereof, and a light-reflective layer and a protective layer formed on a lower surface of the transparent substrate. When a nozzle makes close contact with the template to inject a molten solder into the cavities, damage to the template may be prevented by the light-reflective layer and the protective layer, and thus the lifetime of the template may be increased. An inspection process on the solder bumps, which are formed in the cavities of the template, may be easily performed by analyzing light reflected by the light-reflective layer.

Abstract: The present invention provides an evaluation method for evaluating whether a light-emitting element material to be evaluated is suitable for a host material or a guest material. By carrying out a first step of measuring absorption intensity of a light-emitting element material and a second step of irradiating the light-emitting element material with light for a predetermined period of time, repeatedly; thereby a change in absorption intensity with time is evaluated so that whether the light-emitting material is suitable for a host material or a guest material can be distinguished. The light emitted to the light-emitting element material preferably has a wavelength component which is absorbed by a skeleton which contributes to excitation of the light-emitting element material.

Abstract: A method for applying a heat insulation layer (11, 12, 13) or a metallic protective layer to a thermally stressed component (200) having a basic material (10) in order to eliminate local damage (14) or an untreated place in the coating, includes, in a first step, pretreating the local damage (14) or untreated place, and, in a second step, applying layers (17, 18) necessary for eliminating the local damage (14) or untreated place. A markedly improved lifetime of the processed component can be achieved in that, within the first step, the edge regions (15) of the layers (11, 12, 13) ending at the local damage (14) or untreated place are processed so that they form uniformly sloped and terrace-shaped edge regions (16). Furthermore, a precharacterization of the entire coated region of the operationally stressed component or critical places by FSECT makes it possible to reduce the risk in terms of otherwise overlooked layer regions, the remaining lifetime of which would not persist for the following operating time.

Abstract: A semiconductor chip includes a semiconductor chip region provided with a plurality of internal circuits, and a plurality of electrode pads provided proximate to an outer edge of the semiconductor chip region and each electrically connected to any one of the plurality of internal circuits. The plurality of electrode pads include: a long pad including a probe region with which a probe is brought into contact, and a bonding region provided in a position different from a position of the probe region, for bonding a wire; and a short pad for high frequency, which is formed to have a smaller pad area compared with the long pad and inputs/outputs a high frequency signal by employing a structure including the bonding region but the probe region.

Abstract: The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer sequences. The S-D creation procedures can be performed using S-D processing elements, the S-D evaluation procedures can be performed using S-D evaluation elements, and S-D transfer sequences can be performed using site-dependent transfer subsystems. Site-dependent data can be stored in site-dependent libraries and/or databases.

Abstract: Methods for assembling multilayer semiconductor device packages are disclosed. A base substrate having device mounting sites is provided. A number of semiconductor devices are connected to the device mounting sites. Upper boards are attached to the base substrate and over each of the coupled devices. The method includes steps of testing one or more of the base substrate, semiconductor device, or upper board, prior to operably connecting one to another.

Abstract: An imaging apparatus is provided in which a plurality of pixels, each having a conversion element and a thin-film transistor, are arranged in a two-dimensional fashion on an insulating substrate; the photoelectric conversion element is arranged over the thin-film transistor, with an insulating film, which serves as an interlayer insulating film, inserted between the conversion element and the thin-film transistor; and by way of a contact hole portion provided in the insulating film, the source electrode or the drain electrode of the thin-film transistor and the photoelectric conversion element are connected with each other. The imaging apparatus has a pixel in which the contact hole portion is removed through a laser-beam irradiation so that the connection portion between the conversion element and a conductive layer, which serves as the source electrode or the drain electrode of the thin-film transistor, is discontinued.

Abstract: A computer-implemented method for inspection of a sample includes defining a plurality of locations on a surface of the sample, irradiating the surface at each of the locations with a beam of X-rays, and measuring an angular distribution of the X-rays that are emitted from the surface responsively to the beam, so as to produce a respective plurality of X-ray spectra. The X-ray spectra are analyzed to produce respective figures-of-merit indicative of a measurement quality of the X-ray spectra at the respective locations. One or more locations are selected out of the plurality of locations responsively to the figures-of-merit, and a property of the sample is estimated using the X-ray spectra measured at the selected locations.

Abstract: One embodiment of the present invention relates to a method of forming an integrated circuit, comprising forming an STI structure in a semiconductor body, the STI structure having a divot characteristic, performing scatterometry on the STI structure and obtaining signature spectra associated therewith, and continuing fabrication of the integrated circuit when the obtained signature spectra satisfies a predetermined performance specification.

Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.

Abstract: It has been found that for silicon integrated circuits having capacitor structures or other p-n junctions structure at a technology node of 32 nm or smaller, photovoltaic induced corrosion of copper in the metallization stack is a significant issue. Thus processing conditions or device configurations are employed that preclude such corrosion. In one embodiment photovoltaic induced corrosion is monitored to prevent completion of devices with corrosion defects.

Abstract: A substrate processing apparatus has: a process chamber in which a substrate is processed; a heating device that optically heats the substrate accommodated in the process chamber from an outer periphery side of the substrate; a cooling device that cools the outer periphery side of the substrate by flowing a fluid in a vicinity of an outer periphery of the substrate optically heated by the heating device; a temperature detection portion that detects a temperature inside the process chamber; and a heating control portion that controls the heating device and the cooling device in such a manner so as to provide a temperature difference between a center portion of the substrate and an end portion of the substrate while maintaining a temperature at the center portion at a pre-determined temperature according to the temperature detected by the temperature detection portion.

Abstract: A method of fabricating a TFT using dual or multiple gates, and a TFT having superior characteristics and uniformity by providing a method of fabricating a TFT using dual or multiple gates by calculating the probability including Nmax, the maximum number of crystal grain boundaries in active channel regions according to the length of the active channels, and adjusting a gap between the active channels capable of synchronizing the number of the crystal grain boundaries in each active channel region of the TFT using the dual or multiple gates in the case where Gs, the size of crystal grains of polycrystalline silicon forming a TFT substrate, ? angle in which “primary” crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the gates, the width of the active channels and the length of the active channels are determined.

Abstract: A method of manufacturing a semiconductor light emitting device. The method includes: mounting a semiconductor light emitting element on a flat substrate; covering the semiconductor light emitting element on the flat substrate by a cover layer in a domed shape to form a light emitting device, the cover layer including at least a phosphor layer and a coating resin layer that are laminated in order, so as to fill around the semiconductor light emitting element; measuring an emission condition of the light emitting device; and forming a convex lens unit on the outermost of the coating resin layer using a liquid droplet discharging apparatus to adjust an emission distribution of the light emitting device based on the measured emission condition.

Abstract: The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region and an activation region arranged within the substrate. The activation region is generally in contact with the conduction region and is configured to change its electrical resistance when activation occurs.

Abstract: A thermal stress resistance evaluating method of a semiconductor device includes: forming a test circuit on a corner of each of unit regions arranged on a wafer in an array arrangement; forming a TEG chip by dicing a TEG chip region which is determined by grouping at least two of the unit regions in a predetermined shape; assembling a packaged TEG chip from the TEG chip; and executing a temperature cycling test on the packaged TEG chip by using the test circuit on the TEG chip. According to such a configuration, by adjusting the predetermined shape, the packaged TEG chip of various sizes can be formed in accordance with the design of the product chip size.

Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a method of forming a material layer. The method includes providing a semiconductor wafer, forming a first portion of a material layer over the semiconductor wafer at a first pressure, and forming a second portion of the material layer over the first portion of the material layer at a second pressure, the second pressure being less than the first pressure.

Abstract: According to various exemplary embodiments, a spring device that includes a substrate, a self-releasing layer provided over the substrate and a stressed-metal layer provided over the self-releasing layer is disclosed, wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer. Moreover, a method of manufacturing a spring device, according to various exemplary embodiments, includes providing a substrate, providing a self-releasing layer over the substrate and providing a stressed-metal layer over the self-releasing layer wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer is also disclosed in this invention.

Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

Abstract: Substrate shrinkage that occurs during manufacture of an electronic assembly is compensated for by the incorporation of a horizontal line, having a plurality of vertical graduations, across a horizontal portion of a substrate and a vertical line, having a plurality of horizontal graduations, across a vertical portion of the substrate. The substrate is then cured and an amount of substrate shrinkage is determined, based upon a location change in the graduations of the horizontal and vertical lines. In this manner, solder can be properly provided on solder pads of the substrate responsive to the amount of substrate shrinkage. As such, electronic components can be properly mounted to the solder pads of the substrate.

Abstract: Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion species to non-impurity-based ion species in a plasma generated by the plasma doping process and a ratio of each impurity-based ion species to a total impurity-based ion species in the plasma are directly measured. The ratios may be directly measured by ion mass spectroscopy. The total ion dose and the ratios are used to determine the total impurity dose. The apparatus includes an ion detector, an ion mass spectrometer, a dosimeter, and software.

Abstract: A laser crystallization apparatus which capable of correcting both shift in imaging position caused by thermal lens effect of the imaging optical system and shift due to flatness of the substrate comprises an crystallization optical system which irradiates laser light to a thin film disposed on the substrate to melt and crystallize an irradiated region of the thin film, the apparatus includes a measurement light source which is disposed outside a light path of the laser light, and which emits measurement light being illuminated the irradiated region of the thin film, and a substrate height correction system which illuminates the thin film with the measurement light through an imaging optical system in the crystallization optical system, and which detects the reflected measurement light from the thin film.

Abstract: A method and apparatus are provided to control the radial or non-radial temperature distribution across a substrate during processing to compensate for non-uniform effects, including radial and angular non-uniformities arising from system variations, or process variations, or both. The temperature is controlled, preferably dynamically, by flowing backside gas differently across different areas on a wafer supporting chuck to vary heat conduction across the wafer. Backside gas flow, of helium, for example, is dynamically varied across the chuck to control the uniformity of processing of the wafer. Ports in the support are grouped, and gas to or from the groups is separately controlled by different valves responsive to a controller that controls gas pressure in each of the areas to spatially and preferably dynamically control wafer temperature to compensate for system and process non-uniformities.

Abstract: A process of manufacturing a semiconductor device utilizing a thermo-chemical reaction is started based on preset initial settings, a state function of an atmosphere associated with the thermo-chemical reaction is measured, a state of the atmosphere and a change thereof are analyzed based on measurement data obtained by the measurement, and then, analysis data obtained by the analysis is fed back to a manufacturing process.